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PAR/PDR registers

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folkert van heusden 2022-03-22 08:57:07 +01:00
parent 8f5a05d0d2
commit 1a3bc28d95
1 changed files with 114 additions and 40 deletions
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154
bus.cpp
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@ -93,36 +93,66 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev)
} }
/// MMU /// /// MMU ///
if (a >= 0172300 && a < 0172320) { if (a >= 0172200 && a < 0172220) {
uint16_t t = pages[run_mode][((a & 017) >> 1)].pdr; uint16_t t = pages[001][((a & 017) >> 1)].pdr;
D(fprintf(stderr, "read PDR for %d: %o\n", (a & 017) >> 1, t);) D(fprintf(stderr, "read supervisor I PDR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0172220 && a < 0172240) {
uint16_t t = pages[001][((a & 017) >> 1) + 8].pdr;
D(fprintf(stderr, "read supervisor D PDR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0172240 && a < 0172260) {
uint16_t t = pages[001][((a & 017) >> 1)].par;
D(fprintf(stderr, "read supervisor I PAR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0172260 && a < 0172300) {
uint16_t t = pages[001][((a & 017) >> 1) + 8].par;
D(fprintf(stderr, "read supervisor D PAR for %d: %o\n", (a & 017) >> 1, t);)
return t; return t;
} }
if (a >= 0172300 && a < 0172320) {
uint16_t t = pages[000][((a & 017) >> 1)].pdr;
D(fprintf(stderr, "read kernel I PDR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0172320 && a < 0172340) {
uint16_t t = pages[000][((a & 017) >> 1) + 8].pdr;
D(fprintf(stderr, "read kernel D PDR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0172340 && a < 0172360) { if (a >= 0172340 && a < 0172360) {
uint16_t t = pages[run_mode][((a & 017) >> 1)].par; uint16_t t = pages[000][((a & 017) >> 1)].par;
D(fprintf(stderr, "read PAR for %d: %o\n", (a & 017) >> 1, t);) D(fprintf(stderr, "read kernel I PAR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0172360 && a < 0172400) {
uint16_t t = pages[000][((a & 017) >> 1) + 8].par;
D(fprintf(stderr, "read kernel D PAR for %d: %o\n", (a & 017) >> 1, t);)
return t; return t;
} }
if (a >= 0177600 && a < 0177620) { if (a >= 0177600 && a < 0177620) {
uint16_t t = pages[run_mode][((a & 017) >> 1) + 8].pdr; uint16_t t = pages[003][((a & 017) >> 1)].pdr;
D(fprintf(stderr, "read PDR for %d: %o\n", ((a & 017) >> 1) + 8, t);) D(fprintf(stderr, "read userspace I PDR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0177620 && a < 0177640) {
uint16_t t = pages[003][((a & 017) >> 1) + 8].pdr;
D(fprintf(stderr, "read userspace D PDR for %d: %o\n", (a & 017) >> 1, t);)
return t; return t;
} }
if (a >= 0177640 && a < 0177660) { if (a >= 0177640 && a < 0177660) {
uint16_t t = pages[run_mode][((a & 017) >> 1) + 8].par; uint16_t t = pages[003][((a & 017) >> 1)].par;
D(fprintf(stderr, "read PAR for %d: %o\n", ((a & 017) >> 1) + 8, t);) D(fprintf(stderr, "read userspace I PAR for %d: %o\n", (a & 017) >> 1, t);)
return t; return t;
} }
if (a >= 0177660 && a < 0177700) {
if (a == 0177572) { uint16_t t = pages[003][((a & 017) >> 1) + 8].par;
uint16_t t = ((c -> getRunMode() ? 0b11 : 0b00) << 5) | // kernel == 00 D(fprintf(stderr, "read userspace D PAR for %d: %o\n", (a & 017) >> 1, t);)
((c -> getRegister(7) >> 13) << 1) | // page nr
0 // MMU enabled
;
D(fprintf(stderr, "read MMU SR0 %o\n", t);)
return t; return t;
} }
/////////// ///////////
@ -178,9 +208,13 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev)
} }
} }
else { else {
if (a == 0177572) { // MMR0 if (a == 0177572) {
D(fprintf(stderr, "read MMR0\n");) uint16_t t = (run_mode << 5) | // kernel == 00
return MMR0; ((c -> getRegister(7) >> 13) << 1) | // page nr
0 // MMU enabled
;
D(fprintf(stderr, "read MMU SR0 %o\n", t);)
return t;
} }
if (a == 0177574) { // MMR1 if (a == 0177574) { // MMR1
@ -247,10 +281,6 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev)
if (tty_ && a >= PDP11TTY_BASE && a < PDP11TTY_END) if (tty_ && a >= PDP11TTY_BASE && a < PDP11TTY_END)
return word_mode ? tty_ -> readByte(a) : tty_ -> readWord(a); return word_mode ? tty_ -> readByte(a) : tty_ -> readWord(a);
if (a & 1)
D(fprintf(stderr, "bus::readWord: odd address UNHANDLED %o\n", a);)
D(fprintf(stderr, "UNHANDLED read %o(%c)\n", a, word_mode ? 'B' : ' ');)
// LO size register field must be all 1s, so subtract 1 // LO size register field must be all 1s, so subtract 1
constexpr const uint32_t system_size = n_pages * 8192 - 4096 - 1; constexpr const uint32_t system_size = n_pages * 8192 - 4096 - 1;
@ -260,6 +290,11 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev)
if (a == 0177760) // system size LO if (a == 0177760) // system size LO
return system_size & 65535; return system_size & 65535;
if (a & 1)
D(fprintf(stderr, "bus::readWord: odd address UNHANDLED %o\n", a);)
else
D(fprintf(stderr, "UNHANDLED read %o(%c)\n", a, word_mode ? 'B' : ' ');)
// c -> busError(); // c -> busError();
return -1; return -1;
@ -442,30 +477,69 @@ uint16_t bus::write(const uint16_t a, const bool word_mode, uint16_t value, cons
} }
/// MMU /// /// MMU ///
if (a >= 0172200 && a < 0172220) {
uint16_t t = pages[001][((a & 017) >> 1)].pdr = value;
D(fprintf(stderr, "write supervisor I PDR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0172220 && a < 0172240) {
uint16_t t = pages[001][((a & 017) >> 1) + 8].pdr = value;
D(fprintf(stderr, "write supervisor D PDR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0172240 && a < 0172260) {
uint16_t t = pages[001][((a & 017) >> 1)].par = value;
D(fprintf(stderr, "write supervisor I PAR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0172260 && a < 0172300) {
uint16_t t = pages[001][((a & 017) >> 1) + 8].par = value;
D(fprintf(stderr, "write supervisor D PAR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0172300 && a < 0172320) { if (a >= 0172300 && a < 0172320) {
D(fprintf(stderr, "write set PDR for %d to %o\n", (a & 017) >> 1, value);) uint16_t t = pages[000][((a & 017) >> 1)].pdr = value;
pages[run_mode][((a & 017) >> 1)].pdr = value; D(fprintf(stderr, "write kernel I PDR for %d: %o\n", (a & 017) >> 1, t);)
return value; return t;
}
if (a >= 0172320 && a < 0172340) {
uint16_t t = pages[000][((a & 017) >> 1) + 8].pdr = value;
D(fprintf(stderr, "write kernel D PDR for %d: %o\n", (a & 017) >> 1, t);)
return t;
} }
if (a >= 0172340 && a < 0172360) { if (a >= 0172340 && a < 0172360) {
D(fprintf(stderr, "write set PAR for %d to %o\n", (a & 017) >> 1, value);) uint16_t t = pages[000][((a & 017) >> 1)].par = value;
pages[run_mode][((a & 017) >> 1)].par = value; D(fprintf(stderr, "write kernel I PAR for %d: %o\n", (a & 017) >> 1, t);)
return value; return t;
}
if (a >= 0172360 && a < 0172400) {
uint16_t t = pages[000][((a & 017) >> 1) + 8].par = value;
D(fprintf(stderr, "write kernel D PAR for %d: %o\n", (a & 017) >> 1, t);)
return t;
} }
if (a >= 0117600 && a < 0117620) { if (a >= 0177600 && a < 0177620) {
D(fprintf(stderr, "write set PDR for %d to %o\n", ((a & 017) >> 1) + 8, value);) uint16_t t = pages[003][((a & 017) >> 1)].pdr = value;
pages[run_mode][((a & 017) >> 1) + 8].pdr = value; D(fprintf(stderr, "write userspace I PDR for %d: %o\n", (a & 017) >> 1, t);)
return value; return t;
} }
if (a >= 0177620 && a < 0177640) {
if (a >= 0117640 && a < 0177660) { uint16_t t = pages[003][((a & 017) >> 1) + 8].pdr = value;
D(fprintf(stderr, "write set PAR for %d to %o\n", ((a & 017) >> 1) + 8, value);) D(fprintf(stderr, "write userspace D PDR for %d: %o\n", (a & 017) >> 1, t);)
pages[run_mode][((a & 017) >> 1) + 8].par = value; return t;
return value;
} }
if (a >= 0177640 && a < 0177660) {
uint16_t t = pages[003][((a & 017) >> 1)].par = value;
D(fprintf(stderr, "write userspace I PAR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
if (a >= 0177660 && a < 0177700) {
uint16_t t = pages[003][((a & 017) >> 1) + 8].par = value;
D(fprintf(stderr, "write userspace D PAR for %d: %o\n", (a & 017) >> 1, t);)
return t;
}
////
if (a == 0177746) { // cache control register if (a == 0177746) { // cache control register
// FIXME // FIXME