PAR/PDR registers
This commit is contained in:
folkert van heusden
parent
8f5a05d0d2
commit
1a3bc28d95
1 changed files with 114 additions and 40 deletions
154
bus.cpp
154
bus.cpp
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@ -93,36 +93,66 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev)
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}
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/// MMU ///
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if (a >= 0172300 && a < 0172320) {
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uint16_t t = pages[run_mode][((a & 017) >> 1)].pdr;
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D(fprintf(stderr, "read PDR for %d: %o\n", (a & 017) >> 1, t);)
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if (a >= 0172200 && a < 0172220) {
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uint16_t t = pages[001][((a & 017) >> 1)].pdr;
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D(fprintf(stderr, "read supervisor I PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172220 && a < 0172240) {
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uint16_t t = pages[001][((a & 017) >> 1) + 8].pdr;
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D(fprintf(stderr, "read supervisor D PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172240 && a < 0172260) {
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uint16_t t = pages[001][((a & 017) >> 1)].par;
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D(fprintf(stderr, "read supervisor I PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172260 && a < 0172300) {
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uint16_t t = pages[001][((a & 017) >> 1) + 8].par;
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D(fprintf(stderr, "read supervisor D PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172300 && a < 0172320) {
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uint16_t t = pages[000][((a & 017) >> 1)].pdr;
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D(fprintf(stderr, "read kernel I PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172320 && a < 0172340) {
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uint16_t t = pages[000][((a & 017) >> 1) + 8].pdr;
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D(fprintf(stderr, "read kernel D PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172340 && a < 0172360) {
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uint16_t t = pages[run_mode][((a & 017) >> 1)].par;
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D(fprintf(stderr, "read PAR for %d: %o\n", (a & 017) >> 1, t);)
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uint16_t t = pages[000][((a & 017) >> 1)].par;
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D(fprintf(stderr, "read kernel I PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172360 && a < 0172400) {
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uint16_t t = pages[000][((a & 017) >> 1) + 8].par;
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D(fprintf(stderr, "read kernel D PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0177600 && a < 0177620) {
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uint16_t t = pages[run_mode][((a & 017) >> 1) + 8].pdr;
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D(fprintf(stderr, "read PDR for %d: %o\n", ((a & 017) >> 1) + 8, t);)
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uint16_t t = pages[003][((a & 017) >> 1)].pdr;
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D(fprintf(stderr, "read userspace I PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0177620 && a < 0177640) {
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uint16_t t = pages[003][((a & 017) >> 1) + 8].pdr;
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D(fprintf(stderr, "read userspace D PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0177640 && a < 0177660) {
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uint16_t t = pages[run_mode][((a & 017) >> 1) + 8].par;
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D(fprintf(stderr, "read PAR for %d: %o\n", ((a & 017) >> 1) + 8, t);)
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uint16_t t = pages[003][((a & 017) >> 1)].par;
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D(fprintf(stderr, "read userspace I PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a == 0177572) {
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uint16_t t = ((c -> getRunMode() ? 0b11 : 0b00) << 5) | // kernel == 00
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((c -> getRegister(7) >> 13) << 1) | // page nr
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0 // MMU enabled
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;
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D(fprintf(stderr, "read MMU SR0 %o\n", t);)
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if (a >= 0177660 && a < 0177700) {
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uint16_t t = pages[003][((a & 017) >> 1) + 8].par;
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D(fprintf(stderr, "read userspace D PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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///////////
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@ -178,9 +208,13 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev)
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}
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}
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else {
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if (a == 0177572) { // MMR0
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D(fprintf(stderr, "read MMR0\n");)
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return MMR0;
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if (a == 0177572) {
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uint16_t t = (run_mode << 5) | // kernel == 00
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((c -> getRegister(7) >> 13) << 1) | // page nr
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0 // MMU enabled
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;
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D(fprintf(stderr, "read MMU SR0 %o\n", t);)
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return t;
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}
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if (a == 0177574) { // MMR1
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@ -247,10 +281,6 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev)
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if (tty_ && a >= PDP11TTY_BASE && a < PDP11TTY_END)
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return word_mode ? tty_ -> readByte(a) : tty_ -> readWord(a);
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if (a & 1)
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D(fprintf(stderr, "bus::readWord: odd address UNHANDLED %o\n", a);)
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D(fprintf(stderr, "UNHANDLED read %o(%c)\n", a, word_mode ? 'B' : ' ');)
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// LO size register field must be all 1s, so subtract 1
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constexpr const uint32_t system_size = n_pages * 8192 - 4096 - 1;
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@ -260,6 +290,11 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev)
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if (a == 0177760) // system size LO
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return system_size & 65535;
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if (a & 1)
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D(fprintf(stderr, "bus::readWord: odd address UNHANDLED %o\n", a);)
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else
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D(fprintf(stderr, "UNHANDLED read %o(%c)\n", a, word_mode ? 'B' : ' ');)
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// c -> busError();
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return -1;
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@ -442,30 +477,69 @@ uint16_t bus::write(const uint16_t a, const bool word_mode, uint16_t value, cons
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}
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/// MMU ///
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if (a >= 0172200 && a < 0172220) {
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uint16_t t = pages[001][((a & 017) >> 1)].pdr = value;
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D(fprintf(stderr, "write supervisor I PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172220 && a < 0172240) {
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uint16_t t = pages[001][((a & 017) >> 1) + 8].pdr = value;
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D(fprintf(stderr, "write supervisor D PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172240 && a < 0172260) {
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uint16_t t = pages[001][((a & 017) >> 1)].par = value;
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D(fprintf(stderr, "write supervisor I PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172260 && a < 0172300) {
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uint16_t t = pages[001][((a & 017) >> 1) + 8].par = value;
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D(fprintf(stderr, "write supervisor D PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172300 && a < 0172320) {
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D(fprintf(stderr, "write set PDR for %d to %o\n", (a & 017) >> 1, value);)
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pages[run_mode][((a & 017) >> 1)].pdr = value;
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return value;
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uint16_t t = pages[000][((a & 017) >> 1)].pdr = value;
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D(fprintf(stderr, "write kernel I PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172320 && a < 0172340) {
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uint16_t t = pages[000][((a & 017) >> 1) + 8].pdr = value;
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D(fprintf(stderr, "write kernel D PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172340 && a < 0172360) {
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D(fprintf(stderr, "write set PAR for %d to %o\n", (a & 017) >> 1, value);)
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pages[run_mode][((a & 017) >> 1)].par = value;
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return value;
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uint16_t t = pages[000][((a & 017) >> 1)].par = value;
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D(fprintf(stderr, "write kernel I PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172360 && a < 0172400) {
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uint16_t t = pages[000][((a & 017) >> 1) + 8].par = value;
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D(fprintf(stderr, "write kernel D PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0117600 && a < 0117620) {
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D(fprintf(stderr, "write set PDR for %d to %o\n", ((a & 017) >> 1) + 8, value);)
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pages[run_mode][((a & 017) >> 1) + 8].pdr = value;
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return value;
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if (a >= 0177600 && a < 0177620) {
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uint16_t t = pages[003][((a & 017) >> 1)].pdr = value;
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D(fprintf(stderr, "write userspace I PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0117640 && a < 0177660) {
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D(fprintf(stderr, "write set PAR for %d to %o\n", ((a & 017) >> 1) + 8, value);)
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pages[run_mode][((a & 017) >> 1) + 8].par = value;
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return value;
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if (a >= 0177620 && a < 0177640) {
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uint16_t t = pages[003][((a & 017) >> 1) + 8].pdr = value;
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D(fprintf(stderr, "write userspace D PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0177640 && a < 0177660) {
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uint16_t t = pages[003][((a & 017) >> 1)].par = value;
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D(fprintf(stderr, "write userspace I PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0177660 && a < 0177700) {
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uint16_t t = pages[003][((a & 017) >> 1) + 8].par = value;
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D(fprintf(stderr, "write userspace D PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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////
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if (a == 0177746) { // cache control register
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// FIXME
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