All write-access to 0177776 should not affect the flag registers
This commit is contained in:
folkert van heusden
parent
5a77604127
commit
1e748d3d37
2 changed files with 195 additions and 110 deletions
300
cpu.cpp
300
cpu.cpp
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@ -138,12 +138,17 @@ void cpu::setRegisterLowByte(const int nr, const bool word_mode, const uint16_t
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}
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}
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void cpu::put_result(const uint16_t a, const uint8_t dst_mode, const uint8_t dst_reg, const bool word_mode, const uint16_t value)
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bool cpu::put_result(const uint16_t a, const uint8_t dst_mode, const uint8_t dst_reg, const bool word_mode, const uint16_t value)
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{
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if (dst_mode == 0)
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if (dst_mode == 0) {
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setRegisterLowByte(dst_reg, word_mode, value);
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else
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b->write(a, word_mode, value, false);
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return true;
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}
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b->write(a, word_mode, value, false);
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return a != 0177776;
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}
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uint16_t cpu::addRegister(const int nr, const bool prev_mode, const uint16_t value)
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@ -326,23 +331,27 @@ uint16_t cpu::getGAM(const uint8_t mode, const uint8_t reg, const bool word_mode
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return -1;
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}
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void cpu::putGAM(const uint8_t mode, const int reg, const bool word_mode, const uint16_t value, bool const prev_mode)
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bool cpu::putGAM(const uint8_t mode, const int reg, const bool word_mode, const uint16_t value, bool const prev_mode)
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{
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uint16_t next_word = 0;
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int addr = -1;
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switch(mode) {
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case 0:
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setRegister(reg, prev_mode, value);
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break;
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case 1:
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b -> write(getRegister(reg, prev_mode), word_mode, value, false);
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addr = getRegister(reg, prev_mode);
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b -> write(addr, word_mode, value, false);
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break;
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case 2:
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b -> write(getRegister(reg, prev_mode), word_mode, value, false);
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addr = getRegister(reg, prev_mode);
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b -> write(addr, word_mode, value, false);
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addRegister(reg, prev_mode, !word_mode || reg == 7 || reg == 6 ? 2 : 1);
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break;
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case 3:
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b -> write(b -> readWord(getRegister(reg, prev_mode)), word_mode, value, false);
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addr = b -> readWord(getRegister(reg, prev_mode));
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b -> write(addr, word_mode, value, false);
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addRegister(reg, prev_mode, 2);
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break;
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case 4:
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@ -351,23 +360,28 @@ void cpu::putGAM(const uint8_t mode, const int reg, const bool word_mode, const
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break;
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case 5:
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addRegister(reg, prev_mode, -2);
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b -> write(b -> readWord(getRegister(reg, prev_mode)), word_mode, value, false);
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addr = b -> readWord(getRegister(reg, prev_mode));
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b -> write(addr, word_mode, value, false);
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break;
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case 6:
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next_word = b -> readWord(getPC());
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addRegister(7, prev_mode, 2);
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b -> write(getRegister(reg, prev_mode) + next_word, word_mode, value, false);
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addr = (getRegister(reg, prev_mode) + next_word) & 0xffff;
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b -> write(addr, word_mode, value, false);
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break;
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case 7:
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next_word = b -> readWord(getPC());
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addRegister(7, prev_mode, 2);
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b -> write(b -> readWord(getRegister(reg, prev_mode) + next_word), word_mode, value, false);
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addr = b -> readWord(getRegister(reg, prev_mode) + next_word);
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b -> write(addr, word_mode, value, false);
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break;
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default:
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// error
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break;
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}
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return addr == -1 || addr != 0177776;
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}
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uint16_t cpu::getGAMAddress(const uint8_t mode, const int reg, const bool word_mode, const bool prev_mode)
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@ -429,21 +443,16 @@ bool cpu::double_operand_instructions(const uint16_t instr)
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const uint8_t dst_mode = (dst >> 3) & 7;
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const uint8_t dst_reg = dst & 7;
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bool set_flags = true;
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switch(operation) {
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case 0b001: { // MOV/MOVB Move Word/Byte
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bool set_flags = true;
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addToMMR1(src_mode, src_reg, word_mode);
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if (word_mode && dst_mode == 0)
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setRegister(dst_reg, false, int8_t(src_value)); // int8_t: sign extension
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else {
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uint16_t addr = getGAMAddress(dst_mode, dst_reg, word_mode, false);
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set_flags = addr != 0177776;
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b->write(addr, word_mode, src_value, false);
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}
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else
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set_flags = putGAM(dst_mode, dst_reg, word_mode, src_value, false);
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addToMMR1(dst_mode, dst_reg, word_mode);
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@ -492,11 +501,11 @@ bool cpu::double_operand_instructions(const uint16_t instr)
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uint16_t result = b->read(a, word_mode, false) & ~src_value;
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put_result(a, dst_mode, dst_reg, word_mode, result);
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setPSW_n(SIGN(result, word_mode));
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setPSW_z(IS_0(result, word_mode));
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setPSW_v(false);
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if (put_result(a, dst_mode, dst_reg, word_mode, result)) {
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setPSW_n(SIGN(result, word_mode));
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setPSW_z(IS_0(result, word_mode));
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setPSW_v(false);
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}
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return true;
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}
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@ -506,11 +515,11 @@ bool cpu::double_operand_instructions(const uint16_t instr)
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uint16_t result = b->read(a, word_mode, false) | src_value;
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put_result(a, dst_mode, dst_reg, word_mode, result);
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setPSW_n(SIGN(result, word_mode));
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setPSW_z(IS_0(result, word_mode));
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setPSW_v(false);
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if (put_result(a, dst_mode, dst_reg, word_mode, result)) {
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setPSW_n(SIGN(result, word_mode));
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setPSW_z(IS_0(result, word_mode));
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setPSW_v(false);
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}
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return true;
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}
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@ -522,19 +531,29 @@ bool cpu::double_operand_instructions(const uint16_t instr)
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int16_t dst_value = b->readWord(dst_addr);
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int16_t result = 0;
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bool set_flags = dst_addr != 0177776;
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if (instr & 0x8000) {
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result = (dst_value - ssrc_value) & 0xffff;
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setPSW_v(sign(ssrc_value) != sign(dst_value) && sign(ssrc_value) == sign(result));
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setPSW_c(uint16_t(dst_value) < uint16_t(ssrc_value));
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if (set_flags) {
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setPSW_v(sign(ssrc_value) != sign(dst_value) && sign(ssrc_value) == sign(result));
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setPSW_c(uint16_t(dst_value) < uint16_t(ssrc_value));
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}
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}
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else {
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result = (dst_value + ssrc_value) & 0xffff;
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setPSW_v(sign(ssrc_value) == sign(dst_value) && sign(dst_value) != sign(result));
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setPSW_c(uint16_t(result) < uint16_t(ssrc_value));
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if (set_flags) {
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setPSW_v(sign(ssrc_value) == sign(dst_value) && sign(dst_value) != sign(result));
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setPSW_c(uint16_t(result) < uint16_t(ssrc_value));
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}
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}
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setPSW_n(result < 0);
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setPSW_z(result == 0);
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if (set_flags) {
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setPSW_n(result < 0);
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setPSW_z(result == 0);
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}
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if (dst_mode == 0)
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setRegister(dst_reg, false, result);
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@ -684,17 +703,23 @@ bool cpu::additional_double_operand_instructions(const uint16_t instr)
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}
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case 4: { // XOR (word only)
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uint16_t a = getGAMAddress(dst_mode, dst_reg, false, false);
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uint16_t vl = b->read(a, false, false) ^ getRegister(reg);
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uint16_t a = getGAMAddress(dst_mode, dst_reg, false, false);
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uint16_t vl = b->read(a, false, false) ^ getRegister(reg);
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bool set_flags = true;
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if (dst_mode == 0)
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putGAM(dst_mode, dst_reg, false, vl, false);
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else
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else {
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b->write(a, false, vl, false);
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setPSW_n(vl & 0x8000);
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setPSW_z(vl == 0);
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setPSW_v(false);
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set_flags = a != 0177776;
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}
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if (set_flags) {
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setPSW_n(vl & 0x8000);
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setPSW_z(vl == 0);
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setPSW_v(false);
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}
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return true;
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}
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@ -722,6 +747,7 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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const uint8_t dst_mode = (dst >> 3) & 7;
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const uint8_t dst_reg = dst & 7;
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const bool word_mode = !!(instr & 0x8000);
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bool set_flags = true;
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switch(opcode) {
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case 0b00000011: { // SWAB
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@ -743,13 +769,17 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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v = ((v & 0xff) << 8) | (v >> 8);
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set_flags = a != 0177776;
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b->writeWord(a, v);
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}
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setPSW_n(v & 0x80);
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setPSW_z((v & 0xff) == 0);
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setPSW_v(false);
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setPSW_c(false);
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if (set_flags) {
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setPSW_n(v & 0x80);
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setPSW_z((v & 0xff) == 0);
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setPSW_v(false);
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setPSW_c(false);
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}
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}
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break;
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@ -768,13 +798,17 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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else {
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uint16_t a = getGAMAddress(dst_mode, dst_reg, word_mode, false);
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set_flags = a != 0177776;
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b -> write(a, word_mode, 0, false);
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}
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setPSW_n(false);
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setPSW_z(true);
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setPSW_v(false);
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setPSW_c(false);
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if (set_flags) {
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setPSW_n(false);
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setPSW_z(true);
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setPSW_v(false);
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setPSW_c(false);
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}
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break;
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}
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@ -804,10 +838,14 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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else
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v ^= 0xffff;
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setPSW_n(SIGN(v, word_mode));
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setPSW_z(IS_0(v, word_mode));
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setPSW_v(false);
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setPSW_c(true);
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bool set_flags = a != 0177776;
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if (set_flags) {
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setPSW_n(SIGN(v, word_mode));
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setPSW_z(IS_0(v, word_mode));
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setPSW_v(false);
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setPSW_c(true);
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}
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b->write(a, word_mode, v, false);
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}
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@ -833,9 +871,13 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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uint16_t v = b -> read(a, word_mode, false);
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int32_t vl = (v + 1) & (word_mode ? 0xff : 0xffff);
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setPSW_n(SIGN(vl, word_mode));
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setPSW_z(IS_0(vl, word_mode));
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setPSW_v(word_mode ? vl == 0x80 : v == 0x8000);
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bool set_flags = a != 0177776;
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if (set_flags) {
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setPSW_n(SIGN(vl, word_mode));
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setPSW_z(IS_0(vl, word_mode));
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setPSW_v(word_mode ? vl == 0x80 : v == 0x8000);
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}
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b->write(a, word_mode, vl, false);
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}
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@ -862,9 +904,13 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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uint16_t v = b -> read(a, word_mode, false);
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int32_t vl = (v - 1) & (word_mode ? 0xff : 0xffff);
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setPSW_n(SIGN(vl, word_mode));
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setPSW_z(IS_0(vl, word_mode));
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setPSW_v(word_mode ? vl == 0x7f : vl == 0x7fff);
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bool set_flags = a != 0177776;
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if (set_flags) {
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setPSW_n(SIGN(vl, word_mode));
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setPSW_z(IS_0(vl, word_mode));
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setPSW_v(word_mode ? vl == 0x7f : vl == 0x7fff);
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}
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b->write(a, word_mode, vl, false);
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}
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@ -893,10 +939,14 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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b->write(a, word_mode, v, false);
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setPSW_n(SIGN(v, word_mode));
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setPSW_z(IS_0(v, word_mode));
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setPSW_v(word_mode ? (v & 0xff) == 0x80 : v == 0x8000);
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setPSW_c(v);
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bool set_flags = a != 0177776;
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if (set_flags) {
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setPSW_n(SIGN(v, word_mode));
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setPSW_z(IS_0(v, word_mode));
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setPSW_v(word_mode ? (v & 0xff) == 0x80 : v == 0x8000);
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setPSW_c(v);
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}
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}
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break;
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@ -927,10 +977,14 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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b->write(a, word_mode, v, false);
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setPSW_n(SIGN(v, word_mode));
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setPSW_z(IS_0(v, word_mode));
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setPSW_v((word_mode ? (vo & 0xff) == 0x80 : vo == 0x8000) && org_c);
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setPSW_c((word_mode ? (vo & 0xff) == 0xff : vo == 0xffff) && org_c);
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bool set_flags = a != 0177776;
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if (set_flags) {
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setPSW_n(SIGN(v, word_mode));
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setPSW_z(IS_0(v, word_mode));
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setPSW_v((word_mode ? (vo & 0xff) == 0x80 : vo == 0x8000) && org_c);
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setPSW_c((word_mode ? (vo & 0xff) == 0xff : vo == 0xffff) && org_c);
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}
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}
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break;
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@ -961,12 +1015,16 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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b->write(a, word_mode, v, false);
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setPSW_n(SIGN(v, word_mode));
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setPSW_z(IS_0(v, word_mode));
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setPSW_v(word_mode? (v & 0xff) == 0x80 : v == 0x8000); // FIXME? v/c flags?
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bool set_flags = a != 0177776;
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if (IS_0(vo, word_mode) && org_c)
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setPSW_c(true);
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if (set_flags) {
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setPSW_n(SIGN(v, word_mode));
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setPSW_z(IS_0(v, word_mode));
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setPSW_v(word_mode? (v & 0xff) == 0x80 : v == 0x8000); // FIXME? v/c flags?
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if (IS_0(vo, word_mode) && org_c)
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setPSW_c(true);
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}
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}
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break;
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}
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@ -1017,10 +1075,14 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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b->write(a, word_mode, temp, false);
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setPSW_c(new_carry);
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setPSW_n(SIGN(temp, word_mode));
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setPSW_z(IS_0(temp, word_mode));
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setPSW_v(getPSW_c() ^ getPSW_n());
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bool set_flags = a != 0177776;
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if (set_flags) {
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setPSW_c(new_carry);
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setPSW_n(SIGN(temp, word_mode));
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setPSW_z(IS_0(temp, word_mode));
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setPSW_v(getPSW_c() ^ getPSW_n());
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}
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}
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break;
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}
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@ -1064,10 +1126,14 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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b->write(a, word_mode, temp, false);
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setPSW_c(new_carry);
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setPSW_n(SIGN(temp, word_mode));
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setPSW_z(IS_0(temp, word_mode));
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setPSW_v(getPSW_c() ^ getPSW_n());
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bool set_flags = a != 0177776;
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if (set_flags) {
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setPSW_c(new_carry);
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setPSW_n(SIGN(temp, word_mode));
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setPSW_z(IS_0(temp, word_mode));
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setPSW_v(getPSW_c() ^ getPSW_n());
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}
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}
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break;
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}
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@ -1119,9 +1185,13 @@ bool cpu::single_operand_instructions(const uint16_t instr)
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b->write(a, word_mode, v, false);
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||||
setPSW_n(SIGN(v, word_mode));
|
||||
setPSW_z(IS_0(v, word_mode));
|
||||
setPSW_v(getPSW_n() ^ getPSW_c());
|
||||
bool set_flags = a != 0177776;
|
||||
|
||||
if (set_flags) {
|
||||
setPSW_n(SIGN(v, word_mode));
|
||||
setPSW_z(IS_0(v, word_mode));
|
||||
setPSW_v(getPSW_n() ^ getPSW_c());
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
|
@ -1146,10 +1216,14 @@ bool cpu::single_operand_instructions(const uint16_t instr)
|
|||
uint16_t vl = b -> read(a, word_mode, false);
|
||||
uint16_t v = (vl << 1) & (word_mode ? 0xff : 0xffff);
|
||||
|
||||
setPSW_n(SIGN(v, word_mode));
|
||||
setPSW_z(IS_0(v, word_mode));
|
||||
setPSW_c(SIGN(vl, word_mode));
|
||||
setPSW_v(getPSW_n() ^ getPSW_c());
|
||||
bool set_flags = a != 0177776;
|
||||
|
||||
if (set_flags) {
|
||||
setPSW_n(SIGN(v, word_mode));
|
||||
setPSW_z(IS_0(v, word_mode));
|
||||
setPSW_c(SIGN(vl, word_mode));
|
||||
setPSW_v(getPSW_n() ^ getPSW_c());
|
||||
}
|
||||
|
||||
b->write(a, word_mode, v, false);
|
||||
}
|
||||
|
|
@ -1168,9 +1242,13 @@ bool cpu::single_operand_instructions(const uint16_t instr)
|
|||
// reed from previous space
|
||||
uint16_t v = b -> read(a, false, true);
|
||||
|
||||
setPSW_n(SIGN(v, false));
|
||||
setPSW_z(v == 0);
|
||||
setPSW_v(false);
|
||||
bool set_flags = a != 0177776;
|
||||
|
||||
if (set_flags) {
|
||||
setPSW_n(SIGN(v, false));
|
||||
setPSW_z(v == 0);
|
||||
setPSW_v(false);
|
||||
}
|
||||
|
||||
// put on current stack
|
||||
pushStack(v);
|
||||
|
|
@ -1188,11 +1266,16 @@ bool cpu::single_operand_instructions(const uint16_t instr)
|
|||
// retrieve word from '15/14'-stack
|
||||
uint16_t v = popStack();
|
||||
|
||||
setPSW_n(SIGN(v, false));
|
||||
setPSW_z(v == 0);
|
||||
setPSW_v(false);
|
||||
|
||||
uint16_t a = getGAMAddress(dst_mode, dst_reg, false, false);
|
||||
|
||||
bool set_flags = a != 0177776;
|
||||
|
||||
if (set_flags) {
|
||||
setPSW_n(SIGN(v, false));
|
||||
setPSW_z(v == 0);
|
||||
setPSW_v(false);
|
||||
}
|
||||
|
||||
b -> write(a, false, v, true); // put in '13/12' address space
|
||||
|
||||
break;
|
||||
|
|
@ -1205,28 +1288,29 @@ bool cpu::single_operand_instructions(const uint16_t instr)
|
|||
|
||||
case 0b000110111: // MFPS (get PSW to something) / SXT
|
||||
if (word_mode) { // MFPS
|
||||
uint16_t temp = psw & 0xff;
|
||||
|
||||
setPSW_z(temp == 0);
|
||||
setPSW_v(false);
|
||||
|
||||
if (temp & 128) {
|
||||
setPSW_n(true);
|
||||
uint16_t temp = psw & 0xff;
|
||||
bool extend_b7 = temp & 128;
|
||||
|
||||
if (extend_b7)
|
||||
temp |= 0xff00;
|
||||
}
|
||||
|
||||
putGAM(dst_mode, dst_reg, word_mode, temp, false);
|
||||
set_flags = putGAM(dst_mode, dst_reg, word_mode, temp, false);
|
||||
|
||||
if (set_flags) {
|
||||
setPSW_z(temp == 0);
|
||||
setPSW_v(false);
|
||||
setPSW_n(!extend_b7);
|
||||
}
|
||||
}
|
||||
else { // SXT
|
||||
uint16_t a = getGAMAddress(dst_mode, dst_reg, word_mode, false);
|
||||
|
||||
int32_t vl = -getPSW_n();
|
||||
|
||||
setPSW_z(getPSW_n() == false);
|
||||
setPSW_v(false);
|
||||
|
||||
put_result(a, dst_mode, dst_reg, word_mode, vl);
|
||||
if (put_result(a, dst_mode, dst_reg, word_mode, vl)) {
|
||||
setPSW_z(getPSW_n() == false);
|
||||
setPSW_v(false);
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
|
|
|
|||
5
cpu.h
5
cpu.h
|
|
@ -43,7 +43,8 @@ private:
|
|||
void addToMMR1(const uint8_t mode, const uint8_t reg, const bool word_mode);
|
||||
uint16_t getGAMAddress(const uint8_t mode, const int reg, const bool word_mode, const bool MF_MT);
|
||||
uint16_t getGAM(const uint8_t mode, const uint8_t reg, const bool word_mode, const bool MF_MT);
|
||||
void putGAM(const uint8_t mode, const int reg, const bool word_mode, const uint16_t value, const bool MF_FT);
|
||||
// returns false when flag registers should not be updated
|
||||
bool putGAM(const uint8_t mode, const int reg, const bool word_mode, const uint16_t value, const bool MF_FT);
|
||||
|
||||
bool double_operand_instructions(const uint16_t instr);
|
||||
bool additional_double_operand_instructions(const uint16_t instr);
|
||||
|
|
@ -130,5 +131,5 @@ public:
|
|||
uint16_t getRegister(const int nr) const { return getRegister(nr, false); } // FIXME remove
|
||||
void setRegister(const int nr, const uint16_t v) { setRegister(nr, false, v); } // FIXME remove
|
||||
|
||||
void put_result(const uint16_t a, const uint8_t dst_mode, const uint8_t dst_reg, const bool word_mode, const uint16_t value);
|
||||
bool put_result(const uint16_t a, const uint8_t dst_mode, const uint8_t dst_reg, const bool word_mode, const uint16_t value);
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue