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RTI/RTT shall not change the PSW in user/supervisor mode

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This commit is contained in:
folkert van heusden 2022-06-18 18:05:31 +02:00
parent 51670ef199
commit 31edf022cc
2 changed files with 20 additions and 12 deletions
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30
cpu.cpp
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@ -246,17 +246,15 @@ int cpu::getPSW_spl() const
return (psw >> 5) & 7;
}
void cpu::setPSW(const uint16_t v, const bool limited)
void cpu::setPSW(uint16_t v, const bool limited)
{
if (limited) {
psw |= v & 0174000; // current & previous mode can only be increased, 11 can only be set
v &= 0174037;
psw &= 0174000; // retain upper 5 bit
psw |= v & ~0174000;
}
else {
psw = v;
v |= psw & 0174340;
}
psw = v;
}
bool cpu::check_queued_interrupts()
@ -1548,10 +1546,15 @@ bool cpu::misc_operations(const uint16_t instr)
case 0b0000000000000001: // WAIT
return true;
case 0b0000000000000010: // RTI
case 0b0000000000000010: { // RTI
setPC(popStack());
setPSW(popStack(), !!((getPSW() >> 12) & 3));
uint16_t replacement_psw = popStack();
setPSW(replacement_psw, true);
return true;
}
case 0b0000000000000011: // BPT
trap(014);
@ -1561,10 +1564,15 @@ bool cpu::misc_operations(const uint16_t instr)
trap(020);
return true;
case 0b0000000000000110: // RTT
case 0b0000000000000110: { // RTT
setPC(popStack());
setPSW(popStack(), !!((getPSW() >> 12) & 3));
uint16_t replacement_psw = popStack();
setPSW(replacement_psw, true);
return true;
}
case 0b0000000000000111: // MFPT
if (emulateMFPT)

2
cpu.h
View file

@ -118,7 +118,7 @@ public:
void setBitPSW(const int bit, const bool v);
uint16_t getPSW() const { return psw; }
void setPSW(const uint16_t v, const bool limited);
void setPSW(uint16_t v, const bool limited);
uint16_t getStackLimitRegister() { return stackLimitRegister; }
void setStackLimitRegister(const uint16_t v) { stackLimitRegister = v; }