diff --git a/cpu.cpp b/cpu.cpp index e5a3cfb..1f01104 100644 --- a/cpu.cpp +++ b/cpu.cpp @@ -41,6 +41,7 @@ void cpu::emulation_start() instruction_count = 0; running_since = get_ms(); + wait_time = 0; } bool cpu::check_breakpoint() @@ -75,7 +76,7 @@ std::tuple cpu::get_mips_rel_speed() { uint64_t instr_count = get_instructions_executed_count(); - uint32_t t_diff = get_ms() - running_since; // TODO fix this because we now implement WAIT where it sits idle + uint32_t t_diff = get_ms() - running_since - (wait_time / 1000); double mips = instr_count / (1000.0 * t_diff); @@ -1563,6 +1564,7 @@ bool cpu::misc_operations(const uint16_t instr) case 0b0000000000000001: // WAIT { + uint64_t start = get_us(); #if defined(BUILD_FOR_RP2040) uint8_t rc = 0; xQueueReceive(qi_q, &rc, 0); @@ -1571,6 +1573,9 @@ bool cpu::misc_operations(const uint16_t instr) qi_cv.wait(lck); #endif + uint64_t end = get_us(); + + wait_time += end - start; // used for MIPS calculation } DOLOG(debug, false, "WAIT returned"); diff --git a/cpu.h b/cpu.h index 9683dda..e06f125 100644 --- a/cpu.h +++ b/cpu.h @@ -31,15 +31,16 @@ class cpu private: uint16_t regs0_5[2][6]; // R0...5, selected by bit 11 in PSW, uint16_t sp[3 + 1]; // stackpointers, MF../MT.. select via 12/13 from PSW, others via 14/15 - uint16_t pc { 0 }; - uint16_t psw { 0 }; - uint16_t fpsr { 0 }; - uint16_t stackLimitRegister { 0377 }; - int processing_trap_depth { 0 }; - uint64_t instruction_count { 0 }; - uint64_t running_since { 0 }; - bool it_is_a_trap { false }; - uint64_t mtpi_count { 0 }; + uint16_t pc { 0 }; + uint16_t psw { 0 }; + uint16_t fpsr { 0 }; + uint16_t stackLimitRegister { 0377 }; + int processing_trap_depth { 0 }; + uint64_t instruction_count { 0 }; + uint64_t running_since { 0 }; + uint64_t wait_time { 0 }; + bool it_is_a_trap { false }; + uint64_t mtpi_count { 0 }; // level, vector std::map > queued_interrupts;