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changes to make it compile on ESP32 (does currently not support "std::optional")

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This commit is contained in:
folkert van heusden 2022-04-11 14:06:35 +02:00
parent f5bea4b5dc
commit 517f2afb9b
3 changed files with 61 additions and 59 deletions
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10
ESP32/platformio.ini
View file

@ -2,13 +2,9 @@
default_envs = serial32 default_envs = serial32
src_dir = . src_dir = .
[env]
framework = arduino
lib_ldf_mode = deep+
lib_deps =
src_filter = +<*> -<.git/> -<.svn/> -<example/> -<examples/> -<test/> -<tests/> -<build> -<player.cpp>
[env:serial32] [env:serial32]
lib_ldf_mode = deep+
src_filter = +<*> -<.git/> -<.svn/> -<example/> -<examples/> -<test/> -<tests/> -<build> -<player.cpp>
platform = espressif32 platform = espressif32
board = wemos_d1_mini32 board = wemos_d1_mini32
framework = arduino framework = arduino
@ -16,5 +12,5 @@ monitor_speed = 115200
upload_speed = 1000000 upload_speed = 1000000
lib_deps = greiman/SdFat@^2.1.2 lib_deps = greiman/SdFat@^2.1.2
adafruit/Adafruit NeoPixel@^1.10.4 adafruit/Adafruit NeoPixel@^1.10.4
build_flags = -std=c++17 -Ofast -DESP32=1 build_flags = -std=gnu++17 -Ofast -DESP32=1
build_unflags = -std=gnu++11 -Os build_unflags = -std=gnu++11 -Os

100
cpu.cpp
View file

@ -1433,7 +1433,7 @@ void cpu::trap(const uint16_t vector, const int new_ipl)
D(fprintf(stderr, "TRAP %o: PC is now %06o, PSW is now %06o\n", vector, getPC(), new_psw);) D(fprintf(stderr, "TRAP %o: PC is now %06o, PSW is now %06o\n", vector, getPC(), new_psw);)
} }
std::tuple<std::string, int, std::optional<uint16_t>, uint16_t> cpu::addressing_to_string(const uint8_t mode_register, const uint16_t pc, const bool word_mode) const cpu::operand_parameters cpu::addressing_to_string(const uint8_t mode_register, const uint16_t pc, const bool word_mode) const
{ {
assert(mode_register < 64); assert(mode_register < 64);
@ -1453,43 +1453,43 @@ std::tuple<std::string, int, std::optional<uint16_t>, uint16_t> cpu::addressing_
switch(mode_register >> 3) { switch(mode_register >> 3) {
case 0: case 0:
return { reg_name, 2, { }, uint16_t(getRegister(reg) & mask) }; return { reg_name, 2, -1, uint16_t(getRegister(reg) & mask) };
case 1: case 1:
return { format("(%s)", reg_name.c_str()), 2, { }, uint16_t(b->readWord(getRegister(reg)) & mask) }; return { format("(%s)", reg_name.c_str()), 2, -1, uint16_t(b->readWord(getRegister(reg)) & mask) };
case 2: case 2:
if (reg == 7) if (reg == 7)
return { format("#%06o", next_word), 4, next_word, uint16_t(next_word & mask) }; return { format("#%06o", next_word), 4, int(next_word), uint16_t(next_word & mask) };
return { format("(%s)+", reg_name.c_str()), 2, { }, uint16_t(b->readWord(getRegister(reg)) & mask) }; return { format("(%s)+", reg_name.c_str()), 2, -1, uint16_t(b->readWord(getRegister(reg)) & mask) };
case 3: case 3:
if (reg == 7) if (reg == 7)
return { format("@#%06o", next_word), 4, next_word, uint16_t(b->readWord(next_word) & mask) }; return { format("@#%06o", next_word), 4, int(next_word), uint16_t(b->readWord(next_word) & mask) };
return { format("@(%s)+", reg_name.c_str()), 2, { }, uint16_t(b->readWord(b->readWord(getRegister(reg))) & mask) }; return { format("@(%s)+", reg_name.c_str()), 2, -1, uint16_t(b->readWord(b->readWord(getRegister(reg))) & mask) };
case 4: case 4:
return { format("-(%s)", reg_name.c_str()), 2, { }, uint16_t(b->readWord(getRegister(reg) - (word_mode == false || reg >= 6 ? 2 : 1)) & mask) }; return { format("-(%s)", reg_name.c_str()), 2, -1, uint16_t(b->readWord(getRegister(reg) - (word_mode == false || reg >= 6 ? 2 : 1)) & mask) };
case 5: case 5:
return { format("@-(%s)", reg_name.c_str()), 2, { }, uint16_t(b->readWord(b->readWord(getRegister(reg) - 2)) & mask) }; return { format("@-(%s)", reg_name.c_str()), 2, -1, uint16_t(b->readWord(b->readWord(getRegister(reg) - 2)) & mask) };
case 6: case 6:
if (reg == 7) if (reg == 7)
return { format("%06o", (pc + next_word + 2) & 65535), 4, next_word, uint16_t(b->readWord(getRegister(reg) + next_word) & mask) }; return { format("%06o", (pc + next_word + 2) & 65535), 4, int(next_word), uint16_t(b->readWord(getRegister(reg) + next_word) & mask) };
return { format("%o(%s)", next_word, reg_name.c_str()), 4, next_word, uint16_t(b->readWord(getRegister(reg) + next_word) & mask) }; return { format("%o(%s)", next_word, reg_name.c_str()), 4, int(next_word), uint16_t(b->readWord(getRegister(reg) + next_word) & mask) };
case 7: case 7:
if (reg == 7) if (reg == 7)
return { format("@%06o", next_word), 4, next_word, uint16_t(b->readWord(b->readWord(getRegister(reg) + next_word)) & mask) }; return { format("@%06o", next_word), 4, int(next_word), uint16_t(b->readWord(b->readWord(getRegister(reg) + next_word)) & mask) };
return { format("@%o(%s)", next_word, reg_name.c_str()), 4, next_word, uint16_t(b->readWord(b->readWord(getRegister(reg) + next_word)) & mask) }; return { format("@%o(%s)", next_word, reg_name.c_str()), 4, int(next_word), uint16_t(b->readWord(b->readWord(getRegister(reg) + next_word)) & mask) };
} }
return { "??", 0, { }, 0123456 }; return { "??", 0, -1, 0123456 };
} }
std::map<std::string, std::vector<std::string> > cpu::disassemble(const uint16_t addr) const std::map<std::string, std::vector<std::string> > cpu::disassemble(const uint16_t addr) const
@ -1521,18 +1521,18 @@ std::map<std::string, std::vector<std::string> > cpu::disassemble(const uint16_t
// TODO: 100000011 // TODO: 100000011
if (do_opcode == 0b000) { if (do_opcode == 0b000) {
auto dst_text = addressing_to_string(dst_register, (pc + 2) & 65535, word_mode); auto dst_text { addressing_to_string(dst_register, (pc + 2) & 65535, word_mode) };
auto next_word = std::get<2>(dst_text); auto next_word = dst_text.instruction_part;
if (next_word.has_value()) if (next_word != -1)
instruction_words.push_back(next_word.value()); instruction_words.push_back(next_word);
work_values.push_back(std::get<3>(dst_text)); work_values.push_back(dst_text.work_value);
// single_operand_instructions // single_operand_instructions
switch(so_opcode) { switch(so_opcode) {
case 0b00000011: case 0b00000011:
text = "SWAB " + std::get<0>(dst_text); text = "SWAB " + dst_text.operand;
break; break;
case 0b000101000: case 0b000101000:
@ -1605,17 +1605,17 @@ std::map<std::string, std::vector<std::string> > cpu::disassemble(const uint16_t
} }
if (text.empty() && name.empty() == false) if (text.empty() && name.empty() == false)
text = name + word_mode_str + space + std::get<0>(dst_text); text = name + word_mode_str + space + dst_text.operand;
} }
else if (do_opcode == 0b111) { else if (do_opcode == 0b111) {
std::string src_text = format("R%d", (instruction >> 6) & 7); std::string src_text = format("R%d", (instruction >> 6) & 7);
auto dst_text = addressing_to_string(dst_register, (pc + 2) & 65535, word_mode); auto dst_text { addressing_to_string(dst_register, (pc + 2) & 65535, word_mode) };
auto next_word = std::get<2>(dst_text); auto next_word = dst_text.instruction_part;
if (next_word.has_value()) if (next_word != -1)
instruction_words.push_back(next_word.value()); instruction_words.push_back(next_word);
work_values.push_back(std::get<3>(dst_text)); work_values.push_back(dst_text.work_value);
switch(ado_opcode) { // additional double operand switch(ado_opcode) { // additional double operand
case 0: case 0:
@ -1644,7 +1644,7 @@ std::map<std::string, std::vector<std::string> > cpu::disassemble(const uint16_t
} }
if (text.empty() && name.empty() == false) if (text.empty() && name.empty() == false)
text = name + space + src_text + comma + std::get<0>(dst_text); text = name + space + src_text + comma + dst_text.operand;
} }
else { else {
switch(do_opcode) { switch(do_opcode) {
@ -1677,24 +1677,24 @@ std::map<std::string, std::vector<std::string> > cpu::disassemble(const uint16_t
} }
// source // source
auto src_text = addressing_to_string(src_register, (pc + 2) & 65535, word_mode); auto src_text { addressing_to_string(src_register, (pc + 2) & 65535, word_mode) };
auto next_word_src = std::get<2>(src_text); auto next_word_src = src_text.instruction_part;
if (next_word_src.has_value()) if (next_word_src != -1)
instruction_words.push_back(next_word_src.value()); instruction_words.push_back(next_word_src);
work_values.push_back(std::get<3>(src_text)); work_values.push_back(src_text.work_value);
// destination // destination
auto dst_text = addressing_to_string(dst_register, (pc + std::get<1>(src_text)) & 65535, word_mode); auto dst_text { addressing_to_string(dst_register, (pc + src_text.length) & 65535, word_mode) };
auto next_word_dst = std::get<2>(dst_text); auto next_word_dst = dst_text.instruction_part;
if (next_word_dst.has_value()) if (next_word_dst != -1)
instruction_words.push_back(next_word_dst.value()); instruction_words.push_back(next_word_dst);
work_values.push_back(std::get<3>(dst_text)); work_values.push_back(dst_text.work_value);
text = name + word_mode_str + space + std::get<0>(src_text) + comma + std::get<0>(dst_text); text = name + word_mode_str + space + src_text.operand + comma + dst_text.operand;
} }
if (text.empty()) { // conditional branch instructions if (text.empty()) { // conditional branch instructions
@ -1837,27 +1837,27 @@ std::map<std::string, std::vector<std::string> > cpu::disassemble(const uint16_t
text = format("TRAP %o", instruction & 255); text = format("TRAP %o", instruction & 255);
if ((instruction & ~0b111111) == 0b0000000001000000) { if ((instruction & ~0b111111) == 0b0000000001000000) {
auto dst_text = addressing_to_string(dst_register, (pc + 2) & 65535, word_mode); auto dst_text { addressing_to_string(dst_register, (pc + 2) & 65535, word_mode) };
auto next_word = std::get<2>(dst_text); auto next_word = dst_text.instruction_part;
if (next_word.has_value()) if (next_word != -1)
instruction_words.push_back(next_word.value()); instruction_words.push_back(next_word);
work_values.push_back(std::get<3>(dst_text)); work_values.push_back(dst_text.work_value);
text = std::string("JMP ") + std::get<0>(dst_text); text = std::string("JMP ") + dst_text.operand;
} }
if ((instruction & 0b1111111000000000) == 0b0000100000000000) { if ((instruction & 0b1111111000000000) == 0b0000100000000000) {
auto dst_text = addressing_to_string(dst_register, (pc + 2) & 65535, word_mode); auto dst_text { addressing_to_string(dst_register, (pc + 2) & 65535, word_mode) };
auto next_word = std::get<2>(dst_text); auto next_word = dst_text.instruction_part;
if (next_word.has_value()) if (next_word != -1)
instruction_words.push_back(next_word.value()); instruction_words.push_back(next_word);
work_values.push_back(std::get<3>(dst_text)); work_values.push_back(dst_text.work_value);
text = format("JSR R%d,", src_register & 7) + std::get<0>(dst_text); text = format("JSR R%d,", src_register & 7) + dst_text.operand;
} }
if ((instruction & 0b1111111111111000) == 0b0000000010000000) if ((instruction & 0b1111111111111000) == 0b0000000010000000)

10
cpu.h
View file

@ -4,7 +4,6 @@
#include <assert.h> #include <assert.h>
#include <map> #include <map>
#include <optional>
#include <set> #include <set>
#include <stdint.h> #include <stdint.h>
#include <vector> #include <vector>
@ -51,7 +50,14 @@ private:
bool condition_code_operations(const uint16_t instr); bool condition_code_operations(const uint16_t instr);
bool misc_operations(const uint16_t instr); bool misc_operations(const uint16_t instr);
std::tuple<std::string, int, std::optional<uint16_t>, uint16_t> addressing_to_string(const uint8_t mode_register, const uint16_t pc, const bool word_mode) const; struct operand_parameters {
std::string operand;
int length;
int instruction_part;
uint16_t work_value;
};
operand_parameters addressing_to_string(const uint8_t mode_register, const uint16_t pc, const bool word_mode) const;
std::map<std::string, std::vector<std::string> > disassemble(const uint16_t addr) const; std::map<std::string, std::vector<std::string> > disassemble(const uint16_t addr) const;
void disassemble(void) const; void disassemble(void) const;