Code-cleanup (PAR/PDR read/write helper methods)
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parent
2717799df4
commit
55ad46c55c
2 changed files with 89 additions and 148 deletions
232
bus.cpp
232
bus.cpp
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@ -51,13 +51,35 @@ void bus::init()
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MMR3 = 0;
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}
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uint16_t bus::read_pdr(const uint32_t a, const int run_mode, const bool word_mode, const bool peek_only)
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{
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bool is_11_34 = c->get_34();
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int page = (a >> 1) & 7;
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bool is_d = is_11_34 ? false : (a & 16);
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uint16_t t = pages[run_mode][is_d][page].pdr;
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DOLOG(debug, !peek_only, "read run-mode %d: %c PDR for %d: %o", run_mode, is_d ? 'D' : 'I', page, t);
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return word_mode ? (a & 1 ? t >> 8 : t & 255) : t;
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}
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uint16_t bus::read_par(const uint32_t a, const int run_mode, const bool word_mode, const bool peek_only)
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{
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bool is_11_34 = c->get_34();
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int page = (a >> 1) & 7;
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bool is_d = is_11_34 ? false : (a & 16);
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uint16_t t = pages[run_mode][is_d][page].par;
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DOLOG(debug, !peek_only, "read run-mode %d: %c PAR for %d: %o (phys: %07o)", run_mode, is_d ? 'D' : 'I', page, t, t * 64);
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return word_mode ? (a & 1 ? t >> 8 : t & 255) : t;
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}
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uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev, const bool peek_only)
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{
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uint16_t temp = 0;
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if (a >= 0160000) {
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bool is_11_34 = c->get_34();
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if (word_mode)
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DOLOG(debug, false, "READ I/O %06o in byte mode", a);
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@ -93,48 +115,18 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev,
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}
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/// MMU ///
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if (a >= 0172200 && a < 0172240) {
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int page = (a >> 1) & 7;
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bool is_d = is_11_34 ? false : (a & 16);
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uint16_t t = pages[001][is_d][page].pdr;
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DOLOG(debug, !peek_only, "read supervisor %c PDR for %d: %o", is_d ? 'D' : 'I', page, t);
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return word_mode ? (a & 1 ? t >> 8 : t & 255) : t;
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}
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else if (a >= 0172240 && a < 0172300) {
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int page = (a >> 1) & 7;
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bool is_d = is_11_34 ? false : (a & 16);
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uint16_t t = pages[001][is_d][page].par;
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DOLOG(debug, !peek_only, "read supervisor %c PAR for %d: %o (phys: %07o)", is_d ? 'D' : 'I', page, t, t * 64);
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return word_mode ? (a & 1 ? t >> 8 : t & 255) : t;
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}
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else if (a >= 0172300 && a < 0172340) {
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int page = (a >> 1) & 7;
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bool is_d = is_11_34 ? false : (a & 16);
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uint16_t t = pages[000][is_d][page].pdr;
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DOLOG(debug, !peek_only, "read kernel %c PDR for %d: %o", is_d ? 'D' : 'I', page, t);
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return word_mode ? (a & 1 ? t >> 8 : t & 255) : t;
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}
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else if (a >= 0172340 && a < 0172400) {
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int page = (a >> 1) & 7;
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bool is_d = is_11_34 ? false : (a & 16);
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uint16_t t = pages[000][is_d][page].par;
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DOLOG(debug, !peek_only, "read kernel %c PAR for %d: %o (phys: %07o)", is_d ? 'D' : 'I', page, t, t * 64);
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return word_mode ? (a & 1 ? t >> 8 : t & 255) : t;
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}
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else if (a >= 0177600 && a < 0177640) {
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int page = (a >> 1) & 7;
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bool is_d = is_11_34 ? false : (a & 16);
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uint16_t t = pages[003][is_d][page].pdr;
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DOLOG(debug, !peek_only, "read userspace %c PDR for %d: %o", is_d ? 'D' : 'I', page, t);
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return word_mode ? (a & 1 ? t >> 8 : t & 255) : t;
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}
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else if (a >= 0177640 && a < 0177700) {
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int page = (a >> 1) & 7;
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bool is_d = is_11_34 ? false : (a & 16);
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uint16_t t = pages[003][is_d][page].par;
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DOLOG(debug, !peek_only, "read userspace %c PAR for %d: %o (phys: %07o)", is_d ? 'D' : 'I', page, t, t * 64);
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return word_mode ? (a & 1 ? t >> 8 : t & 255) : t;
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}
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if (a >= 0172200 && a < 0172240)
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return read_pdr(a, 1, word_mode, peek_only);
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else if (a >= 0172240 && a < 0172300)
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return read_par(a, 1, word_mode, peek_only);
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else if (a >= 0172300 && a < 0172340)
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return read_pdr(a, 0, word_mode, peek_only);
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else if (a >= 0172340 && a < 0172400)
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return read_par(a, 0, word_mode, peek_only);
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else if (a >= 0177600 && a < 0177640)
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return read_pdr(a, 3, word_mode, peek_only);
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else if (a >= 0177640 && a < 0177700)
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return read_par(a, 3, word_mode, peek_only);
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///////////
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if (word_mode) {
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@ -493,6 +485,48 @@ void bus::addToMMR1(const int8_t delta, const uint8_t reg)
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MMR1 |= reg;
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}
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void bus::write_pdr(const uint32_t a, const int run_mode, const uint16_t value, const bool word_mode)
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{
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bool is_11_34 = c->get_34();
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bool is_d = is_11_34 ? false : (a & 16);
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int page = (a >> 1) & 7;
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if (word_mode) {
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a & 1 ? (pages[run_mode][is_d][page].pdr &= 0xff, pages[run_mode][is_d][page].pdr |= value << 8) :
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(pages[run_mode][is_d][page].pdr &= 0xff00, pages[run_mode][is_d][page].pdr |= value);
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}
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else {
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pages[run_mode][is_d][page].pdr = value;
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}
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if (is_11_34) // 11/34 has no cache bit
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pages[run_mode][is_d][page].pdr &= 077416;
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else
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pages[run_mode][is_d][page].pdr &= ~(128 + 64 + 32 + 16); // set bit 4 & 5 to 0 as they are unused and A/W are set to 0 by writes
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DOLOG(debug, true, "write run-mode %d: %c PDR for %d: %o [%d]", run_mode, is_d ? 'D' : 'I', page, value, word_mode);
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}
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void bus::write_par(const uint32_t a, const int run_mode, const uint16_t value, const bool word_mode)
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{
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bool is_11_34 = c->get_34();
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bool is_d = is_11_34 ? false : (a & 16);
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int page = (a >> 1) & 7;
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if (word_mode) {
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a & 1 ? (pages[run_mode][is_d][page].par &= 0xff, pages[run_mode][is_d][page].par |= value << 8) :
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(pages[run_mode][is_d][page].par &= 0xff00, pages[run_mode][is_d][page].par |= value);
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}
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else {
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pages[run_mode][is_d][page].par = value;
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}
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if (is_11_34) // 11/34 has 12 bit PARs
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pages[run_mode][is_d][page].par &= 4095;
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DOLOG(debug, true, "write run-mode %d: %c PAR for %d: %o (%07o)", run_mode, is_d ? 'D' : 'I', page, word_mode ? value & 0xff : value, pages[run_mode][is_d][page].par * 64);
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}
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void bus::write(const uint16_t a, const bool word_mode, uint16_t value, const bool use_prev)
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{
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int run_mode = (c->getPSW() >> (use_prev ? 12 : 14)) & 3;
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@ -505,8 +539,6 @@ void bus::write(const uint16_t a, const bool word_mode, uint16_t value, const bo
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}
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if (a >= 0160000) {
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bool is_11_34 = c->get_34();
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if (word_mode) {
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assert(value < 256);
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DOLOG(debug, true, "WRITE I/O %06o in byte mode", a);
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@ -646,127 +678,31 @@ void bus::write(const uint16_t a, const bool word_mode, uint16_t value, const bo
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/// MMU ///
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// supervisor
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if (a >= 0172200 && a < 0172240) {
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bool is_d = is_11_34 ? false : (a & 16);
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int page = (a >> 1) & 7;
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if (word_mode) {
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a & 1 ? (pages[001][is_d][page].pdr &= 0xff, pages[001][is_d][page].pdr |= value << 8) :
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(pages[001][is_d][page].pdr &= 0xff00, pages[001][is_d][page].pdr |= value);
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}
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else {
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pages[001][is_d][page].pdr = value;
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}
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if (is_11_34) // 11/34 has no cache bit
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pages[001][is_d][page].pdr &= 077416;
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else
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pages[001][is_d][page].pdr &= ~(128 + 64 + 32 + 16); // set bit 4 & 5 to 0 as they are unused and A/W are set to 0 by writes
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DOLOG(debug, true, "write supervisor %c PDR for %d: %o [%d]", is_d ? 'D' : 'I', page, value, word_mode);
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write_pdr(a, 1, value, word_mode);
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return;
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}
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if (a >= 0172240 && a < 0172300) {
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bool is_d = is_11_34 ? false : (a & 16);
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int page = (a >> 1) & 7;
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if (word_mode) {
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a & 1 ? (pages[001][is_d][page].par &= 0xff, pages[001][is_d][page].par |= value << 8) :
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(pages[001][is_d][page].par &= 0xff00, pages[001][is_d][page].par |= value);
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}
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else {
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pages[001][is_d][page].par = value;
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}
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if (is_11_34) // 11/34 has 12 bit PARs
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pages[001][is_d][page].par &= 4095;
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DOLOG(debug, true, "write supervisor %c PAR for %d: %o (%07o)", is_d ? 'D' : 'I', page, word_mode ? value & 0xff : value, pages[001][is_d][page].par * 64);
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write_par(a, 1, value, word_mode);
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return;
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}
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// kernel
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if (a >= 0172300 && a < 0172340) {
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bool is_d = is_11_34 ? false : (a & 16);
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int page = (a >> 1) & 7;
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if (word_mode) {
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a & 1 ? (pages[000][is_d][page].pdr &= 0xff, pages[000][is_d][page].pdr |= value << 8) :
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(pages[000][is_d][page].pdr &= 0xff00, pages[000][is_d][page].pdr |= value);
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}
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else {
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pages[000][is_d][page].pdr = value;
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}
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if (is_11_34) // 11/34 has no cache bit
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pages[000][is_d][page].pdr &= 077416;
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else
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pages[000][is_d][page].pdr &= ~(128 + 64 + 32 + 16); // set bit 4 & 5 to 0 as they are unused and A/W are set to 0 by writes
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DOLOG(debug, true, "write kernel %c PDR for %d: %o [%d]", is_d ? 'D' : 'I', page, value, word_mode);
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write_pdr(a, 0, value, word_mode);
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return;
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}
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if (a >= 0172340 && a < 0172400) {
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bool is_d = is_11_34 ? false : (a & 16);
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int page = (a >> 1) & 7;
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if (word_mode) {
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a & 1 ? (pages[000][is_d][page].par &= 0xff, pages[000][is_d][page].par |= value << 8) :
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(pages[000][is_d][page].par &= 0xff00, pages[000][is_d][page].par |= value);
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}
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else {
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pages[000][is_d][page].par = value;
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}
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if (is_11_34) // 11/34 has 12 bit PARs
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pages[000][is_d][page].par &= 4095;
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DOLOG(debug, true, "write kernel %c PAR for %d: %o (%07o)", is_d ? 'D' : 'I', page, word_mode ? value & 0xff : value, pages[000][is_d][page].par * 64);
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write_par(a, 0, value, word_mode);
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return;
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}
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// user
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if (a >= 0177600 && a < 0177640) {
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bool is_d = is_11_34 ? false : (a & 16);
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int page = (a >> 1) & 7;
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if (word_mode) {
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a & 1 ? (pages[003][is_d][page].pdr &= 0xff, pages[003][is_d][page].pdr |= value << 8) :
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(pages[003][is_d][page].pdr &= 0xff00, pages[003][is_d][page].pdr |= value);
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}
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else {
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pages[003][is_d][page].pdr = value;
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}
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if (is_11_34) // 11/34 has no cache bit
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pages[003][is_d][page].pdr &= 077416;
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else
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pages[003][is_d][page].pdr &= ~(128 + 64 + 32 + 16); // set bit 4 & 5 to 0 as they are unused and A/W are set to 0 by writes
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DOLOG(debug, true, "write user %c PDR for %d: %o [%d]", is_d ? 'D' : 'I', page, value, word_mode);
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write_pdr(a, 3, value, word_mode);
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return;
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}
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if (a >= 0177640 && a < 0177700) {
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bool is_d = is_11_34 ? false : (a & 16);
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int page = (a >> 1) & 7;
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if (word_mode) {
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a & 1 ? (pages[003][is_d][page].par &= 0xff, pages[003][is_d][page].par |= value << 8) :
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(pages[003][is_d][page].par &= 0xff00, pages[003][is_d][page].par |= value);
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}
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else {
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pages[003][is_d][page].par = value;
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}
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if (is_11_34) // 11/34 has 12 bit PARs
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pages[003][is_d][page].par &= 4095;
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DOLOG(debug, true, "write user %c PAR for %d: %o (%07o)", is_d ? 'D' : 'I', page, word_mode ? value & 0xff : value, pages[003][is_d][page].par * 64);
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write_par(a, 3, value, word_mode);
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return;
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}
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////
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5
bus.h
5
bus.h
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@ -41,6 +41,11 @@ private:
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uint16_t console_switches { 0 };
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uint16_t read_pdr (const uint32_t a, const int run_mode, const bool word_mode, const bool peek_only);
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uint16_t read_par (const uint32_t a, const int run_mode, const bool word_mode, const bool peek_only);
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void write_pdr(const uint32_t a, const int run_mode, const uint16_t value, const bool word_mode);
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void write_par(const uint32_t a, const int run_mode, const uint16_t value, const bool word_mode);
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public:
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bus();
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~bus();
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