several swapped MMR1 instances
This commit is contained in:
parent
ce8af01f63
commit
85e8f873e9
2 changed files with 28 additions and 11 deletions
20
cpu.cpp
20
cpu.cpp
|
@ -511,10 +511,10 @@ bool cpu::double_operand_instructions(const uint16_t instr)
|
|||
}
|
||||
|
||||
case 0b010: { // CMP/CMPB Compare Word/Byte
|
||||
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode, rm_cur);
|
||||
|
||||
auto g_dst = getGAM(dst_mode, dst_reg, word_mode, rm_cur);
|
||||
|
||||
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode, rm_cur);
|
||||
|
||||
uint16_t temp = (g_src.value.value() - g_dst.value.value()) & (word_mode == wm_byte ? 0xff : 0xffff);
|
||||
|
||||
setPSW_n(SIGN(temp, word_mode));
|
||||
|
@ -526,9 +526,9 @@ bool cpu::double_operand_instructions(const uint16_t instr)
|
|||
}
|
||||
|
||||
case 0b011: { // BIT/BITB Bit Test Word/Byte
|
||||
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode, rm_cur);
|
||||
auto g_dst = getGAM(dst_mode, dst_reg, word_mode, rm_cur);
|
||||
|
||||
auto g_dst = getGAM(dst_mode, dst_reg, word_mode, rm_cur);
|
||||
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode, rm_cur);
|
||||
|
||||
uint16_t result = (g_dst.value.value() & g_src.value.value()) & (word_mode == wm_byte ? 0xff : 0xffff);
|
||||
|
||||
|
@ -538,10 +538,10 @@ bool cpu::double_operand_instructions(const uint16_t instr)
|
|||
}
|
||||
|
||||
case 0b100: { // BIC/BICB Bit Clear Word/Byte
|
||||
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode, rm_cur);
|
||||
|
||||
auto g_dst = getGAM(dst_mode, dst_reg, word_mode, rm_cur);
|
||||
|
||||
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode, rm_cur);
|
||||
|
||||
uint16_t result = g_dst.value.value() & ~g_src.value.value();
|
||||
|
||||
if (put_result(g_dst, result))
|
||||
|
@ -552,10 +552,10 @@ bool cpu::double_operand_instructions(const uint16_t instr)
|
|||
|
||||
case 0b101: { // BIS/BISB Bit Set Word/Byte
|
||||
// TODO: retain MSB for register operations?
|
||||
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode, rm_cur);
|
||||
|
||||
auto g_dst = getGAM(dst_mode, dst_reg, word_mode, rm_cur);
|
||||
|
||||
gam_rc_t g_src = getGAM(src_mode, src_reg, word_mode, rm_cur);
|
||||
|
||||
uint16_t result = g_dst.value.value() | g_src.value.value();
|
||||
|
||||
if (put_result(g_dst, result)) {
|
||||
|
@ -568,10 +568,10 @@ bool cpu::double_operand_instructions(const uint16_t instr)
|
|||
}
|
||||
|
||||
case 0b110: { // ADD/SUB Add/Subtract Word
|
||||
auto g_ssrc = getGAM(src_mode, src_reg, wm_word, rm_cur);
|
||||
|
||||
auto g_dst = getGAM(dst_mode, dst_reg, wm_word, rm_cur);
|
||||
|
||||
auto g_ssrc = getGAM(src_mode, src_reg, wm_word, rm_cur);
|
||||
|
||||
int16_t result = 0;
|
||||
|
||||
bool set_flags = true;
|
||||
|
|
19
main.cpp
19
main.cpp
|
@ -206,7 +206,24 @@ int run_cpu_validation(const std::string & filename)
|
|||
uint16_t should_be_mmr = json_integer_value(a_mmr);
|
||||
uint16_t is_mmr = b->getMMR(r);
|
||||
if (should_be_mmr != is_mmr) {
|
||||
DOLOG(warning, true, "MMR%d register mismatch (is: %06o (%d), should be: %06o (%d))", r, is_mmr, is_mmr, should_be_mmr, should_be_mmr);
|
||||
int is_d1 = is_mmr >> 11;
|
||||
if (is_d1 & 16)
|
||||
is_d1 = -(32 - is_d1);
|
||||
int is_r1 = (is_mmr >> 8) & 7;
|
||||
int is_d2 = (is_mmr >> 3) & 31;
|
||||
if (is_d2 & 16)
|
||||
is_d2 = -(32 - is_d2);
|
||||
int is_r2 = is_mmr & 7;
|
||||
|
||||
int sb_d1 = should_be_mmr >> 11;
|
||||
if (sb_d1 & 16)
|
||||
sb_d1 = -(32 - sb_d1);
|
||||
int sb_r1 = (should_be_mmr >> 8) & 7;
|
||||
int sb_d2 = (should_be_mmr >> 3) & 31;
|
||||
if (sb_d2 & 16)
|
||||
sb_d2 = -(32 - sb_d2);
|
||||
int sb_r2 = should_be_mmr & 7;
|
||||
DOLOG(warning, true, "MMR%d register mismatch (is: %06o (%d / %02d,%02d - %02d,%02d), should be: %06o (%d / %02d,%02d - %02d,%02d))%s", r, is_mmr, is_mmr, is_d1, is_r1, is_d2, is_r2, should_be_mmr, should_be_mmr, sb_d1, sb_r1, sb_d2, sb_r2, c->is_it_a_trap() ? " TRAP": "");
|
||||
err = true;
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Add table
Reference in a new issue