fixes
This commit is contained in:
folkert van heusden
parent
c62aadd318
commit
a0630fd485
GPG key ID:
6B6455EDFEED3BD1
5 changed files with 190 additions and 84 deletions
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@ -6,6 +6,9 @@ cmake_minimum_required(VERSION 3.9)
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add_compile_options(-Wall -pedantic -Wextra)
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add_compile_options(-fsanitize=address)
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add_link_options(-fsanitize=address)
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set(CMAKE_CXX_STANDARD 17)
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set(CMAKE_CXX_STANDARD_REQUIRED True)
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@ -69,9 +72,9 @@ endif (WIN32)
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include(CheckIPOSupported)
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check_ipo_supported(RESULT supported)
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set(CMAKE_BUILD_TYPE RelWithDebInfo)
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set(CMAKE_INTERPROCEDURAL_OPTIMIZATION_RELEASE TRUE)
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#set(CMAKE_BUILD_TYPE Debug)
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#set(CMAKE_BUILD_TYPE RelWithDebInfo)
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#set(CMAKE_INTERPROCEDURAL_OPTIMIZATION_RELEASE TRUE)
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set(CMAKE_BUILD_TYPE Debug)
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set(CMAKE_THREAD_PREFER_PTHREAD TRUE)
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set(THREADS_PREFER_PTHREAD_FLAG TRUE)
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23
cpu.cpp
23
cpu.cpp
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@ -1,4 +1,4 @@
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// (C) 2018-2023 by Folkert van Heusden
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// (C) 2018-2024 by Folkert van Heusden
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// Released under MIT license
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#include <assert.h>
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@ -179,6 +179,27 @@ uint16_t cpu::addRegister(const int nr, const rm_selection_t mode_selection, con
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return pc += value;
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}
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void cpu::lowlevel_register_set(const uint8_t set, const uint8_t reg, const uint16_t value)
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{
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if (reg < 6)
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regs0_5[set][reg] = value;
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else if (reg == 6)
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sp[set == 0 ? 0 : 3] = value;
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else
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pc = value;
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}
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uint16_t cpu::lowlevel_register_get(const uint8_t set, const uint8_t reg)
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{
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if (reg < 6)
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return regs0_5[set][reg];
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if (reg == 6)
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return sp[set == 0 ? 0 : 3];
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return pc;
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}
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bool cpu::getBitPSW(const int bit) const
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{
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return (psw >> bit) & 1;
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8
cpu.h
8
cpu.h
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@ -1,4 +1,4 @@
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// (C) 2018-2023 by Folkert van Heusden
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// (C) 2018-2024 by Folkert van Heusden
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// Released under MIT license
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#pragma once
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@ -64,7 +64,6 @@ private:
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void addToMMR1(const uint8_t mode, const uint8_t reg, const word_mode_t word_mode);
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gam_rc_t getGAM(const uint8_t mode, const uint8_t reg, const word_mode_t word_mode, const rm_selection_t mode_selection, const bool read_value = true);
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gam_rc_t getGAMAddress(const uint8_t mode, const int reg, const word_mode_t word_mode);
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bool putGAM(const gam_rc_t & g, const uint16_t value); // returns false when flag registers should not be updated
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@ -143,8 +142,11 @@ public:
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uint16_t getPC() const { return pc; }
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void setRegister(const int nr, const uint16_t value, const rm_selection_t mode_selection = rm_cur);
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void setRegisterLowByte(const int nr, const word_mode_t word_mode, const uint16_t value);
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// used by 'main' for json-validation
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void lowlevel_register_set(const uint8_t set, const uint8_t reg, const uint16_t value);
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uint16_t lowlevel_register_get(const uint8_t set, const uint8_t reg);
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void lowlevel_psw_set(const uint16_t value) { psw = value; }
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void setStackPointer(const int which, const uint16_t value) { assert(which >= 0 && which < 4); sp[which] = value; }
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void setPC(const uint16_t value) { pc = value; }
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@ -2,6 +2,7 @@
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import json
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from machine import PDP1170
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from pdptraps import PDPTrap, PDPTraps
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import random
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import sys
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@ -14,23 +15,32 @@ class PDP1170_wrapper(PDP1170):
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def reset_mem_transactions_dict(self):
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self.mem_transactions = dict()
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self.before = dict()
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def get_mem_before(self):
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return self.before
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def get_mem_transactions_dict(self):
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return self.mem_transactions
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def put(self, physaddr, value):
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self.before[physaddr] = value
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super().physRW(physaddr, value)
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def physRW(self, physaddr, value=None):
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if value == None: # read
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self.mem_transactions[physaddr] = random.randint(0, 65536)
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return super().physRW(physaddr, self.mem_transactions[physaddr])
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if not physaddr in self.mem_transactions and not physaddr in self.before:
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self.before[physaddr] = random.randint(0, 65536)
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return super().physRW(physaddr, self.before[physaddr])
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self.mem_transactions[physaddr] = value
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super().physRW(physaddr, value)
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return super().physRW(physaddr, value)
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def physRW_N(self, physaddr, nwords, words=None):
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temp_addr = physaddr
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if words == None:
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for i in range(nwords):
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physRW(temp_addr, random.randint(0, 65536))
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self.physRW(temp_addr, random.randint(0, 65536))
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temp_addr += 2
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return super().physRW_N(physaddr, nwords)
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@ -38,32 +48,28 @@ class PDP1170_wrapper(PDP1170):
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self.mem_transactions[temp_addr] = w
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temp_addr += 2
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super().physRW_N(physaddr, nwords, words=words)
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return super().physRW_N(physaddr, nwords, words=words)
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class test_generator:
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def _invoke_bp(self, a, i):
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return True
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def _run_test(self, addr, mem_setup, reg_setup, psw):
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p = PDP1170_wrapper(loglevel='DEBUG')
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def put_registers(self, p, target, tag):
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target[tag] = dict()
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target[tag][0] = dict()
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target[tag][1] = dict()
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for set_ in range(0, 2):
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for reg_ in range(0, 6):
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target[tag][set_][reg_] = p.registerfiles[set_][reg_]
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for a, v in mem_setup:
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p.mmu.wordRW(a, v)
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for r, v in reg_setup:
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p.r[r] = v
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p.reset_mem_transactions_dict()
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p._syncregs()
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p.run_steps(pc=addr, steps=1)
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p._syncregs()
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return p
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target[tag]['sp'] = p.stackpointers
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target[tag]['pc'] = p.PC
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def create_test(self):
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out = { }
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p = PDP1170_wrapper(loglevel='DEBUG')
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addr = random.randint(0, 65536) & ~3
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# TODO what is the maximum size of an instruction?
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@ -72,41 +78,59 @@ class test_generator:
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mem_kv.append((addr + 2, random.randint(0, 65536)))
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mem_kv.append((addr + 4, random.randint(0, 65536)))
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mem_kv.append((addr + 6, random.randint(0, 65536)))
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out['memory-before'] = dict()
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for a, v in mem_kv:
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out['memory-before'][a] = v
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reg_kv = []
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for i in range(7):
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reg_kv.append((i, random.randint(0, 65536)))
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reg_kv.append((7, addr))
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out['registers-before'] = dict()
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for r, v in reg_kv:
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out['registers-before'][r] = v
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out['registers-before']['psw'] = 0 # TODO random.randint(0, 65536)
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p.put(a, v)
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try:
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p = self._run_test(addr, mem_kv, reg_kv, out['registers-before']['psw'])
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# generate & set PSW
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while True:
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try:
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p.psw = random.randint(0, 65536)
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break
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except PDPTraps.ReservedInstruction as ri:
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pass
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out['registers-after'] = dict()
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# generate other registers
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reg_kv = []
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for i in range(7):
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reg_kv.append((i, random.randint(0, 65536)))
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reg_kv.append((7, addr))
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# set registers
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set_ = (p.psw >> 11) & 1
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for r, v in reg_kv:
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out['registers-after'][r] = v
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p.registerfiles[set_][r] = v
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p.registerfiles[1 - set_][r] = (~v) & 65535 # make sure it triggers errors
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assert p.registerfiles[set_][r] == p.r[r]
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p.r[6] = p.registerfiles[set_][6]
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p._syncregs()
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self.put_registers(p, out, 'registers-before')
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out['registers-before']['psw'] = p.psw
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p.run_steps(pc=addr, steps=1)
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self.put_registers(p, out, 'registers-after')
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out['registers-after']['psw'] = p.psw
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mb = p.get_mem_before()
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for a in mb:
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out['memory-before'][a] = mb[a]
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out['memory-after'] = dict()
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for a, v in mem_kv:
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out['memory-after'][a] = v
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mem_transactions = p.get_mem_transactions_dict()
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for a in mem_transactions:
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out['memory-after'][a] = mem_transactions[a]
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# TODO originele geheugeninhouden checken
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# TODO check if mem_transactions affects I/O, then return None
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return out
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except PDPTraps.ReservedInstruction as pri:
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return None
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except Exception as e:
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# handle PDP11 traps; store them
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print('test failed', e)
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@ -122,5 +146,5 @@ for i in range(0, 4096):
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if test != None:
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tests.append(test)
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fh.write(json.dumps(tests))
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fh.write(json.dumps(tests, indent=4))
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fh.close()
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132
main.cpp
132
main.cpp
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@ -1,6 +1,7 @@
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// (C) 2018-2024 by Folkert van Heusden
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// Released under MIT license
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#include <assert.h>
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#include <atomic>
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#include <jansson.h>
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#include <signal.h>
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@ -70,20 +71,40 @@ int run_cpu_validation(const std::string & filename)
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// {"memory-before": {"512": 51435, "514": 45610, "516": 15091, "518": 43544}, "registers-before": {"0": 64423, "1": 1, "2": 41733, "3": 14269, "4": 48972, "5": 42770, "6": 57736, "7": 512}, "registers-after": {"0": 64423, "1": 1, "2": 41733, "3": 14269, "4": 48972, "5": 42770, "6": 57736, "7": 512}, "memory-after": {"512": 51435, "514": 45610, "516": 15091, "518": 43544}}
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// initialize
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json_t *memory_before = json_object_get(test, "memory-before");
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const char *key = nullptr;
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json_t *value = nullptr;
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json_object_foreach(memory_before, key, value) {
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b->writePhysical(atoi(key), json_integer_value(value));
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{
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// initialize
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json_t *memory_before = json_object_get(test, "memory-before");
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const char *key = nullptr;
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json_t *value = nullptr;
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json_object_foreach(memory_before, key, value) {
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b->writePhysical(atoi(key), json_integer_value(value));
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}
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}
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json_t *registers_before = json_object_get(test, "registers-before");
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json_object_foreach(registers_before, key, value) {
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if (strcmp(key, "psw") == 0)
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c->setPSW(uint16_t(json_integer_value(value)), false); // TODO: without the AND
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else
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c->setRegister(atoi(key), json_integer_value(value), rm_cur);
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json_t *const registers_before = json_object_get(test, "registers-before");
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{
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const char *key = nullptr;
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json_t *value = nullptr;
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json_t *set0 = json_object_get(registers_before, "0");
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json_object_foreach(set0, key, value) {
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c->lowlevel_register_set(0, atoi(key), json_integer_value(value));
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}
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json_t *set1 = json_object_get(registers_before, "1");
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json_object_foreach(set1, key, value) {
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c->lowlevel_register_set(1, atoi(key), json_integer_value(value));
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}
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}
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{
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json_t *psw_reg = json_object_get(registers_before, "psw");
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assert(psw_reg);
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c->lowlevel_psw_set(json_integer_value(psw_reg));
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}
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{
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json_t *b_pc = json_object_get(registers_before, "pc");
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assert(b_pc);
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c->setPC(json_integer_value(b_pc));
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// TODO PS
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}
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c->step_a();
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@ -91,39 +112,74 @@ int run_cpu_validation(const std::string & filename)
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c->step_b();
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// validate
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bool err = false;
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json_t *memory_after = json_object_get(test, "memory-after");
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json_object_foreach(memory_before, key, value) {
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uint16_t mem_contains = b->readPhysical(atoi(key));
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uint16_t should_be = json_integer_value(value);
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{
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bool err = false;
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{
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json_t *memory_after = json_object_get(test, "memory-after");
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const char *key = nullptr;
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json_t *value = nullptr;
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json_object_foreach(memory_after, key, value) {
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int key_v = atoi(key);
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uint16_t mem_contains = b->readPhysical(key_v);
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uint16_t should_be = json_integer_value(value);
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if (mem_contains != should_be) {
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DOLOG(warning, true, "memory address %s mismatch (is: %06o, should be: %06o)", key, mem_contains, should_be);
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err = true;
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if (mem_contains != should_be) {
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DOLOG(warning, true, "memory address %06o (%d) mismatch (is: %06o (%d), should be: %06o (%d))", key_v, key_v, mem_contains, mem_contains, should_be, should_be);
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err = true;
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}
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}
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}
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}
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json_t *registers_after = json_object_get(test, "registers-after");
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json_object_foreach(registers_before, key, value) {
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uint16_t register_is = 0;
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uint16_t psw = c->getPSW();
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if (strcmp(key, "psw") == 0)
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register_is = c->getPSW();
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json_t *const registers_after = json_object_get(test, "registers-after");
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{
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int set_nr = (psw >> 11) & 1;
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char set[] = { char('0' + set_nr), 0x00 };
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json_t *a_set = json_object_get(registers_after, set);
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const char *key = nullptr;
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json_t *value = nullptr;
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json_object_foreach(a_set, key, value) {
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uint16_t register_is = c->lowlevel_register_get(set_nr, atoi(key));
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uint16_t should_be = json_integer_value(value);
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if (register_is != should_be) {
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DOLOG(warning, true, "set %d register %s mismatch (is: %06o, should be: %06o)", set_nr, key, register_is, should_be);
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err = true;
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}
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}
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}
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{
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json_t *a_pc = json_object_get(registers_after, "pc");
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assert(a_pc);
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uint16_t should_be_pc = json_integer_value(a_pc);
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if (c->getPC() != should_be_pc) {
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DOLOG(warning, true, "PC register mismatch (is: %06o, should be: %06o)", c->getPC(), should_be_pc);
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err = true;
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}
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}
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// TODO check PS
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{
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json_t *a_psw = json_object_get(registers_after, "psw");
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assert(a_psw);
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uint16_t should_be_psw = json_integer_value(a_psw);
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if (should_be_psw != psw) {
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DOLOG(warning, true, "PSW register mismatch (is: %06o, should be: %06o)", psw, should_be_psw);
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err = true;
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}
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}
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if (err)
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DOLOG(warning, true, "%s\n", json_dumps(test, 0)); // also emit empty line(!)
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else
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register_is = c->getRegister(atoi(key), rm_cur);
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uint16_t should_be = json_integer_value(value);
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if (register_is != should_be) {
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DOLOG(warning, true, "register %s mismatch (is: %06o, should be: %06o)", key, register_is, should_be);
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err = true;
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}
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n_ok++;
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}
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if (err)
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DOLOG(warning, true, "%s", json_dumps(test, 0));
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else
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n_ok++;
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// clean-up
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delete b;
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}
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