Merge branch 'master' of ssh://172.29.0.8/home/folkert/git/PDP-11
This commit is contained in:
folkert van heusden
commit
a13acb4ba0
GPG key ID:
6B6455EDFEED3BD1
8 changed files with 309 additions and 308 deletions
286
bus.cpp
286
bus.cpp
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@ -24,7 +24,6 @@
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bus::bus()
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{
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mmu_ = new mmu();
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mmu_->begin();
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kw11_l_ = new kw11_l(this);
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@ -80,9 +79,10 @@ bus *bus::deserialize(const json_t *const j, console *const cnsl, std::atomic_ui
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json_t *temp = nullptr;
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memory *m = nullptr;
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temp = json_object_get(j, "memory");
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if (temp) {
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memory *m = memory::deserialize(temp);
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m = memory::deserialize(temp);
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b->add_ram(m);
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}
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@ -100,7 +100,7 @@ bus *bus::deserialize(const json_t *const j, console *const cnsl, std::atomic_ui
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temp = json_object_get(j, "mmu");
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if (temp) {
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mmu *mmu_ = mmu::deserialize(temp);
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mmu *mmu_ = mmu::deserialize(temp, m);
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b->add_mmu(mmu_);
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}
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@ -135,6 +135,8 @@ void bus::set_memory_size(const int n_pages)
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delete m;
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m = new memory(n_bytes);
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mmu_->begin(m);
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DOLOG(info, false, "Memory is now %u kB in size", n_bytes / 1024);
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}
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@ -168,6 +170,8 @@ void bus::add_ram(memory *const m)
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{
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delete this->m;
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this->m = m;
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mmu_->begin(m);
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}
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void bus::add_mmu(mmu *const mmu_)
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@ -212,25 +216,13 @@ void bus::init()
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mmu_->setMMR3(0);
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}
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void bus::trap_odd(const uint16_t a)
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{
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uint16_t temp = mmu_->getMMR0();
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temp &= ~(7 << 1);
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temp |= (a >> 13) << 1;
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mmu_->setMMR0(temp);
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c->trap(004); // invalid access
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}
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uint16_t bus::read(const uint16_t addr_in, const word_mode_t word_mode, const rm_selection_t mode_selection, const bool peek_only, const d_i_space_t space)
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{
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int run_mode = mode_selection == rm_cur ? c->getPSW_runmode() : c->getPSW_prev_runmode();
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uint32_t m_offset = calculate_physical_address(run_mode, addr_in, !peek_only, false, peek_only, space);
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uint32_t m_offset = mmu_->calculate_physical_address(c, run_mode, addr_in, !peek_only, false, peek_only, space);
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uint32_t io_base = get_io_base();
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uint32_t io_base = mmu_->get_io_base();
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bool is_io = m_offset >= io_base;
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if (is_io) {
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@ -270,9 +262,9 @@ uint16_t bus::read(const uint16_t addr_in, const word_mode_t word_mode, const rm
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///^ registers ^///
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if (!peek_only) {
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if ((a & 1) && word_mode == wm_word) {
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if ((a & 1) && word_mode == wm_word) [[unlikely]] {
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DOLOG(debug, false, "READ-I/O odd address %06o UNHANDLED", a);
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trap_odd(a);
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mmu_->trap_if_odd(addr_in, run_mode, space, false);
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throw 0;
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return 0;
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}
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@ -497,7 +489,7 @@ uint16_t bus::read(const uint16_t addr_in, const word_mode_t word_mode, const rm
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}
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if (!peek_only) {
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DOLOG(debug, false, "READ-I/O UNHANDLED read %08o (%c), (base: %o)", m_offset, word_mode == wm_byte ? 'B' : ' ', get_io_base());
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DOLOG(debug, false, "READ-I/O UNHANDLED read %08o (%c), (base: %o)", m_offset, word_mode == wm_byte ? 'B' : ' ', mmu_->get_io_base());
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c->trap(004); // no such i/o
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throw 1;
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@ -507,8 +499,8 @@ uint16_t bus::read(const uint16_t addr_in, const word_mode_t word_mode, const rm
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}
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if (peek_only == false && word_mode == wm_word && (addr_in & 1)) {
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if (!peek_only) DOLOG(debug, false, "READ from %06o - odd address!", addr_in);
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trap_odd(addr_in);
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DOLOG(debug, false, "READ from %06o - odd address!", addr_in);
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mmu_->trap_if_odd(addr_in, run_mode, space, false);
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throw 2;
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return 0;
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}
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@ -534,53 +526,9 @@ uint16_t bus::read(const uint16_t addr_in, const word_mode_t word_mode, const rm
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return temp;
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}
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void bus::check_odd_addressing(const uint16_t a, const int run_mode, const d_i_space_t space, const bool is_write)
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{
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if (a & 1) {
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if (is_write)
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mmu_->set_page_trapped(run_mode, space == d_space, a >> 13);
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trap_odd(a);
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throw 4;
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}
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}
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memory_addresses_t bus::calculate_physical_address(const int run_mode, const uint16_t a) const
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{
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const uint8_t apf = a >> 13; // active page field
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if (mmu_->is_enabled() == false) {
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bool is_psw = a == ADDR_PSW;
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return { a, apf, a, is_psw, a, is_psw };
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}
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uint32_t physical_instruction = mmu_->get_physical_memory_offset(run_mode, 0, apf);
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uint32_t physical_data = mmu_->get_physical_memory_offset(run_mode, 1, apf);
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uint16_t p_offset = a & 8191; // page offset
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physical_instruction += p_offset;
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physical_data += p_offset;
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if ((mmu_->getMMR3() & 16) == 0) { // offset is 18bit
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physical_instruction &= 0x3ffff;
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physical_data &= 0x3ffff;
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}
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if (mmu_->get_use_data_space(run_mode) == false)
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physical_data = physical_instruction;
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uint32_t io_base = get_io_base();
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bool physical_instruction_is_psw = (physical_instruction - io_base + 0160000) == ADDR_PSW;
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bool physical_data_is_psw = (physical_data - io_base + 0160000) == ADDR_PSW;
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return { a, apf, physical_instruction, physical_instruction_is_psw, physical_data, physical_data_is_psw };
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}
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bool bus::is_psw(const uint16_t addr, const int run_mode, const d_i_space_t space) const
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{
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auto meta = calculate_physical_address(run_mode, addr);
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auto meta = mmu_->calculate_physical_address(run_mode, addr);
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if (space == d_space && meta.physical_data_is_psw)
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return true;
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@ -591,194 +539,6 @@ bool bus::is_psw(const uint16_t addr, const int run_mode, const d_i_space_t spac
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return false;
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}
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void bus::mmudebug(const uint16_t a)
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{
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for(int rm=0; rm<4; rm++) {
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auto ma = calculate_physical_address(rm, a);
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DOLOG(debug, false, "RM %d, a: %06o, apf: %d, PI: %08o (PSW: %d), PD: %08o (PSW: %d)", rm, ma.virtual_address, ma.apf, ma.physical_instruction, ma.physical_instruction_is_psw, ma.physical_data, ma.physical_data_is_psw);
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}
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}
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std::pair<trap_action_t, int> bus::get_trap_action(const int run_mode, const bool d, const int apf, const bool is_write)
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{
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const int access_control = mmu_->get_access_control(run_mode, d, apf);
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trap_action_t trap_action = T_PROCEED;
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if (access_control == 0)
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trap_action = T_ABORT_4;
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else if (access_control == 1)
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trap_action = is_write ? T_ABORT_4 : T_TRAP_250;
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else if (access_control == 2) {
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if (is_write)
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trap_action = T_ABORT_4;
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}
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else if (access_control == 3)
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trap_action = T_ABORT_4;
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else if (access_control == 4)
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trap_action = T_TRAP_250;
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else if (access_control == 5) {
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if (is_write)
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trap_action = T_TRAP_250;
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}
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else if (access_control == 6) {
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// proceed
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}
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else if (access_control == 7) {
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trap_action = T_ABORT_4;
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}
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return { trap_action, access_control };
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}
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uint32_t bus::calculate_physical_address(const int run_mode, const uint16_t a, const bool trap_on_failure, const bool is_write, const bool peek_only, const d_i_space_t space)
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{
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uint32_t m_offset = a;
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if (mmu_->is_enabled() || (is_write && (mmu_->getMMR0() & (1 << 8 /* maintenance check */)))) {
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uint8_t apf = a >> 13; // active page field
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bool d = space == d_space && mmu_->get_use_data_space(run_mode);
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uint16_t p_offset = a & 8191; // page offset
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m_offset = mmu_->get_physical_memory_offset(run_mode, d, apf);
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m_offset += p_offset;
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if ((mmu_->getMMR3() & 16) == 0) // off is 18bit
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m_offset &= 0x3ffff;
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uint32_t io_base = get_io_base();
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bool is_io = m_offset >= io_base;
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if (trap_on_failure) [[unlikely]] {
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{
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auto rc = get_trap_action(run_mode, d, apf, is_write);
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auto trap_action = rc.first;
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int access_control = rc.second;
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if (trap_action != T_PROCEED) {
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if (is_write)
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mmu_->set_page_trapped(run_mode, d, apf);
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if (mmu_->is_locked() == false) {
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uint16_t temp = mmu_->getMMR0();
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temp &= ~((1l << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (3 << 5) | (7 << 1) | (1 << 4));
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if (is_write && access_control != 6)
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temp |= 1 << 13; // read-only
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//
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if (access_control == 0 || access_control == 4)
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temp |= 1l << 15; // not resident
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else
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temp |= 1 << 13; // read-only
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temp |= run_mode << 5; // TODO: kernel-mode or user-mode when a trap occurs in user-mode?
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temp |= apf << 1; // add current page
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temp |= d << 4;
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mmu_->setMMR0(temp);
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DOLOG(debug, false, "MMR0: %06o", temp);
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}
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if (trap_action == T_TRAP_250) {
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DOLOG(debug, false, "Page access %d (for virtual address %06o): trap 0250", access_control, a);
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c->trap(0250); // trap
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throw 5;
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}
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else { // T_ABORT_4
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DOLOG(debug, false, "Page access %d (for virtual address %06o): trap 004", access_control, a);
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c->trap(004); // abort
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throw 5;
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}
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}
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}
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if (m_offset >= m->get_memory_size() && !is_io) [[unlikely]] {
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DOLOG(debug, !peek_only, "bus::calculate_physical_address %o >= %o", m_offset, m->get_memory_size());
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DOLOG(debug, false, "TRAP(04) (throw 6) on address %06o", a);
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if (mmu_->is_locked() == false) {
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uint16_t temp = mmu_->getMMR0();
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temp &= 017777;
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temp |= 1l << 15; // non-resident
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temp &= ~14; // add current page
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temp |= apf << 1;
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temp &= ~(3 << 5);
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temp |= run_mode << 5;
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mmu_->setMMR0(temp);
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}
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if (is_write)
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mmu_->set_page_trapped(run_mode, d, apf);
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c->trap(04);
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throw 6;
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}
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uint16_t pdr_len = mmu_->get_pdr_len(run_mode, d, apf);
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uint16_t pdr_cmp = (a >> 6) & 127;
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bool direction = mmu_->get_pdr_direction(run_mode, d, apf);
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// DOLOG(debug, false, "p_offset %06o pdr_len %06o direction %d, run_mode %d, apf %d, pdr: %06o", p_offset, pdr_len, direction, run_mode, apf, pages[run_mode][d][apf].pdr);
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if ((pdr_cmp > pdr_len && direction == false) || (pdr_cmp < pdr_len && direction == true)) {
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DOLOG(debug, false, "bus::calculate_physical_address::p_offset %o versus %o direction %d", pdr_cmp, pdr_len, direction);
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DOLOG(debug, false, "TRAP(0250) (throw 7) on address %06o", a);
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c->trap(0250); // invalid access
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if (mmu_->is_locked() == false) {
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uint16_t temp = mmu_->getMMR0();
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temp &= 017777;
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temp |= 1 << 14; // length
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temp &= ~14; // add current page
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temp |= apf << 1;
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temp &= ~(3 << 5);
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temp |= run_mode << 5;
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temp &= ~(1 << 4);
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temp |= d << 4;
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mmu_->setMMR0(temp);
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}
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if (is_write)
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mmu_->set_page_trapped(run_mode, d, apf);
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throw 7;
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}
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}
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DOLOG(debug, false, "virtual address %06o maps to physical address %08o (run_mode: %d, apf: %d, par: %08o, poff: %o, AC: %d, %s)", a, m_offset, run_mode, apf,
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mmu_->get_physical_memory_offset(run_mode, d, apf),
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p_offset, mmu_->get_access_control(run_mode, d, apf), d ? "D" : "I");
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}
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else {
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// DOLOG(debug, false, "no MMU (read physical address %08o)", m_offset);
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}
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return m_offset;
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}
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write_rc_t bus::write(const uint16_t addr_in, const word_mode_t word_mode, uint16_t value, const rm_selection_t mode_selection, const d_i_space_t space)
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{
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int run_mode = mode_selection == rm_cur ? c->getPSW_runmode() : c->getPSW_prev_runmode();
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@ -791,9 +551,9 @@ write_rc_t bus::write(const uint16_t addr_in, const word_mode_t word_mode, uint1
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if (mmu_->is_enabled() && (addr_in & 1) == 0 /* TODO remove this? */ && addr_in != ADDR_MMR0)
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mmu_->set_page_written_to(run_mode, d, apf);
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uint32_t m_offset = calculate_physical_address(run_mode, addr_in, true, true, false, space);
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uint32_t m_offset = mmu_->calculate_physical_address(c, run_mode, addr_in, true, true, false, space);
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uint32_t io_base = get_io_base();
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uint32_t io_base = mmu_->get_io_base();
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bool is_io = m_offset >= io_base;
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if (is_io) {
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@ -1009,12 +769,13 @@ write_rc_t bus::write(const uint16_t addr_in, const word_mode_t word_mode, uint1
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///////////
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DOLOG(debug, false, "WRITE-I/O UNHANDLED %08o(%c): %06o (base: %o)", m_offset, word_mode == wm_byte ? 'B' : 'W', value, get_io_base());
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DOLOG(debug, false, "WRITE-I/O UNHANDLED %08o(%c): %06o (base: %o)", m_offset, word_mode == wm_byte ? 'B' : 'W', value, mmu_->get_io_base());
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if (word_mode == wm_word && (a & 1)) {
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if (word_mode == wm_word && (a & 1)) [[unlikely]] {
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DOLOG(debug, false, "WRITE-I/O to %08o (value: %06o) - odd address!", m_offset, value);
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trap_odd(a);
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mmu_->trap_if_odd(a, run_mode, space, true);
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throw 8;
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}
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|
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@ -1023,10 +784,11 @@ write_rc_t bus::write(const uint16_t addr_in, const word_mode_t word_mode, uint1
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throw 9;
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}
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if (word_mode == wm_word && (addr_in & 1)) {
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if (word_mode == wm_word && (addr_in & 1)) [[unlikely]] {
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DOLOG(debug, false, "WRITE to %06o (value: %06o) - odd address!", addr_in, value);
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trap_odd(addr_in);
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mmu_->trap_if_odd(addr_in, run_mode, space, true);
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throw 10;
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}
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||||
|
|
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|||
37
bus.h
37
bus.h
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|
@ -52,17 +52,6 @@ class memory;
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|||
class tm_11;
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||||
class tty;
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||||
|
||||
typedef enum { T_PROCEED, T_ABORT_4, T_TRAP_250 } trap_action_t;
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|
||||
typedef struct {
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uint16_t virtual_address;
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||||
uint8_t apf; // active page field
|
||||
uint32_t physical_instruction;
|
||||
bool physical_instruction_is_psw;
|
||||
uint32_t physical_data;
|
||||
bool physical_data_is_psw;
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} memory_addresses_t;
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||||
|
||||
typedef struct {
|
||||
bool is_psw;
|
||||
} write_rc_t;
|
||||
|
|
@ -104,8 +93,6 @@ public:
|
|||
|
||||
void set_memory_size(const int n_pages);
|
||||
|
||||
void mmudebug(const uint16_t a);
|
||||
|
||||
void add_ram (memory *const m );
|
||||
void add_cpu (cpu *const c );
|
||||
void add_mmu (mmu *const mmu_ );
|
||||
|
|
@ -124,30 +111,18 @@ public:
|
|||
rl02 *getRL02() { return rl02_; }
|
||||
tm_11 *getTM11() { return tm11; }
|
||||
|
||||
uint16_t read (const uint16_t a, const word_mode_t word_mode, const rm_selection_t mode_selection, const bool peek_only=false, const d_i_space_t s = i_space);
|
||||
uint16_t read(const uint16_t a, const word_mode_t word_mode, const rm_selection_t mode_selection, const bool peek_only=false, const d_i_space_t s = i_space);
|
||||
uint16_t read_byte(const uint16_t a) { return read(a, wm_byte, rm_cur); }
|
||||
uint16_t read_word(const uint16_t a, const d_i_space_t s = i_space);
|
||||
uint16_t peekWord(const uint16_t a);
|
||||
|
||||
uint8_t readUnibusByte(const uint32_t a);
|
||||
void writeUnibusByte(const uint32_t a, const uint8_t value);
|
||||
|
||||
write_rc_t write (const uint16_t a, const word_mode_t word_mode, uint16_t value, const rm_selection_t mode_selection, const d_i_space_t s = i_space);
|
||||
void write_byte(const uint16_t a, const uint8_t value) { write(a, wm_byte, value, rm_cur); }
|
||||
void write_word(const uint16_t a, const uint16_t value, const d_i_space_t s = i_space);
|
||||
|
||||
uint16_t readPhysical(const uint32_t a);
|
||||
|
||||
write_rc_t write(const uint16_t a, const word_mode_t word_mode, uint16_t value, const rm_selection_t mode_selection, const d_i_space_t s = i_space);
|
||||
void writeUnibusByte(const uint32_t a, const uint8_t value);
|
||||
void write_byte(const uint16_t a, const uint8_t value) { write(a, wm_byte, value, rm_cur); }
|
||||
void write_word(const uint16_t a, const uint16_t value, const d_i_space_t s = i_space);
|
||||
void writePhysical(const uint32_t a, const uint16_t value);
|
||||
|
||||
void check_odd_addressing(const uint16_t a, const int run_mode, const d_i_space_t space, const bool is_write);
|
||||
void trap_odd(const uint16_t a);
|
||||
|
||||
uint32_t get_io_base() const { return mmu_->getMMR0() & 1 ? (mmu_->getMMR3() & 16 ? 017760000 : 0760000) : 0160000; }
|
||||
bool is_psw(const uint16_t addr, const int run_mode, const d_i_space_t space) const;
|
||||
|
||||
std::pair<trap_action_t, int> get_trap_action(const int run_mode, const bool d, const int apf, const bool is_write);
|
||||
uint32_t calculate_physical_address(const int run_mode, const uint16_t a, const bool trap_on_failure, const bool is_write, const bool peek_only, const d_i_space_t space);
|
||||
|
||||
memory_addresses_t calculate_physical_address(const int run_mode, const uint16_t a) const;
|
||||
void check_address(const bool trap_on_failure, const bool is_write, const memory_addresses_t & addr, const word_mode_t word_mode, const bool is_data, const int run_mode);
|
||||
};
|
||||
|
|
|
|||
|
|
@ -145,7 +145,7 @@ void console_ncurses::panel_update_thread()
|
|||
int run_mode = current_PSW >> 14;
|
||||
|
||||
uint16_t current_PC = c->getPC();
|
||||
uint32_t full_addr = b->calculate_physical_address(run_mode, current_PC, false, false, true, i_space);
|
||||
uint32_t full_addr = b->getMMU()->calculate_physical_address(c, run_mode, current_PC, false, false, true, i_space);
|
||||
|
||||
uint16_t current_instr = b->read_word(current_PC);
|
||||
|
||||
|
|
|
|||
7
cpu.cpp
7
cpu.cpp
|
|
@ -6,11 +6,14 @@
|
|||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "breakpoint.h"
|
||||
#include "bus.h"
|
||||
#include "cpu.h"
|
||||
#include "gen.h"
|
||||
#include "log.h"
|
||||
#include "utils.h"
|
||||
|
||||
|
||||
#define SIGN(x, wm) ((wm) == wm_byte ? (x) & 0x80 : (x) & 0x8000)
|
||||
|
||||
#define IS_0(x, wm) ((wm) == wm_byte ? ((x) & 0xff) == 0 : (x) == 0)
|
||||
|
|
@ -1390,7 +1393,7 @@ bool cpu::single_operand_instructions(const uint16_t instr)
|
|||
}
|
||||
else {
|
||||
auto a = getGAM(dst_mode, dst_reg, word_mode, rm_cur);
|
||||
addToMMR1(a);
|
||||
addToMMR1(a);
|
||||
uint16_t vl = a.value.value();
|
||||
uint16_t v = (vl << 1) & (word_mode == wm_byte ? 0xff : 0xffff);
|
||||
|
||||
|
|
@ -1441,7 +1444,7 @@ bool cpu::single_operand_instructions(const uint16_t instr)
|
|||
auto a = getGAMAddress(dst_mode, dst_reg, wm_word);
|
||||
addToMMR1(a);
|
||||
|
||||
b->mmudebug(a.addr.value());
|
||||
b->getMMU()->mmudebug(a.addr.value());
|
||||
|
||||
a.mode_selection = rm_prev;
|
||||
a.space = word_mode == wm_byte ? d_space : i_space;
|
||||
|
|
|
|||
8
cpu.h
8
cpu.h
|
|
@ -3,7 +3,8 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#include <assert.h>
|
||||
#include <atomic>
|
||||
#include <cassert>
|
||||
#include <condition_variable>
|
||||
#include <map>
|
||||
#include <mutex>
|
||||
|
|
@ -12,11 +13,12 @@
|
|||
#include <stdint.h>
|
||||
#include <vector>
|
||||
|
||||
#include "breakpoint.h"
|
||||
#include "bus.h"
|
||||
#include "gen.h"
|
||||
|
||||
|
||||
class breakpoint;
|
||||
class bus;
|
||||
|
||||
constexpr const int initial_trap_delay = 8;
|
||||
|
||||
constexpr const int max_stacktrace_depth = 16;
|
||||
|
|
|
|||
|
|
@ -498,7 +498,7 @@ void mmu_resolve(console *const cnsl, bus *const b, const uint16_t va)
|
|||
int run_mode = b->getCpu()->getPSW_runmode();
|
||||
cnsl->put_string_lf(format("Run mode: %d, use data space: %d", run_mode, b->getMMU()->get_use_data_space(run_mode)));
|
||||
|
||||
auto data = b->calculate_physical_address(run_mode, va);
|
||||
auto data = b->getMMU()->calculate_physical_address(run_mode, va);
|
||||
|
||||
uint16_t page_offset = va & 8191;
|
||||
cnsl->put_string_lf(format("Active page field: %d, page offset: %o (%d)", data.apf, page_offset, page_offset));
|
||||
|
|
@ -521,8 +521,8 @@ void mmu_resolve(console *const cnsl, bus *const b, const uint16_t va)
|
|||
}
|
||||
|
||||
for(int i=0; i<2; i++) {
|
||||
auto ta_i = b->get_trap_action(run_mode, false, data.apf, i);
|
||||
auto ta_d = b->get_trap_action(run_mode, true, data.apf, i);
|
||||
auto ta_i = b->getMMU()->get_trap_action(run_mode, false, data.apf, i);
|
||||
auto ta_d = b->getMMU()->get_trap_action(run_mode, true, data.apf, i);
|
||||
|
||||
cnsl->put_string_lf(format("Instruction action: %s (%s)", trap_action_to_str(ta_i.first), i ? "write" : "read"));
|
||||
cnsl->put_string_lf(format("Data action : %s (%s)", trap_action_to_str(ta_d.first), i ? "write" : "read"));
|
||||
|
|
|
|||
240
mmu.cpp
240
mmu.cpp
|
|
@ -1,6 +1,7 @@
|
|||
#include <cassert>
|
||||
#include <cstring>
|
||||
|
||||
#include "bus.h" // for (at least) ADDR_PSW
|
||||
#include "gen.h"
|
||||
#include "log.h"
|
||||
#include "mmu.h"
|
||||
|
|
@ -15,8 +16,10 @@ mmu::~mmu()
|
|||
{
|
||||
}
|
||||
|
||||
void mmu::begin()
|
||||
void mmu::begin(memory *const m)
|
||||
{
|
||||
this->m = m;
|
||||
|
||||
reset();
|
||||
}
|
||||
|
||||
|
|
@ -213,6 +216,237 @@ void mmu::write_byte(const uint16_t a, const uint8_t value)
|
|||
write_par(a, 3, value, wm_byte);
|
||||
}
|
||||
|
||||
void mmu::trap_if_odd(const uint16_t a, const int run_mode, const d_i_space_t space, const bool is_write)
|
||||
{
|
||||
int page = a >> 13;
|
||||
|
||||
if (is_write)
|
||||
set_page_trapped(run_mode, space == d_space, page);
|
||||
|
||||
MMR0 &= ~(7 << 1);
|
||||
MMR0 |= page << 1;
|
||||
}
|
||||
|
||||
memory_addresses_t mmu::calculate_physical_address(const int run_mode, const uint16_t a) const
|
||||
{
|
||||
const uint8_t apf = a >> 13; // active page field
|
||||
|
||||
if (is_enabled() == false) {
|
||||
bool is_psw = a == ADDR_PSW;
|
||||
return { a, apf, a, is_psw, a, is_psw };
|
||||
}
|
||||
|
||||
uint32_t physical_instruction = get_physical_memory_offset(run_mode, 0, apf);
|
||||
uint32_t physical_data = get_physical_memory_offset(run_mode, 1, apf);
|
||||
|
||||
uint16_t p_offset = a & 8191; // page offset
|
||||
|
||||
physical_instruction += p_offset;
|
||||
physical_data += p_offset;
|
||||
|
||||
if ((getMMR3() & 16) == 0) { // offset is 18bit
|
||||
physical_instruction &= 0x3ffff;
|
||||
physical_data &= 0x3ffff;
|
||||
}
|
||||
|
||||
if (get_use_data_space(run_mode) == false)
|
||||
physical_data = physical_instruction;
|
||||
|
||||
uint32_t io_base = get_io_base();
|
||||
bool physical_instruction_is_psw = (physical_instruction - io_base + 0160000) == ADDR_PSW;
|
||||
bool physical_data_is_psw = (physical_data - io_base + 0160000) == ADDR_PSW;
|
||||
|
||||
return { a, apf, physical_instruction, physical_instruction_is_psw, physical_data, physical_data_is_psw };
|
||||
}
|
||||
|
||||
std::pair<trap_action_t, int> mmu::get_trap_action(const int run_mode, const bool d, const int apf, const bool is_write)
|
||||
{
|
||||
const int access_control = get_access_control(run_mode, d, apf);
|
||||
|
||||
trap_action_t trap_action = T_PROCEED;
|
||||
|
||||
if (access_control == 0)
|
||||
trap_action = T_ABORT_4;
|
||||
else if (access_control == 1)
|
||||
trap_action = is_write ? T_ABORT_4 : T_TRAP_250;
|
||||
else if (access_control == 2) {
|
||||
if (is_write)
|
||||
trap_action = T_ABORT_4;
|
||||
}
|
||||
else if (access_control == 3)
|
||||
trap_action = T_ABORT_4;
|
||||
else if (access_control == 4)
|
||||
trap_action = T_TRAP_250;
|
||||
else if (access_control == 5) {
|
||||
if (is_write)
|
||||
trap_action = T_TRAP_250;
|
||||
}
|
||||
else if (access_control == 6) {
|
||||
// proceed
|
||||
}
|
||||
else if (access_control == 7) {
|
||||
trap_action = T_ABORT_4;
|
||||
}
|
||||
|
||||
return { trap_action, access_control };
|
||||
}
|
||||
|
||||
void mmu::mmudebug(const uint16_t a)
|
||||
{
|
||||
for(int rm=0; rm<4; rm++) {
|
||||
auto ma = calculate_physical_address(rm, a);
|
||||
|
||||
DOLOG(debug, false, "RM %d, a: %06o, apf: %d, PI: %08o (PSW: %d), PD: %08o (PSW: %d)", rm, ma.virtual_address, ma.apf, ma.physical_instruction, ma.physical_instruction_is_psw, ma.physical_data, ma.physical_data_is_psw);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t mmu::calculate_physical_address(cpu *const c, const int run_mode, const uint16_t a, const bool trap_on_failure, const bool is_write, const bool peek_only, const d_i_space_t space)
|
||||
{
|
||||
uint32_t m_offset = a;
|
||||
|
||||
if (is_enabled() || (is_write && (getMMR0() & (1 << 8 /* maintenance check */)))) {
|
||||
uint8_t apf = a >> 13; // active page field
|
||||
|
||||
bool d = space == d_space && get_use_data_space(run_mode);
|
||||
|
||||
uint16_t p_offset = a & 8191; // page offset
|
||||
|
||||
m_offset = get_physical_memory_offset(run_mode, d, apf);
|
||||
|
||||
m_offset += p_offset;
|
||||
|
||||
if ((getMMR3() & 16) == 0) // off is 18bit
|
||||
m_offset &= 0x3ffff;
|
||||
|
||||
uint32_t io_base = get_io_base();
|
||||
bool is_io = m_offset >= io_base;
|
||||
|
||||
if (trap_on_failure) [[unlikely]] {
|
||||
{
|
||||
auto rc = get_trap_action(run_mode, d, apf, is_write);
|
||||
auto trap_action = rc.first;
|
||||
int access_control = rc.second;
|
||||
|
||||
if (trap_action != T_PROCEED) {
|
||||
if (is_write)
|
||||
set_page_trapped(run_mode, d, apf);
|
||||
|
||||
if (is_locked() == false) {
|
||||
uint16_t temp = getMMR0();
|
||||
|
||||
temp &= ~((1l << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (3 << 5) | (7 << 1) | (1 << 4));
|
||||
|
||||
if (is_write && access_control != 6)
|
||||
temp |= 1 << 13; // read-only
|
||||
//
|
||||
if (access_control == 0 || access_control == 4)
|
||||
temp |= 1l << 15; // not resident
|
||||
else
|
||||
temp |= 1 << 13; // read-only
|
||||
|
||||
temp |= run_mode << 5; // TODO: kernel-mode or user-mode when a trap occurs in user-mode?
|
||||
|
||||
temp |= apf << 1; // add current page
|
||||
|
||||
temp |= d << 4;
|
||||
|
||||
setMMR0(temp);
|
||||
|
||||
DOLOG(debug, false, "MMR0: %06o", temp);
|
||||
}
|
||||
|
||||
if (trap_action == T_TRAP_250) {
|
||||
DOLOG(debug, false, "Page access %d (for virtual address %06o): trap 0250", access_control, a);
|
||||
|
||||
c->trap(0250); // trap
|
||||
|
||||
throw 5;
|
||||
}
|
||||
else { // T_ABORT_4
|
||||
DOLOG(debug, false, "Page access %d (for virtual address %06o): trap 004", access_control, a);
|
||||
|
||||
c->trap(004); // abort
|
||||
|
||||
throw 5;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (m_offset >= m->get_memory_size() && !is_io) [[unlikely]] {
|
||||
DOLOG(debug, !peek_only, "mmu::calculate_physical_address %o >= %o", m_offset, m->get_memory_size());
|
||||
DOLOG(debug, false, "TRAP(04) (throw 6) on address %06o", a);
|
||||
|
||||
if (is_locked() == false) {
|
||||
uint16_t temp = getMMR0();
|
||||
|
||||
temp &= 017777;
|
||||
temp |= 1l << 15; // non-resident
|
||||
|
||||
temp &= ~14; // add current page
|
||||
temp |= apf << 1;
|
||||
|
||||
temp &= ~(3 << 5);
|
||||
temp |= run_mode << 5;
|
||||
|
||||
setMMR0(temp);
|
||||
}
|
||||
|
||||
if (is_write)
|
||||
set_page_trapped(run_mode, d, apf);
|
||||
|
||||
c->trap(04);
|
||||
|
||||
throw 6;
|
||||
}
|
||||
|
||||
uint16_t pdr_len = get_pdr_len(run_mode, d, apf);
|
||||
uint16_t pdr_cmp = (a >> 6) & 127;
|
||||
|
||||
bool direction = get_pdr_direction(run_mode, d, apf);
|
||||
|
||||
// DOLOG(debug, false, "p_offset %06o pdr_len %06o direction %d, run_mode %d, apf %d, pdr: %06o", p_offset, pdr_len, direction, run_mode, apf, pages[run_mode][d][apf].pdr);
|
||||
|
||||
if ((pdr_cmp > pdr_len && direction == false) || (pdr_cmp < pdr_len && direction == true)) {
|
||||
DOLOG(debug, false, "mmu::calculate_physical_address::p_offset %o versus %o direction %d", pdr_cmp, pdr_len, direction);
|
||||
DOLOG(debug, false, "TRAP(0250) (throw 7) on address %06o", a);
|
||||
c->trap(0250); // invalid access
|
||||
|
||||
if (is_locked() == false) {
|
||||
uint16_t temp = getMMR0();
|
||||
|
||||
temp &= 017777;
|
||||
temp |= 1 << 14; // length
|
||||
|
||||
temp &= ~14; // add current page
|
||||
temp |= apf << 1;
|
||||
|
||||
temp &= ~(3 << 5);
|
||||
temp |= run_mode << 5;
|
||||
|
||||
temp &= ~(1 << 4);
|
||||
temp |= d << 4;
|
||||
|
||||
setMMR0(temp);
|
||||
}
|
||||
|
||||
if (is_write)
|
||||
set_page_trapped(run_mode, d, apf);
|
||||
|
||||
throw 7;
|
||||
}
|
||||
}
|
||||
|
||||
DOLOG(debug, false, "virtual address %06o maps to physical address %08o (run_mode: %d, apf: %d, par: %08o, poff: %o, AC: %d, %s)", a, m_offset, run_mode, apf,
|
||||
get_physical_memory_offset(run_mode, d, apf),
|
||||
p_offset, get_access_control(run_mode, d, apf), d ? "D" : "I");
|
||||
}
|
||||
else {
|
||||
// DOLOG(debug, false, "no MMU (read physical address %08o)", m_offset);
|
||||
}
|
||||
|
||||
return m_offset;
|
||||
}
|
||||
|
||||
#if IS_POSIX
|
||||
void mmu::add_par_pdr(json_t *const target, const int run_mode, const bool is_d, const std::string & name) const
|
||||
{
|
||||
|
|
@ -266,10 +500,10 @@ void mmu::set_par_pdr(const json_t *const j_in, const int run_mode, const bool i
|
|||
pages[run_mode][is_d][i].pdr = json_integer_value(json_array_get(j_pdr, i));
|
||||
}
|
||||
|
||||
mmu *mmu::deserialize(const json_t *const j)
|
||||
mmu *mmu::deserialize(const json_t *const j, memory *const mem)
|
||||
{
|
||||
mmu *m = new mmu();
|
||||
m->begin();
|
||||
m->begin(mem);
|
||||
|
||||
for(int run_mode=0; run_mode<4; run_mode++) {
|
||||
if (run_mode == 2)
|
||||
|
|
|
|||
31
mmu.h
31
mmu.h
|
|
@ -3,8 +3,11 @@
|
|||
#include <cstdint>
|
||||
#include <string>
|
||||
|
||||
#include "device.h"
|
||||
#include "gen.h"
|
||||
#include "cpu.h"
|
||||
#include "device.h"
|
||||
#include "memory.h"
|
||||
|
||||
|
||||
#define ADDR_PDR_SV_START 0172200
|
||||
#define ADDR_PDR_SV_END 0172240
|
||||
|
|
@ -22,6 +25,17 @@
|
|||
#define ADDR_PAR_U_END 0177700
|
||||
|
||||
|
||||
typedef enum { T_PROCEED, T_ABORT_4, T_TRAP_250 } trap_action_t;
|
||||
|
||||
typedef struct {
|
||||
uint16_t virtual_address;
|
||||
uint8_t apf; // active page field
|
||||
uint32_t physical_instruction;
|
||||
bool physical_instruction_is_psw;
|
||||
uint32_t physical_data;
|
||||
bool physical_data_is_psw;
|
||||
} memory_addresses_t;
|
||||
|
||||
typedef struct {
|
||||
uint16_t par;
|
||||
uint16_t pdr;
|
||||
|
|
@ -41,6 +55,8 @@ private:
|
|||
uint16_t PIR { 0 };
|
||||
uint16_t CSR { 0 };
|
||||
|
||||
memory *m { nullptr };
|
||||
|
||||
#if IS_POSIX
|
||||
void add_par_pdr(json_t *const target, const int run_mode, const bool is_d, const std::string & name) const;
|
||||
void set_par_pdr(const json_t *const j_in, const int run_mode, const bool is_d, const std::string & name);
|
||||
|
|
@ -50,13 +66,15 @@ public:
|
|||
mmu();
|
||||
virtual ~mmu();
|
||||
|
||||
void begin();
|
||||
void begin(memory *const m);
|
||||
|
||||
#if IS_POSIX
|
||||
json_t *serialize() const;
|
||||
static mmu *deserialize(const json_t *const j);
|
||||
static mmu *deserialize(const json_t *const j, memory *const m);
|
||||
#endif
|
||||
|
||||
void mmudebug(const uint16_t a);
|
||||
|
||||
void reset() override;
|
||||
|
||||
bool is_enabled() const { return MMR0 & 1; }
|
||||
|
|
@ -69,6 +87,11 @@ public:
|
|||
int get_pdr_direction (const int run_mode, const bool d, const int apf) { return pages[run_mode][d][apf].pdr & 8; }
|
||||
uint32_t get_physical_memory_offset(const int run_mode, const bool d, const int apf) const { return pages[run_mode][d][apf].par * 64; }
|
||||
bool get_use_data_space(const int run_mode) const;
|
||||
uint32_t get_io_base() const { return getMMR0() & 1 ? (getMMR3() & 16 ? 017760000 : 0760000) : 0160000; }
|
||||
|
||||
memory_addresses_t calculate_physical_address(const int run_mode, const uint16_t a) const;
|
||||
std::pair<trap_action_t, int> get_trap_action(const int run_mode, const bool d, const int apf, const bool is_write);
|
||||
uint32_t calculate_physical_address(cpu *const c, const int run_mode, const uint16_t a, const bool trap_on_failure, const bool is_write, const bool peek_only, const d_i_space_t space);
|
||||
|
||||
uint16_t getMMR0() const { return MMR0; }
|
||||
uint16_t getMMR1() const { return MMR1; }
|
||||
|
|
@ -88,6 +111,8 @@ public:
|
|||
void setMMR0Bit(const int bit);
|
||||
void clearMMR0Bit(const int bit);
|
||||
|
||||
void trap_if_odd(const uint16_t a, const int run_mode, const d_i_space_t space, const bool is_write);
|
||||
|
||||
uint16_t getCPUERR() const { return CPUERR; }
|
||||
void setCPUERR(const uint16_t v) { CPUERR = v; }
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue