diff --git a/cpu.cpp b/cpu.cpp
index 5e65150..8a6400d 100644
--- a/cpu.cpp
+++ b/cpu.cpp
@@ -510,7 +510,7 @@ bool cpu::additional_double_operand_instructions(const uint16_t instr)
 				int16_t  R     = getRegister(reg), oldR = R;
 				uint16_t a     = getGAMAddress(dst_mode, dst_reg, false, false);
 				int16_t  shift = b->read(a, false) & 077; // mask of lower 6 bit
-
+				
 				if (shift == 0)
 					setPSW_c(false);
 				else if (shift < 32) {
@@ -521,9 +521,9 @@ bool cpu::additional_double_operand_instructions(const uint16_t instr)
 				else {
 					// extend sign-bit
 					if (R & 0x8000)  // convert to unsigned 32b int & extend sign
-						R = (uint32_t(R) | 0xffff0000) >> (64 - (shift - 1));
+						R = (uint32_t(R) | 0xffff0000) >> (64 - (shift + 1));
 					else
-						R >>= 64 - (shift - 1);
+						R >>= 64 - (shift + 1);
 
 					setPSW_c(R & 1);
 					R >>= 1;
@@ -556,17 +556,17 @@ bool cpu::additional_double_operand_instructions(const uint16_t instr)
 				else {
 					// extend sign-bit
 					if (R0R1 & 0x80000000)  // convert to unsigned 64b int & extend sign
-						R0R1 = (uint64_t(R0R1) | 0xffffffff00000000ll) >> (64 - (shift - 1));
+						R0R1 = (uint64_t(R0R1) | 0xffffffff00000000ll) >> (64 - (shift + 1));
 					else
-						R0R1 >>= 64 - (shift - 1);
+						R0R1 >>= 64 - (shift + 1);
 
 					setPSW_c(R0R1 & 1);
 
 					R0R1 >>= 1;
 				}
 
-				setRegister(reg, R0R1 & 65535);
-				setRegister(reg + 1, R0R1 >> 16);
+				setRegister(reg, R0R1 >> 16);
+				setRegister(reg + 1, R0R1 & 65535);
 
 				setPSW_n(R0R1 >> 31);
 				setPSW_z(R0R1 == 0);