double trap handling (work in progress)
This commit is contained in:
parent
f4d991e86a
commit
ad44232120
2 changed files with 59 additions and 34 deletions
41
cpu.cpp
41
cpu.cpp
|
@ -1656,11 +1656,29 @@ void cpu::schedule_trap(const uint16_t vector)
|
||||||
}
|
}
|
||||||
|
|
||||||
// 'is_interrupt' is not correct naming; it is true for mmu faults and interrupts
|
// 'is_interrupt' is not correct naming; it is true for mmu faults and interrupts
|
||||||
void cpu::trap(const uint16_t vector, const int new_ipl, const bool is_interrupt)
|
void cpu::trap(uint16_t vector, const int new_ipl, const bool is_interrupt)
|
||||||
{
|
{
|
||||||
DOLOG(debug, true, "*** CPU::TRAP ***");
|
DOLOG(debug, true, "*** CPU::TRAP ***");
|
||||||
uint16_t before_psw = getPSW();
|
|
||||||
uint16_t before_pc = getPC();
|
int processing_trap_depth = 0;
|
||||||
|
uint16_t before_psw = 0;
|
||||||
|
uint16_t before_pc = 0;
|
||||||
|
|
||||||
|
for(;;) {
|
||||||
|
try {
|
||||||
|
processing_trap_depth++;
|
||||||
|
|
||||||
|
if (processing_trap_depth >= 2) {
|
||||||
|
vector = 4;
|
||||||
|
|
||||||
|
if (processing_trap_depth >= 3) {
|
||||||
|
// TODO: halt?
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
before_psw = getPSW();
|
||||||
|
before_pc = getPC();
|
||||||
|
}
|
||||||
|
|
||||||
// make sure the trap vector is retrieved from kernel space
|
// make sure the trap vector is retrieved from kernel space
|
||||||
psw &= 037777; // mask off 14/15
|
psw &= 037777; // mask off 14/15
|
||||||
|
@ -1689,6 +1707,18 @@ void cpu::trap(const uint16_t vector, const int new_ipl, const bool is_interrupt
|
||||||
|
|
||||||
pushStack(before_psw);
|
pushStack(before_psw);
|
||||||
pushStack(before_pc);
|
pushStack(before_pc);
|
||||||
|
|
||||||
|
// if we reach this point then the trap was processed without causing
|
||||||
|
// another trap
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
catch(const int exception) {
|
||||||
|
DOLOG(debug, true, "trap during execution of trap (%d)", exception);
|
||||||
|
|
||||||
|
setPSW(before_psw, false);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
DOLOG(debug, true, "*** CPU::TRAP FIN, MMR0: %06o, MMR2: %06o ***", b->getMMR0(), b->getMMR2());
|
DOLOG(debug, true, "*** CPU::TRAP FIN, MMR0: %06o, MMR2: %06o ***", b->getMMR0(), b->getMMR2());
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -2171,12 +2201,7 @@ void cpu::step_a()
|
||||||
b->clearMMR1();
|
b->clearMMR1();
|
||||||
|
|
||||||
if (scheduled_trap) {
|
if (scheduled_trap) {
|
||||||
try {
|
|
||||||
trap(scheduled_trap, 7, true);
|
trap(scheduled_trap, 7, true);
|
||||||
}
|
|
||||||
catch(const int exception) {
|
|
||||||
DOLOG(debug, true, "2nd-bus-trap during execution of command (%d)", exception);
|
|
||||||
}
|
|
||||||
|
|
||||||
scheduled_trap = 0;
|
scheduled_trap = 0;
|
||||||
|
|
||||||
|
|
2
cpu.h
2
cpu.h
|
@ -96,7 +96,7 @@ public:
|
||||||
void queue_interrupt(const uint8_t level, const uint8_t vector);
|
void queue_interrupt(const uint8_t level, const uint8_t vector);
|
||||||
|
|
||||||
void busError();
|
void busError();
|
||||||
void trap(const uint16_t vector, const int new_ipl = -1, const bool is_interrupt = false);
|
void trap(uint16_t vector, const int new_ipl = -1, const bool is_interrupt = false);
|
||||||
void schedule_trap(const uint16_t vector);
|
void schedule_trap(const uint16_t vector);
|
||||||
|
|
||||||
void setEmulateMFPT(const bool v) { emulateMFPT = v; }
|
void setEmulateMFPT(const bool v) { emulateMFPT = v; }
|
||||||
|
|
Loading…
Add table
Reference in a new issue