bus: trap(4) when reading from/writing to i/o or ram that does not exists/is not mapped
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389bc57405
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c77ae1d617
1 changed files with 35 additions and 3 deletions
38
bus.cpp
38
bus.cpp
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@ -177,6 +177,17 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev,
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return read_par(a, 3, word_mode, peek_only);
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return read_par(a, 3, word_mode, peek_only);
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///////////
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///////////
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if (a >= 0177740 && a <= 0177753) { // cache control register and others
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// TODO
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return 0;
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}
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if (a >= 0170200 && a <= 0170377) { // unibus map
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DOLOG(debug, !peek_only, "reading unibus map (%06o)", a);
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// TODO
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return 0;
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}
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if (word_mode) {
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if (word_mode) {
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if (a == ADDR_PSW) { // PSW
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if (a == ADDR_PSW) { // PSW
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DOLOG(debug, !peek_only, "readb PSW LSB");
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DOLOG(debug, !peek_only, "readb PSW LSB");
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@ -275,9 +286,13 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev,
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return system_size;
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return system_size;
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}
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}
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if (!peek_only)
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if (!peek_only) {
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DOLOG(debug, true, "UNHANDLED read %o(%c)", a, word_mode ? 'B' : ' ');
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DOLOG(debug, true, "UNHANDLED read %o(%c)", a, word_mode ? 'B' : ' ');
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DOLOG(debug, false, "Read non existing I/O (%06o)", a);
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c->schedule_trap(004); // no such i/o
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}
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return -1;
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return -1;
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}
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}
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@ -291,6 +306,11 @@ uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev,
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uint32_t m_offset = calculate_physical_address(run_mode, a, !peek_only, false, peek_only, space == d_space);
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uint32_t m_offset = calculate_physical_address(run_mode, a, !peek_only, false, peek_only, space == d_space);
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if (peek_only == false && m_offset >= n_pages * 8192) {
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DOLOG(debug, false, "Read non existing mapped memory (%o >= %o)", m_offset, n_pages * 8192);
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c->schedule_trap(004); // no such memory
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}
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if (word_mode)
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if (word_mode)
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temp = m -> readByte(m_offset);
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temp = m -> readByte(m_offset);
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else
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else
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@ -766,7 +786,13 @@ void bus::write(const uint16_t a, const bool word_mode, uint16_t value, const bo
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}
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}
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////
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////
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if (a == ADDR_CCR) { // cache control register
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if (a >= 0177740 && a <= 0177753) { // cache control register and others
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// TODO
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return;
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}
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if (a >= 0170200 && a <= 0170377) { // unibus map
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DOLOG(debug, false, "writing %06o to unibus map (%06o)", value, a);
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// TODO
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// TODO
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return;
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return;
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}
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}
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@ -787,7 +813,8 @@ void bus::write(const uint16_t a, const bool word_mode, uint16_t value, const bo
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return;
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return;
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}
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}
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// c -> busError();
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DOLOG(debug, false, "Write non existing I/O (%06o, value: %06o)", a, value);
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c->schedule_trap(004); // no such i/o
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return;
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return;
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}
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}
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@ -801,6 +828,11 @@ void bus::write(const uint16_t a, const bool word_mode, uint16_t value, const bo
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uint32_t m_offset = calculate_physical_address(run_mode, a, true, true, false, space == d_space);
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uint32_t m_offset = calculate_physical_address(run_mode, a, true, true, false, space == d_space);
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if (m_offset >= n_pages * 8192) {
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DOLOG(debug, false, "Write non existing mapped memory (%06o, value: %06o)", m_offset, value);
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c->schedule_trap(004); // no such memory
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}
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DOLOG(debug, true, "WRITE to %06o/%07o %c %c: %o", a, m_offset, space == d_space ? 'D' : 'I', word_mode ? 'B' : 'W', value);
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DOLOG(debug, true, "WRITE to %06o/%07o %c %c: %o", a, m_offset, space == d_space ? 'D' : 'I', word_mode ? 'B' : 'W', value);
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if (word_mode)
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if (word_mode)
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