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less shifting & orring in get/setRegister

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folkert van heusden 2022-03-21 14:41:22 +01:00
parent 94c5afb58e
commit f59fb51b38
1 changed files with 6 additions and 8 deletions
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14
cpu.cpp
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@ -42,9 +42,9 @@ uint16_t cpu::getRegister(const int nr, const bool prev_mode) const
if (nr == 6) { if (nr == 6) {
if (prev_mode) if (prev_mode)
return sp[(getBitPSW(13) << 1) | getBitPSW(12)]; return sp[(getPSW() >> 12) & 3];
return sp[(getBitPSW(15) << 1) | getBitPSW(14)]; return sp[getPSW() >> 14];
} }
return pc; return pc;
@ -56,9 +56,9 @@ void cpu::setRegister(const int nr, const bool prev_mode, const uint16_t value)
regs0_5[getBitPSW(11)][nr] = value; regs0_5[getBitPSW(11)][nr] = value;
else if (nr == 6) { else if (nr == 6) {
if (prev_mode) if (prev_mode)
sp[(getBitPSW(13) << 1) | getBitPSW(12)] = value; sp[(getPSW() >> 12) & 3] = value;
else else
sp[(getBitPSW(15) << 1) | getBitPSW(14)] = value; sp[getPSW() >> 14] = value;
} }
else { else {
pc = value; pc = value;
@ -71,14 +71,12 @@ void cpu::addRegister(const int nr, const bool prev_mode, const uint16_t value)
regs0_5[getBitPSW(11)][nr] += value; regs0_5[getBitPSW(11)][nr] += value;
else if (nr == 6) { else if (nr == 6) {
if (prev_mode) if (prev_mode)
sp[(getBitPSW(13) << 1) | getBitPSW(12)] += value; sp[(getPSW() >> 12) & 3] += value;
else else
sp[(getBitPSW(15) << 1) | getBitPSW(14)] += value; sp[getPSW() >> 14] += value;
} }
else { else {
assert((pc & 1) == 0);
pc += value; pc += value;
assert((pc & 1) == 0);
} }
} }