567 lines
14 KiB
C++
567 lines
14 KiB
C++
#include <cassert>
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#include <cstring>
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#include "bus.h" // for (at least) ADDR_PSW
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#include "gen.h"
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#include "log.h"
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#include "mmu.h"
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#include "utils.h"
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mmu::mmu()
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{
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reset();
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}
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mmu::~mmu()
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{
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}
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void mmu::begin(memory *const m, cpu *const c)
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{
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this->m = m;
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this->c = c;
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reset();
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}
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void mmu::reset()
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{
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memset(pages, 0x00, sizeof pages);
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CPUERR = MMR0 = MMR1 = MMR2 = MMR3 = PIR = CSR = 0;
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}
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void mmu::dump_par_pdr(console *const cnsl, const int run_mode, const bool d, const std::string & name, const int state, const std::optional<int> & selection) const
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{
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if (state == 0 || state == 2)
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cnsl->put_string_lf(name);
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else
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cnsl->put_string_lf(format("%s DISABLED", name.c_str()));
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cnsl->put_string_lf(" PAR PDR LEN");
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for(int i=0; i<8; i++) {
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if (selection.has_value() && i != selection.value())
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continue;
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uint16_t par_value = pages[run_mode][d][i].par;
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uint16_t pdr_value = pages[run_mode][d][i].pdr;
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uint16_t pdr_len = (((pdr_value >> 8) & 127) + 1) * 64;
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cnsl->put_string_lf(format("%d] %06o %08o %06o %04o D%d A%d", i, par_value, par_value * 64, pdr_value, pdr_len, !!(pdr_value & 8), pdr_value & 7));
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}
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}
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void mmu::show_state(console *const cnsl) const
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{
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cnsl->put_string_lf(MMR0 & 1 ? "MMU enabled" : "MMU NOT enabled");
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cnsl->put_string_lf(format("MMR0: %06o", MMR0));
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cnsl->put_string_lf(format("MMR1: %06o", MMR1));
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cnsl->put_string_lf(format("MMR2: %06o", MMR2));
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cnsl->put_string_lf(format("MMR3: %06o", MMR3));
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dump_par_pdr(cnsl, 1, false, "supervisor i-space", 0, { });
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dump_par_pdr(cnsl, 1, true, "supervisor d-space", 1 + (!!(MMR3 & 2)), { });
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dump_par_pdr(cnsl, 0, false, "kernel i-space", 0, { });
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dump_par_pdr(cnsl, 0, true, "kernel d-space", 1 + (!!(MMR3 & 2)), { });
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dump_par_pdr(cnsl, 3, false, "user i-space", 0, { });
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dump_par_pdr(cnsl, 3, true, "user d-space", 1 + (!!(MMR3 & 2)), { });
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}
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uint16_t mmu::read_pdr(const uint32_t a, const int run_mode)
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{
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int page = (a >> 1) & 7;
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bool is_d = a & 16;
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uint16_t t = pages[run_mode][is_d][page].pdr;
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return t;
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}
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uint16_t mmu::read_par(const uint32_t a, const int run_mode)
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{
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int page = (a >> 1) & 7;
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bool is_d = a & 16;
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uint16_t t = pages[run_mode][is_d][page].par;
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return t;
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}
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void mmu::setMMR0_as_is(uint16_t value)
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{
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MMR0 = value;
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}
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void mmu::setMMR0(uint16_t value)
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{
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value &= ~(3 << 10); // bit 10 & 11 always read as 0
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if (value & 1)
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value &= ~(7l << 13); // reset error bits
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if (MMR0 & 0160000) {
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if ((value & 1) == 0)
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value &= 254; // bits 7...1 are protected
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}
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MMR0 = value;
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}
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void mmu::setMMR0Bit(const int bit)
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{
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assert(bit != 10 && bit != 11);
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assert(bit < 16 && bit >= 0);
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MMR0 |= 1 << bit;
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}
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void mmu::clearMMR0Bit(const int bit)
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{
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assert(bit != 10 && bit != 11);
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assert(bit < 16 && bit >= 0);
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MMR0 &= ~(1 << bit);
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}
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void mmu::setMMR2(const uint16_t value)
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{
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MMR2 = value;
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}
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void mmu::setMMR3(const uint16_t value)
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{
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MMR3 = value;
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}
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bool mmu::get_use_data_space(const int run_mode) const
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{
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constexpr const int di_ena_mask[4] = { 4, 2, 0, 1 };
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return MMR3 & di_ena_mask[run_mode];
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}
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void mmu::clearMMR1()
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{
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MMR1 = 0;
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}
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void mmu::addToMMR1(const int8_t delta, const uint8_t reg)
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{
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assert(reg >= 0 && reg <= 7);
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assert(delta >= -2 && delta <= 2);
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assert((getMMR0() & 0160000) == 0); // MMR1 should not be locked
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MMR1 <<= 8;
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MMR1 |= (delta & 31) << 3;
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MMR1 |= reg;
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}
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void mmu::write_pdr(const uint32_t a, const int run_mode, const uint16_t value, const word_mode_t word_mode)
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{
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bool is_d = a & 16;
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int page = (a >> 1) & 7;
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if (word_mode == wm_byte) {
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assert(a != 0 || value < 256);
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update_word(&pages[run_mode][is_d][page].pdr, a & 1, value);
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}
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else {
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pages[run_mode][is_d][page].pdr = value;
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}
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pages[run_mode][is_d][page].pdr &= ~(32768 + 128 /*A*/ + 64 /*W*/ + 32 + 16); // set bit 4, 5 & 15 to 0 as they are unused and A/W are set to 0 by writes
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TRACE("mmu WRITE-I/O PDR run-mode %d: %c for %d: %o [%d]", run_mode, is_d ? 'D' : 'I', page, value, word_mode);
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}
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void mmu::write_par(const uint32_t a, const int run_mode, const uint16_t value, const word_mode_t word_mode)
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{
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bool is_d = a & 16;
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int page = (a >> 1) & 7;
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if (word_mode == wm_byte)
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update_word(&pages[run_mode][is_d][page].par, a & 1, value);
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else
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pages[run_mode][is_d][page].par = value;
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pages[run_mode][is_d][page].pdr &= ~(128 /*A*/ + 64 /*W*/); // reset PDR A/W when PAR is written to
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TRACE("mmu WRITE-I/O PAR run-mode %d: %c for %d: %o (%07o)", run_mode, is_d ? 'D' : 'I', page, word_mode == wm_byte ? value & 0xff : value, pages[run_mode][is_d][page].par * 64);
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}
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uint16_t mmu::read_word(const uint16_t a)
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{
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uint16_t v = 0;
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if (a >= ADDR_PDR_SV_START && a < ADDR_PDR_SV_END)
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v = read_pdr(a, 1);
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else if (a >= ADDR_PAR_SV_START && a < ADDR_PAR_SV_END)
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v = read_par(a, 1);
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else if (a >= ADDR_PDR_K_START && a < ADDR_PDR_K_END)
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v = read_pdr(a, 0);
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else if (a >= ADDR_PAR_K_START && a < ADDR_PAR_K_END)
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v = read_par(a, 0);
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else if (a >= ADDR_PDR_U_START && a < ADDR_PDR_U_END)
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v = read_pdr(a, 3);
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else if (a >= ADDR_PAR_U_START && a < ADDR_PAR_U_END)
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v = read_par(a, 3);
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return v;
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}
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uint8_t mmu::read_byte(const uint16_t addr)
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{
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uint16_t v = read_word(addr);
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if (addr & 1)
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return v >> 8;
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return v;
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}
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void mmu::write_word(const uint16_t a, const uint16_t value)
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{
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// supervisor
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if (a >= ADDR_PDR_SV_START && a < ADDR_PDR_SV_END)
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write_pdr(a, 1, value, wm_word);
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else if (a >= ADDR_PAR_SV_START && a < ADDR_PAR_SV_END)
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write_par(a, 1, value, wm_word);
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// kernel
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else if (a >= ADDR_PDR_K_START && a < ADDR_PDR_K_END)
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write_pdr(a, 0, value, wm_word);
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else if (a >= ADDR_PAR_K_START && a < ADDR_PAR_K_END)
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write_par(a, 0, value, wm_word);
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// user
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else if (a >= ADDR_PDR_U_START && a < ADDR_PDR_U_END)
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write_pdr(a, 3, value, wm_word);
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else if (a >= ADDR_PAR_U_START && a < ADDR_PAR_U_END)
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write_par(a, 3, value, wm_word);
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}
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void mmu::write_byte(const uint16_t a, const uint8_t value)
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{
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// supervisor
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if (a >= ADDR_PDR_SV_START && a < ADDR_PDR_SV_END)
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write_pdr(a, 1, value, wm_byte);
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else if (a >= ADDR_PAR_SV_START && a < ADDR_PAR_SV_END)
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write_par(a, 1, value, wm_byte);
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// kernel
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else if (a >= ADDR_PDR_K_START && a < ADDR_PDR_K_END)
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write_pdr(a, 0, value, wm_byte);
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else if (a >= ADDR_PAR_K_START && a < ADDR_PAR_K_END)
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write_par(a, 0, value, wm_byte);
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// user
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else if (a >= ADDR_PDR_U_START && a < ADDR_PDR_U_END)
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write_pdr(a, 3, value, wm_byte);
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else if (a >= ADDR_PAR_U_START && a < ADDR_PAR_U_END)
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write_par(a, 3, value, wm_byte);
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}
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void mmu::trap_if_odd(const uint16_t a, const int run_mode, const d_i_space_t space, const bool is_write)
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{
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int page = a >> 13;
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if (is_write)
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set_page_trapped(run_mode, space == d_space, page);
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MMR0 &= ~(7 << 1);
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MMR0 |= page << 1;
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}
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memory_addresses_t mmu::calculate_physical_address(const int run_mode, const uint16_t a) const
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{
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const uint8_t apf = a >> 13; // active page field
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if (is_enabled() == false) {
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bool is_psw = a == ADDR_PSW;
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return { a, apf, a, is_psw, a, is_psw };
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}
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uint32_t physical_instruction = get_physical_memory_offset(run_mode, 0, apf);
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uint32_t physical_data = get_physical_memory_offset(run_mode, 1, apf);
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uint16_t p_offset = a & 8191; // page offset
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physical_instruction += p_offset;
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physical_data += p_offset;
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if ((getMMR3() & 16) == 0) { // offset is 18bit
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physical_instruction &= 0x3ffff;
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physical_data &= 0x3ffff;
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}
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if (get_use_data_space(run_mode) == false)
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physical_data = physical_instruction;
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uint32_t io_base = get_io_base();
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bool physical_instruction_is_psw = (physical_instruction - io_base + 0160000) == ADDR_PSW;
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bool physical_data_is_psw = (physical_data - io_base + 0160000) == ADDR_PSW;
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return { a, apf, physical_instruction, physical_instruction_is_psw, physical_data, physical_data_is_psw };
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}
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std::pair<trap_action_t, int> mmu::get_trap_action(const int run_mode, const bool d, const int apf, const bool is_write)
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{
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const int access_control = get_access_control(run_mode, d, apf);
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constexpr const trap_action_t map[8][2] {
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{ T_ABORT_4, T_ABORT_4 },
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{ T_TRAP_250, T_ABORT_4 },
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{ T_PROCEED, T_ABORT_4 },
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{ T_ABORT_4, T_ABORT_4 },
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{ T_TRAP_250, T_TRAP_250 },
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{ T_PROCEED, T_TRAP_250 },
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{ T_PROCEED, T_PROCEED },
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{ T_ABORT_4, T_ABORT_4 },
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};
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assert(map[1][false] == T_TRAP_250);
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assert(map[1][true ] == T_ABORT_4 );
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return { map[access_control][is_write], access_control };
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}
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void mmu::mmudebug(const uint16_t a)
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{
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#if !defined(TURBO)
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for(int rm=0; rm<4; rm++) {
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auto ma = calculate_physical_address(rm, a);
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TRACE("RM %d, a: %06o, apf: %d, PI: %08o (PSW: %d), PD: %08o (PSW: %d)", rm, ma.virtual_address, ma.apf, ma.physical_instruction, ma.physical_instruction_is_psw, ma.physical_data, ma.physical_data_is_psw);
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}
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#endif
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}
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void mmu::verify_page_access(const uint16_t virt_addr, const int run_mode, const bool d, const int apf, const bool is_write)
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{
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const auto [ trap_action, access_control ] = get_trap_action(run_mode, d, apf, is_write);
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if (trap_action == T_PROCEED) [[likely]]
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return;
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if (is_write)
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set_page_trapped(run_mode, d, apf);
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if (is_locked() == false) {
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uint16_t temp = getMMR0();
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temp &= ~((1l << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (3 << 5) | (7 << 1) | (1 << 4));
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if (is_write && access_control != 6)
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temp |= 1 << 13; // read-only
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//
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if (access_control == 0 || access_control == 4)
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temp |= 1l << 15; // not resident
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else
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temp |= 1 << 13; // read-only
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temp |= run_mode << 5; // TODO: kernel-mode or user-mode when a trap occurs in user-mode?
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temp |= apf << 1; // add current page
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temp |= d << 4;
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setMMR0_as_is(temp);
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TRACE("MMR0: %06o", temp);
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}
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if (trap_action == T_TRAP_250) {
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TRACE("Page access %d (for virtual address %06o): trap 0250", access_control, virt_addr);
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c->trap(0250); // trap
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throw 5;
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}
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else { // T_ABORT_4
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TRACE("Page access %d (for virtual address %06o): trap 004", access_control, virt_addr);
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c->trap(004); // abort
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throw 5;
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}
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}
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void mmu::verify_access_valid(const uint32_t m_offset, const int run_mode, const bool d, const int apf, const bool is_io, const bool is_write)
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{
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if (m_offset >= m->get_memory_size() && !is_io) [[unlikely]] {
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TRACE("TRAP(04) (throw 6) on address %08o", m_offset);
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if (is_locked() == false) {
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uint16_t temp = getMMR0();
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temp &= 017777;
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temp |= 1l << 15; // non-resident
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temp &= ~14; // add current page
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temp |= apf << 1;
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temp &= ~(3 << 5);
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temp |= run_mode << 5;
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setMMR0_as_is(temp);
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}
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if (is_write)
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set_page_trapped(run_mode, d, apf);
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c->trap(04);
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throw 6;
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}
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}
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void mmu::verify_page_length(const uint16_t virt_addr, const int run_mode, const bool d, const int apf, const bool is_write)
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{
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uint16_t pdr_len = get_pdr_len(run_mode, d, apf);
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if (pdr_len == 127)
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return;
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uint16_t pdr_cmp = (virt_addr >> 6) & 127;
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bool direction = get_pdr_direction(run_mode, d, apf);
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if (direction == false ? pdr_cmp > pdr_len : pdr_cmp < pdr_len) [[unlikely]] {
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TRACE("mmu::calculate_physical_address::p_offset %o versus %o direction %d", pdr_cmp, pdr_len, direction);
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TRACE("TRAP(0250) (throw 7) on address %06o", virt_addr);
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c->trap(0250); // invalid access
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if (is_locked() == false) {
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uint16_t temp = getMMR0();
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temp &= 017777;
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temp |= 1 << 14; // length
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temp &= ~14; // add current page
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temp |= apf << 1;
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temp &= ~(3 << 5);
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temp |= run_mode << 5;
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temp &= ~(1 << 4);
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temp |= d << 4;
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setMMR0_as_is(temp);
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}
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if (is_write)
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set_page_trapped(run_mode, d, apf);
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throw 7;
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}
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}
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uint32_t mmu::calculate_physical_address(const int run_mode, const uint16_t a, const bool is_write, const d_i_space_t space)
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{
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uint32_t m_offset = a;
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if (is_enabled() || (is_write && (getMMR0() & (1 << 8 /* maintenance check */)))) {
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bool d = space == d_space && get_use_data_space(run_mode);
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uint16_t p_offset = a & 8191; // page offset
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uint8_t apf = a >> 13; // active page field
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m_offset = get_physical_memory_offset(run_mode, d, apf);
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m_offset += p_offset;
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if ((getMMR3() & 16) == 0) // off is 18bit
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|
m_offset &= 0x3ffff;
|
|
|
|
verify_page_access(a, run_mode, d, apf, is_write);
|
|
|
|
// e.g. ram or i/o, not unmapped
|
|
uint32_t io_base = get_io_base();
|
|
bool is_io = m_offset >= io_base;
|
|
|
|
verify_access_valid(m_offset, run_mode, d, apf, is_io, is_write);
|
|
|
|
verify_page_length(a, run_mode, d, apf, is_write);
|
|
}
|
|
|
|
return m_offset;
|
|
}
|
|
|
|
JsonDocument mmu::add_par_pdr(const int run_mode, const bool is_d) const
|
|
{
|
|
JsonDocument j;
|
|
|
|
JsonDocument ja_par;
|
|
JsonArray ja_par_work = ja_par.to<JsonArray>();
|
|
for(int i=0; i<8; i++)
|
|
ja_par_work.add(pages[run_mode][is_d][i].par);
|
|
j["par"] = ja_par;
|
|
|
|
JsonDocument ja_pdr;
|
|
JsonArray ja_pdr_work = ja_pdr.to<JsonArray>();
|
|
for(int i=0; i<8; i++)
|
|
ja_pdr_work.add(pages[run_mode][is_d][i].pdr);
|
|
j["pdr"] = ja_pdr;
|
|
|
|
return j;
|
|
}
|
|
|
|
JsonDocument mmu::serialize() const
|
|
{
|
|
JsonDocument j;
|
|
|
|
for(int run_mode=0; run_mode<4; run_mode++) {
|
|
if (run_mode == 2)
|
|
continue;
|
|
|
|
for(int is_d=0; is_d<2; is_d++)
|
|
j[format("runmode_%d_d_%d", run_mode, is_d)] = add_par_pdr(run_mode, is_d);
|
|
}
|
|
|
|
j["MMR0"] = MMR0;
|
|
j["MMR1"] = MMR1;
|
|
j["MMR2"] = MMR2;
|
|
j["MMR3"] = MMR3;
|
|
j["CPUERR"] = CPUERR;
|
|
j["PIR"] = PIR;
|
|
j["CSR"] = CSR;
|
|
|
|
return j;
|
|
}
|
|
|
|
void mmu::set_par_pdr(const JsonVariantConst j_in, const int run_mode, const bool is_d)
|
|
{
|
|
JsonArrayConst j_par = j_in["par"];
|
|
int i_par = 0;
|
|
for(auto v: j_par)
|
|
pages[run_mode][is_d][i_par++].par = v;
|
|
|
|
JsonArrayConst j_pdr = j_in["pdr"];
|
|
int i_pdr = 0;
|
|
for(auto v: j_pdr)
|
|
pages[run_mode][is_d][i_pdr++].pdr = v;
|
|
}
|
|
|
|
mmu *mmu::deserialize(const JsonVariantConst j, memory *const mem, cpu *const c)
|
|
{
|
|
mmu *m = new mmu();
|
|
m->begin(mem, c);
|
|
|
|
for(int run_mode=0; run_mode<4; run_mode++) {
|
|
if (run_mode == 2)
|
|
continue;
|
|
|
|
for(int is_d=0; is_d<2; is_d++)
|
|
m->set_par_pdr(j[format("runmode_%d_d_%d", run_mode, is_d)].as<JsonVariantConst>(), run_mode, is_d);
|
|
}
|
|
|
|
m->MMR0 = j["MMR0"];
|
|
m->MMR1 = j["MMR1"];
|
|
m->MMR2 = j["MMR2"];
|
|
m->MMR3 = j["MMR3"];
|
|
m->CPUERR = j["CPUERR"];
|
|
m->PIR = j["PIR"];
|
|
m->CSR = j["CSR"];
|
|
|
|
return m;
|
|
}
|