475 lines
12 KiB
C++
475 lines
12 KiB
C++
// (C) 2018 by Folkert van Heusden
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// Released under Apache License v2.0
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#if defined(ESP32)
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#include <Arduino.h>
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#endif
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#include <assert.h>
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#include <stdio.h>
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#include "bus.h"
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#include "gen.h"
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#include "cpu.h"
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#include "memory.h"
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#include "tm-11.h"
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#include "tty.h"
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bus::bus() : c(nullptr), tm11(nullptr), rk05_(nullptr), rx02_(nullptr), tty_(nullptr)
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{
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#if defined(ESP32)
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// ESP32 goes in a crash-loop when allocating 128kB
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// see also https://github.com/espressif/esp-idf/issues/1934
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int n = 12;
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#else
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int n = 16;
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#endif
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m = new memory(n * 8192);
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for(int i=0; i<n; i++) {
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pages[i].par = (i & 7) * 8192 / 64;
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pages[i].pdr = (3 << 1) | (0 << 4) | (0 << 6) | ((8192 / (32 * 2)) << 8);
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}
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CPUERR = MMR2 = MMR3 = PIR = CSR = 0;
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}
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bus::~bus()
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{
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delete c;
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delete tm11;
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delete rk05_;
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delete rx02_;
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delete tty_;
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delete m;
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}
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void bus::clearmem()
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{
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m -> reset();
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}
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uint16_t bus::read(const uint16_t a, const bool word_mode, const bool use_prev)
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{
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uint16_t temp = 0;
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if (a >= 0160000) {
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D(fprintf(stderr, "read%c I/O %o\n", word_mode ? 'b' : ' ', a);)
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if (a == 0177750) { // MAINT
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D(fprintf(stderr, "read MAINT\n");)
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return 1; // POWER OK
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}
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if (a == 0177570) { // console switch & display register
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D(fprintf(stderr, "read console switch\n");)
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return 128; // educated guess
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}
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if (a == 0172540) { // KW11P programmable clock
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D(fprintf(stderr, "read programmable clock\n");)
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return 128;
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}
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if (a == 0177772) { // PIR
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D(fprintf(stderr, "read PIT\n");)
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return PIR;
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}
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if (a == 0177546) { // line frequency clock and status register
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D(fprintf(stderr, "read line freq clock\n");)
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return CSR;
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}
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if (a == 0177514) { // printer, CSR register, LP11
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D(fprintf(stderr, "read LP11 CSR\n");)
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return 0x80;
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}
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if (a == 0177564) { // console tty status register
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D(fprintf(stderr, "console tty status register\n");)
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return 0x80;
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}
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/// MMU ///
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if (a >= 0172300 && a < 0172320) {
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uint16_t t = pages[((a & 017) >> 1)].pdr;
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D(fprintf(stderr, "read PDR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0172340 && a < 0172360) {
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uint16_t t = pages[((a & 017) >> 1)].par;
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D(fprintf(stderr, "read PAR for %d: %o\n", (a & 017) >> 1, t);)
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return t;
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}
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if (a >= 0177600 && a < 0177620) {
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uint16_t t = pages[((a & 017) >> 1) + 8].pdr;
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D(fprintf(stderr, "read PDR for %d: %o\n", ((a & 017) >> 1) + 8, t);)
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return t;
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}
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if (a >= 0177640 && a < 0177660) {
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uint16_t t = pages[((a & 017) >> 1) + 8].par;
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D(fprintf(stderr, "read PAR for %d: %o\n", ((a & 017) >> 1) + 8, t);)
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return t;
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}
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if (a == 0177572) {
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uint16_t t = ((c -> getRunMode() ? 0b11 : 0b00) << 5) | // kernel == 00
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((c -> getRegister(7) >> 13) << 1) | // page nr
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0 // MMU enabled
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;
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D(fprintf(stderr, "read MMU SR0 %o\n", t);)
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return t;
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}
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///////////
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if (word_mode) {
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if (a == 0177776) { // PSW
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D(fprintf(stderr, "readb PSW LSB\n");)
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return c -> getPSW() & 255;
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}
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if (a == 0177777) {
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D(fprintf(stderr, "readb PSW MSB\n");)
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return c -> getPSW() >> 8;
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}
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if (a == 0177774) { // stack limit register
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D(fprintf(stderr, "readb stack limit register\n");)
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return c -> getStackLimitRegister() & 0xff;
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}
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if (a == 0177775) { // stack limit register
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D(fprintf(stderr, "readb stack limit register\n");)
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return c -> getStackLimitRegister() >> 8;
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}
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if (a >= 0177700 && a <= 0177705) { // kernel R0-R5
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D(fprintf(stderr, "readb kernel R%d\n", a - 0177700);)
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return c -> getRegister(false, a - 0177700) & 0xff;
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}
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if (a >= 0177710 && a <= 0177715) { // user R0-R5
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D(fprintf(stderr, "readb user R%d\n", a - 0177710);)
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return c -> getRegister(true, a - 0177710) & 0xff;
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}
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if (a == 0177706) { // kernel SP
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D(fprintf(stderr, "readb kernel sp\n");)
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return c -> getStackPointer(0) & 0xff;
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}
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if (a == 0177707) { // PC
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D(fprintf(stderr, "readb pc\n");)
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return c -> getPC() & 0xff;
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}
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if (a == 0177716) { // supervisor SP
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D(fprintf(stderr, "readb supervisor sp\n");)
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return c -> getStackPointer(1) & 0xff;
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}
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if (a == 0177717) { // user SP
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D(fprintf(stderr, "readb user sp\n");)
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return c -> getStackPointer(3) & 0xff;
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}
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if (a == 0177766) { // cpu error register
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D(fprintf(stderr, "readb cpuerr\n");)
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return CPUERR & 0xff;
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}
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}
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else {
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if (a == 0177576) { // MMR2
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D(fprintf(stderr, "read MMR2\n");)
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return MMR2;
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}
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if (a == 0172516) { // MMR3
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D(fprintf(stderr, "read MMR3\n");)
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return MMR3;
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}
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if (a == 0177776) { // PSW
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D(fprintf(stderr, "read PSW\n");)
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return c -> getPSW();
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}
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if (a == 0177774) { // stack limit register
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return c -> getStackLimitRegister();
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}
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if (a >= 0177700 && a <= 0177705) { // kernel R0-R5
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D(fprintf(stderr, "read kernel R%d\n", a - 0177700);)
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return c -> getRegister(false, a - 0177700);
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}
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if (a >= 0177710 && a <= 0177715) { // user R0-R5
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D(fprintf(stderr, "read user R%d\n", a - 0177710);)
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return c -> getRegister(true, a - 0177710);
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}
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if (a == 0177706) { // kernel SP
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D(fprintf(stderr, "read kernel sp\n");)
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return c -> getStackPointer(0);
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}
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if (a == 0177707) { // PC
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D(fprintf(stderr, "read pc\n");)
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return c -> getPC();
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}
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if (a == 0177716) { // supervisor SP
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D(fprintf(stderr, "read supervisor sp\n");)
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return c -> getStackPointer(1);
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}
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if (a == 0177717) { // user SP
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D(fprintf(stderr, "read user sp\n");)
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return c -> getStackPointer(3);
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}
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if (a == 0177766) { // cpu error register
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D(fprintf(stderr, "read CPUERR\n");)
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return CPUERR;
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}
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}
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if (tm11 && a >= TM_11_BASE && a < TM_11_END)
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return word_mode ? tm11 -> readByte(a) : tm11 -> readWord(a);
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if (rk05_ && a >= RK05_BASE && a < RK05_END)
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return word_mode ? rk05_ -> readByte(a) : rk05_ -> readWord(a);
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if (tty_ && a >= PDP11TTY_BASE && a < PDP11TTY_END)
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return word_mode ? tty_ -> readByte(a) : tty_ -> readWord(a);
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if (a & 1)
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D(fprintf(stderr, "bus::readWord: odd address UNHANDLED %o\n", a);)
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D(fprintf(stderr, "UNHANDLED read %o(%c)\n", a, word_mode ? 'B' : ' ');)
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if (a == 0177760)
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return 0167777; // TODO; get this from memory.cpp min(memsize, 64kB - 4kB)
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// c -> busError();
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return -1;
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}
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const uint8_t apf = a >> 13; // active page field
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bool is_user = use_prev ? (c -> getBitPSW(12) && c -> getBitPSW(13)) : (c -> getBitPSW(14) && c -> getBitPSW(15));
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uint32_t m_offset = pages[apf + is_user * 8].par * 64;
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if ((a & 1) && word_mode == 0)
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D(fprintf(stderr, "odd addressing\n");)
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if (!word_mode)
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temp = m -> readWord(m_offset + (a & 8191));
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else
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temp = m -> readByte(m_offset + (a & 8191));
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return temp;
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}
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uint16_t bus::write(const uint16_t a, const bool word_mode, uint16_t value, const bool use_prev)
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{
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//D(fprintf(stderr, "write bus %o(%d): %o\n", a, word_mode, value);)
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if (a >= 0160000) {
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D(fprintf(stderr, "write%c %o to I/O %o\n", word_mode ? 'b' : ' ', value, a);)
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if (word_mode) {
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if (a == 0177776 || a == 0177777) { // PSW
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D(fprintf(stderr, "writeb PSW %s\n", a & 1 ? "MSB" : "LSB");)
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uint16_t vtemp = c -> getPSW();
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if (a & 1)
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vtemp = (vtemp & 0x00ff) | (value << 8);
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else
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vtemp = (vtemp & 0xff00) | value;
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c -> setPSW(vtemp);
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return value;
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}
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if (a == 0177774 || a == 0177775) { // stack limit register
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D(fprintf(stderr, "writeb Set stack limit register to %o\n", value);)
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uint16_t v = c -> getStackLimitRegister();
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if (a & 1)
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v = (v & 0xff00) | value;
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else
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v = (v & 0x00ff) | (value << 8);
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c -> setStackLimitRegister(v);
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return v;
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}
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}
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else {
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if (a == 0177776) { // PSW
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D(fprintf(stderr, "write PSW %o\n", value);)
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c -> setPSW(value);
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return value;
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}
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if (a == 0177774) { // stack limit register
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D(fprintf(stderr, "write Set stack limit register to %o\n", value);)
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c -> setStackLimitRegister(value);
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return value;
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}
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if (a >= 0177700 && a <= 0177705) { // kernel R0-R5
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D(fprintf(stderr, "write kernel R%d to %o\n", a - 01777700, value);)
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c -> setRegister(false, a - 0177700, value);
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return value;
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}
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if (a >= 0177710 && a <= 0177715) { // user R0-R5
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D(fprintf(stderr, "write user R%d to %o\n", a - 01777710, value);)
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c -> setRegister(true, a - 0177710, value);
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return value;
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}
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if (a == 0177706) { // kernel SP
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D(fprintf(stderr, "write kernel SP to %o\n", value);)
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c -> setStackPointer(0, value);
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return value;
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}
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if (a == 0177707) { // PC
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D(fprintf(stderr, "write PC to %o\n", value);)
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c -> setPC(value);
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return value;
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}
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if (a == 0177716) { // supervisor SP
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D(fprintf(stderr, "write supervisor sp to %o\n", value);)
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c -> setStackPointer(1, value);
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return value;
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}
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if (a == 0177717) { // user SP
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D(fprintf(stderr, "write user sp to %o\n", value);)
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c -> setStackPointer(3, value);
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return value;
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}
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if (a == 0177770) { // microprogram break register
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return value;
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}
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}
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if (a == 0177766) { // cpu error register
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D(fprintf(stderr, "write CPUERR %o\n", value);)
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CPUERR = 0;
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return CPUERR;
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}
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if (a == 0172516) { // MMR3
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D(fprintf(stderr, "write set MMR3 to %o\n", value);)
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MMR3 = value;
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return MMR3;
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}
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if (a == 0177772) { // PIR
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D(fprintf(stderr, "write set PIR to %o\n", value);)
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PIR = value; // FIXME
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return PIR;
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}
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if (a == 0177546) { // line frequency clock and status register
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D(fprintf(stderr, "write set LFC/SR to %o\n", value);)
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CSR = value;
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return CSR;
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}
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if (tm11 && a >= TM_11_BASE && a < TM_11_END) {
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word_mode ? tm11 -> writeByte(a, value) : tm11 -> writeWord(a, value);
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return value;
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}
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if (rk05_ && a >= RK05_BASE && a < RK05_END) {
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word_mode ? rk05_ -> writeByte(a, value) : rk05_ -> writeWord(a, value);
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return value;
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}
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if (tty_ && a >= PDP11TTY_BASE && a < PDP11TTY_END) {
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word_mode ? tty_ -> writeByte(a, value) : tty_ -> writeWord(a, value);
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return value;
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}
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/// MMU ///
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if (a >= 0172300 && a < 0172320) {
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D(fprintf(stderr, "write set PDR for %d to %o\n", (a & 017) >> 1, value);)
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pages[((a & 017) >> 1)].pdr = value;
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return value;
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}
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if (a >= 0172340 && a < 0172360) {
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D(fprintf(stderr, "write set PAR for %d to %o\n", (a & 017) >> 1, value);)
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pages[((a & 017) >> 1)].par = value;
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return value;
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}
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if (a >= 0117600 && a < 0117620) {
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D(fprintf(stderr, "write set PDR for %d to %o\n", ((a & 017) >> 1) + 8, value);)
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pages[((a & 017) >> 1) + 8].pdr = value;
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return value;
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}
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if (a >= 0117640 && a < 0177660) {
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D(fprintf(stderr, "write set PAR for %d to %o\n", ((a & 017) >> 1) + 8, value);)
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pages[((a & 017) >> 1) + 8].par = value;
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return value;
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}
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if (a == 0177746) { // cache control register
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// FIXME
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return value;
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}
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///////////
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if (a == 0177374) { // FIXME
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fprintf(stderr, "char: %c\n", value & 127);
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return 128;
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}
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if (a == 0177566) { // console tty buffer register
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D(fprintf(stderr, "bus::write TTY buffer %d / %c\n", value, value);)
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if (value) {
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#if defined(ESP32)
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Serial.print(char(value & 127));
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#else
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printf("%c", value & 127);
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#endif
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}
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return 128;
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}
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if (a & 1)
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D(fprintf(stderr, "bus::writeWord: odd address UNHANDLED\n");)
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D(fprintf(stderr, "UNHANDLED write %o(%c): %o\n", a, word_mode ? 'B' : ' ', value);)
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c -> busError();
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return value;
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}
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const uint8_t apf = a >> 13; // active page field
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bool is_user = use_prev ? (c -> getBitPSW(12) && c -> getBitPSW(13)) : (c -> getBitPSW(14) && c -> getBitPSW(15));
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uint32_t m_offset = pages[apf + is_user * 8].par * 64;
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pages[apf].pdr |= 1 << 6; // page has been written to
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if ((a & 1) && word_mode == 0)
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D(fprintf(stderr, "odd addressing\n");)
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if (word_mode)
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m -> writeByte(m_offset + (a & 8191), value);
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else
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m -> writeWord(m_offset + (a & 8191), value);
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return value;
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}
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uint16_t bus::readWord(const uint16_t a)
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{
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return read(a, false);
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}
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uint16_t bus::writeWord(const uint16_t a, const uint16_t value)
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{
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write(a, false, value);
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return value;
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}
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