some optimizations for >5% increaase in register ops

machine.py

@@ -573,8 +573,13 @@ class PDP11:
 
             # SUBTLETY: Trap handlers expect the PC to be 2 beyond the
             #    instruction causing the trap. Hence "+2 then execute"
-            thisPC = self.r[self.PC]
-            self.r[self.PC] = (thisPC + 2) & 0o177777  # "could" wrap
+            # NOTE: Using literal "7" instead of self.PC makes
+            #       MOV R0,R1 (any register op) ~~ 4% faster.
+            #       The "except IndexError" hack for PC wraparound
+            #       (vs masking the addition) gains another 1.7% on top.
+
+            thisPC = self.r[7]
+            self.r[7] = thisPC + 2
 
             mmu.MMR1_staged = 0     # see discussion in go_trap
             mmu.MMR2 = thisPC       # per handbook
@@ -583,6 +588,11 @@ class PDP11:
             try:
                 inst = mmu.wordRW(thisPC)
                 op4_dispatch_table[inst >> 12](self, inst)
+            except IndexError:      # PC wrapped to 0o200000, or bug
+                if thisPC == 0o200000:
+                    self.r[7] = 0
+                    continue
+                raise               # else a genuine bug
             except PDPTrap as trap:
                 abort_trap = trap
                 self.straps |= self.STRAPBITS.HIGHEST_ABORTTRAP