improved WITH syntax for instruction sequences
This commit is contained in:
Neil Webber
parent
531e5607a5
commit
475f2e4591
2 changed files with 178 additions and 144 deletions
130
pdpasmhelper.py
130
pdpasmhelper.py
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@ -28,6 +28,9 @@
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# are focused around helping to create hand-constructed test code.
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#
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import contextlib
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class PDP11InstructionAssembler:
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B6MODES = {}
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_rnames = [(f"R{_i}", _i) for _i in range(8)] + [("SP", 6), ("PC", 7)]
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@ -40,19 +43,11 @@ class PDP11InstructionAssembler:
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B6MODES[f"@-({_rn})"] = 0o50 | _i # autodecr deferred
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del _i, _rn, _rnames
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def __init__(self):
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self.activeblock = None
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@classmethod
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def newsequence(cls):
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return _Sequence()
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def startblock(self):
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self.activeblock = []
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def addtoblock(self, insts):
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if self.activeblock is not None:
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self.activeblock += insts
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return insts
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def endblock(self):
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insts, self.activeblock = self.activeblock, None
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def append_seq(self, insts):
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return insts
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def immediate_value(self, s):
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@ -125,7 +120,7 @@ class PDP11InstructionAssembler:
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return [self.B6MODES[operand]]
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except KeyError:
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pass
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# last chance: X(Rn) and @X(rn)
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# see if X(Rn) or @X(Rn)...
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@ -149,72 +144,97 @@ class PDP11InstructionAssembler:
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b6 = self.B6MODES['(' + s[1]]
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except KeyError:
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raise valerr() from None
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seq = [mode | (b6 & 0o07), idxval]
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try:
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self.append_seq(seq)
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except AttributeError:
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pass
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return seq
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return [mode | (b6 & 0o07), idxval]
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# no-op here, but overridden in _Sequence to track generated instructions
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def _seqwords(self, seq):
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return seq
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def _2op(self, operation, src, dst):
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src6, *src_i = self.operand_parser(src)
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dst6, *dst_i = self.operand_parser(dst)
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return [ operation | src6 << 6 | dst6, *src_i, *dst_i ]
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return self._seqwords([operation | src6 << 6 | dst6, *src_i, *dst_i])
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def _1op(self, operation, dst):
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dst6, *dst_i = self.operand_parser(dst)
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return [ operation | dst6, *dst_i ]
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return self._seqwords([operation | dst6, *dst_i])
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def mov(self, src, dst):
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return self.addtoblock(self._2op(0o010000, src, dst))
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return self._2op(0o010000, src, dst)
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def cmp(self, src, dst):
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return self._2op(0o020000, src, dst)
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def add(self, src, dst):
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return self._2op(0o060000, src, dst)
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def sub(self, src, dst):
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return self._2op(0o160000, src, dst)
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def clr(self, dst):
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return self.addtoblock(self._1op(0o005000, dst))
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return self._1op(0o005000, dst)
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def inc(self, dst):
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return self.addtoblock(self._1op(0o005200, dst))
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return self._1op(0o005200, dst)
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def halt(self):
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return self.addtoblock([0])
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return self.literal(0)
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xxx = """
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0o012706, 0o20000, # put system stack at 8k and works down
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def mtpi(self, dst):
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return self._1op(0o006600, dst)
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0o012737, 0o22222, 0o20000,
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0o012737, 0o33333, 0o20002,
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0o012737, 0o44444, 0o40000,
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def mfpi(self, src):
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return self._1op(0o006500, src)
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# point both kernel seg 0 PARs to physical zero
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0o005037, cn.KISA0, # CLR $KISA0
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0o005037, cn.KDSA0, # CLR $KDSA0
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def mtpd(self, dst):
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return self._1op(0o106600, dst)
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# kernel seg 7 D space PAR to I/O page (at 22-bit location)
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0o012737, 0o017760000 >> 6, cn.KDSA0 + (7 * 2),
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def mfpd(self, src):
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return self._1op(0o106500, src)
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# user I seg 0 to 0o20000, user D seg 0 to 0o40000
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0o012737, 0o20000 >> 6, cn.UISA0,
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0o012737, 0o40000 >> 6, cn.UDSA0,
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def trap(self, tnum):
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return self.literal(0o104400 | tnum)
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# set the PDRs for segment zero
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0o012703, 0o077406, # MOV #77406,R3
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# 77406 = PDR<2:0> = ACF = 0o110 = read/write
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# PLF<14:8> =0o0774 = full length (128*64 bytes = 8K)
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0o010337, cn.KISD0, # MOV R3,KISD0 ...
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0o010337, cn.KDSD0,
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0o010337, cn.UISD0,
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0o010337, cn.UDSD0,
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# PDR for segment 7
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0o010337, cn.KDSD0 + (7 * 2),
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# generally used for instructions not implemented by an explicit method
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# Allows for one (or none) operand in the low 6 bits
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def literal(self, inst, oprnd=None, /):
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if oprnd is not None:
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return self._1op(inst, oprnd)
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else:
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return self._seqwords(inst)
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# set previous mode to USER, keeping current mode KERNEL, pri 7
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0o012737, (p.KERNEL << 14) | (p.USER << 12) | (7 << 5),
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self.ioaddr(p, p.PS_OFFS),
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# this is used for WITH ... it is mostly for the notational convenience
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# of being able to do thing like
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# with ASM.sequence() as u:
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# u.mov('r2','r6')
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# u.trap(0)
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# user_mode_instructions = u.sequence()
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# turn on 22-bit mode, unibus mapping, and I/D sep for k & u
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0o012737, 0o000065, self.ioaddr(p, p.mmu.MMR3_OFFS),
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class _Sequence(PDP11InstructionAssembler, contextlib.AbstractContextManager):
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def __init__(self):
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super().__init__()
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self._seq = []
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# turn on relocation mode ... yeehah! (MMR0 known zero here)
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0o005237, self.ioaddr(p, p.mmu.MMR0_OFFS), # INC MMR0
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)
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def __enter__(self):
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return self
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"""
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def __exit__(self, *args, **kwargs):
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return None
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def _seqwords(self, seq):
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"""seq can be an iterable, or a naked (integer) instruction."""
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if self._seq is not None:
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try:
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self._seq += seq
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except TypeError:
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self._seq += [seq]
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return seq
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def sequence(self):
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return self._seq
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192
pdptests.py
192
pdptests.py
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@ -29,6 +29,7 @@ import random
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from pdpasmhelper import PDP11InstructionAssembler as ASM
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class TestMethods(unittest.TestCase):
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PDPLOGLEVEL = 'INFO'
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@ -85,6 +86,7 @@ class TestMethods(unittest.TestCase):
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ns.UDSA0 = ns.UISA0 + 0o20
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ns.MMR0 = cls.ioaddr(p, p.mmu.MMR0_OFFS)
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ns.MMR3 = cls.ioaddr(p, p.mmu.MMR3_OFFS)
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return ns
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@ -96,13 +98,17 @@ class TestMethods(unittest.TestCase):
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# User Data space seg 0 points to physical 0o40000
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# and turns on the MMU
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#
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# premmu is an optional list of instructions to execute
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# before turning on the MMU
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#
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# postmmu is an optional list of instructions to execute
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# after turning on the MMU
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#
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def simplemapped_pdp(self, p=None, addons=[]):
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def simplemapped_pdp(self, p=None, *, premmu=[], postmmu=[]):
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if p is None:
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p = self.make_pdp()
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asm = ASM()
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cn = self.usefulconstants()
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# this is a table of instructions that ...
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@ -120,126 +126,132 @@ class TestMethods(unittest.TestCase):
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# These instructions will be placed at 2K in memory
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#
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asm.startblock()
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asm.mov(0o20000, 'sp') # start system stack at 8k
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with ASM.newsequence() as a:
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a.mov(0o20000, 'sp') # start system stack at 8k
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# write the constants as described above
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asm.mov(0o22222, asm.ptr(0o20000))
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asm.mov(0o33333, asm.ptr(0o20002))
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asm.mov(0o44444, asm.ptr(0o40000))
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# write the constants as described above
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a.mov(0o22222, a.ptr(0o20000))
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a.mov(0o33333, a.ptr(0o20002))
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a.mov(0o44444, a.ptr(0o40000))
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# point both kernel seg 0 PARs to physical zero
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asm.clr(asm.ptr(cn.KISA0))
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asm.clr(asm.ptr(cn.KDSA0))
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# point both kernel seg 0 PARs to physical zero
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a.clr(a.ptr(cn.KISA0))
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a.clr(a.ptr(cn.KDSA0))
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# kernel seg 7 D space PAR to I/O page (at 22-bit location)
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asm.mov(0o017760000 >> 6, asm.ptr(cn.KDSA0 + (7 * 2)))
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# kernel seg 7 D space PAR to I/O page (at 22-bit location)
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a.mov(0o017760000 >> 6, a.ptr(cn.KDSA0 + (7 * 2)))
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# user I seg 0 to 0o20000, user D seg 0 to 0o40000
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asm.mov(0o20000 >> 6, asm.ptr(cn.UISA0))
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asm.mov(0o40000 >> 6, asm.ptr(cn.UDSA0))
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# user I seg 0 to 0o20000, user D seg 0 to 0o40000
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a.mov(0o20000 >> 6, a.ptr(cn.UISA0))
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a.mov(0o40000 >> 6, a.ptr(cn.UDSA0))
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# set the PDRs for segment zero
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asm.mov(0o077406, 'r3')
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# 77406 = PDR<2:0> = ACF = 0o110 = read/write
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# PLF<14:8> =0o0774 = full length (128*64 bytes = 8K)
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# set the PDRs for segment zero
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a.mov(0o077406, 'r3')
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# 77406 = PDR<2:0> = ACF = 0o110 = read/write
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# PLF<14:8> =0o0774 = full length (128*64 bytes = 8K)
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asm.mov('r3', asm.ptr(cn.KISD0))
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asm.mov('r3', asm.ptr(cn.KDSD0))
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asm.mov('r3', asm.ptr(cn.UISD0))
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asm.mov('r3', asm.ptr(cn.UDSD0))
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a.mov('r3', a.ptr(cn.KISD0))
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a.mov('r3', a.ptr(cn.KDSD0))
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a.mov('r3', a.ptr(cn.UISD0))
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a.mov('r3', a.ptr(cn.UDSD0))
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# PDR for segment 7
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asm.mov('r3', asm.ptr(cn.KDSD0 + (7 * 2)))
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# PDR for segment 7
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a.mov('r3', a.ptr(cn.KDSD0 + (7 * 2)))
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# set previous mode to USER, keeping current mode KERNEL, pri 7
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asm.mov((p.KERNEL << 14) | (p.USER << 12) | (7 << 5),
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asm.ptr(self.ioaddr(p, p.PS_OFFS)))
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# set previous mode to USER, keeping current mode KERNEL, pri 7
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a.mov((p.KERNEL << 14) | (p.USER << 12) | (7 << 5),
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a.ptr(self.ioaddr(p, p.PS_OFFS)))
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# turn on 22-bit mode, unibus mapping, and I/D sep for k & u
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asm.mov(0o000065, asm.ptr(self.ioaddr(p, p.mmu.MMR3_OFFS)))
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# turn on 22-bit mode, unibus mapping, and I/D sep for k & u
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a.mov(0o000065, a.ptr(cn.MMR3))
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# turn on relocation mode ... yeehah! (MMR0 known zero here)
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asm.inc(asm.ptr(self.ioaddr(p, p.mmu.MMR0_OFFS)))
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# Instructions supplied by caller, to be execute before
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# enabling the MMU. They are "literals" since they have
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# already been assembled.
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for w in premmu:
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a.literal(w)
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# turn on relocation mode ...
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a.inc(a.ptr(cn.MMR0))
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asm.addtoblock(addons)
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asm.halt()
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setup_instructions = asm.endblock()
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# and the post-MMU instructions
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for w in postmmu:
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a.literal(w)
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a.halt()
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instloc = 0o4000 # 2K
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self.loadphysmem(p, setup_instructions, instloc)
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self.loadphysmem(p, a.sequence(), instloc)
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return p, instloc
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# these tests end up testing a other stuff too of course, including MMU
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def test_mfpi(self):
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# ((r0, ..., rN) results, (instructions)), ...
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tvecs = (
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# r1=2, mfpi (r1) -> r0; expect r0 = 33333
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((0o33333,), (0o012701, 0o02, 0o006511, 0o012600)),
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tvecs = []
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# r1=0, mfpi (r1) -> r0; expect r0 = 22222
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((0o22222,), (0o012701, 0o00, 0o006511, 0o012600)),
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)
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for result, r1tval in ((0o33333, 2), (0o22222, 0)):
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# r1=r1tval, mfpi (r1) -> r0; expect r0 = result
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with ASM.newsequence() as a:
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a.mov(r1tval, 'r1')
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a.mfpi('(r1)')
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a.mov('(sp)+', 'r0')
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tvecs.append((result, a.sequence()))
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for rslts, insts in tvecs:
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with self.subTest(rslts=rslts, insts=insts):
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p, pc = self.simplemapped_pdp(addons=insts)
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for result, insts in tvecs:
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with self.subTest(result=result, insts=insts):
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p, pc = self.simplemapped_pdp(postmmu=insts)
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p.run(pc=pc)
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for rN, v in enumerate(rslts):
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self.assertEqual(p.r[rN], v)
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self.assertEqual(p.r[0], result)
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def test_mfpxsp(self):
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cn = self.usefulconstants()
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insts = (
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# gotta turn mapping back off for these...
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0o005037, cn.MMR0, # CLR MMR0
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0o012737, 0o14000, 0o34, # mov $14000,*#34
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0o005037, 0o36, # clear *#36 .. perfectly fine PSW
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0o012700, 0o20000, # mov #20000,r0
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0o012720, 0o010206, # put into user 0: mov r2,r6
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0o012720, 0o104400, # put into user 2: trap 0
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# these two instructions are needed as literals in the test sequence
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with ASM.newsequence() as u:
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u.mov('r2', 'r6')
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u.trap(0)
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user_mode_instructions = u.sequence()
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0o012702, 0o123456, # put 123456 into R2
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0o012746, 0o140340, # push user-ish PSW onto kernel stack
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0o005046, # new user PC == 0
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0o005237, cn.MMR0, # back on with the mapping!
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with ASM.newsequence() as premmu:
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ts = premmu # just for brevity...
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ts.mov(0o14000, ts.ptr(0o34)) # set vector 034 to 14000
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ts.clr(ts.ptr(0o36)) # PSW for trap - zero work
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ts.mov(0o20000, 'r0') # mov #20000,r0
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0o000006, # RTT -- goes to user mode, addr 0
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)
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for uinst in user_mode_instructions:
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ts.mov(uinst, '(r0)+')
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ts.mov(0o123456, 'r2') # mov #123456,r2
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ts.mov(0o140340, '-(sp)') # push user-ish PSW to K stack
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ts.clr('-(sp)') # new user PC = 0
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p, pc = self.simplemapped_pdp(addons=insts)
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with ASM.newsequence() as postmmu:
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postmmu.literal(6) # RTT - goes to user mode, addr 0
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p, pc = self.simplemapped_pdp(premmu=premmu.sequence(),
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postmmu=postmmu.sequence())
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# put the trap handler at 14000 as expected
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traph = (
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0o106506, # mfpd sp
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0o012603, # pop stack into r3
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0
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)
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self.loadphysmem(p, traph, 0o14000)
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p.instlog = True
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with ASM.newsequence() as th:
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th.mfpd('sp')
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th.mov('(sp)+', 'r3')
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th.halt()
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self.loadphysmem(p, th.sequence(), 0o14000)
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p.run(pc=pc)
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self.assertEqual(p.r[2], p.r[3])
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def test_mtpi(self):
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# need an instance just for the constants, meh
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px = self.make_pdp()
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cn = self.usefulconstants()
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tvecs = (
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((0o1717,), (0o012746, 0o1717, 0o006637, 0o02,
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# turn MMU back off (!)
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0o005037, self.ioaddr(px, px.mmu.MMR0_OFFS),
|
||||
0o013700, 0o20002)),
|
||||
(0o1717, (0o012746, 0o1717, 0o006637, 0o02,
|
||||
# turn MMU back off (!)
|
||||
0o005037, cn.MMR0,
|
||||
0o013700, 0o20002)),
|
||||
)
|
||||
for rslts, insts in tvecs:
|
||||
with self.subTest(rslts=rslts, insts=insts):
|
||||
p, pc = self.simplemapped_pdp(addons=insts)
|
||||
for r0result, insts in tvecs:
|
||||
with self.subTest(r0result=r0result, insts=insts):
|
||||
p, pc = self.simplemapped_pdp(postmmu=insts)
|
||||
p.run(pc=pc)
|
||||
for rN, v in enumerate(rslts):
|
||||
self.assertEqual(p.r[rN], v)
|
||||
self.assertEqual(p.r[0], r0result)
|
||||
|
||||
def test_add_sub(self):
|
||||
p = self.make_pdp()
|
||||
|
|
@ -258,10 +270,12 @@ class TestMethods(unittest.TestCase):
|
|||
add_loc = testloc
|
||||
sub_loc = testloc + 4
|
||||
|
||||
p.physmem[add_loc >> 1] = 0o060001 # ADD R0,R1
|
||||
p.physmem[(add_loc >> 1) + 1] = 0
|
||||
p.physmem[sub_loc >> 1] = 0o160001 # SUB R0,R1
|
||||
p.physmem[(sub_loc >> 1) + 1] = 0
|
||||
for addsub, loc in (('add', add_loc), ('sub', sub_loc)):
|
||||
with ASM.newsequence() as a:
|
||||
getattr(a, addsub)('r0', 'r1')
|
||||
a.halt()
|
||||
for offs, inst in enumerate(a.sequence()):
|
||||
p.physmem[(loc >> 1) + offs] = inst
|
||||
|
||||
for r0, r1, added, a_nzvc, subbed, s_nzvc in testvecs:
|
||||
with self.subTest(r0=r0, r1=r1, op="add"):
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue