stacklimit red and yellow now both conform to SIMH behavior
This commit is contained in:
Neil Webber
parent
cc4303765d
commit
6c5dbb1e34
2 changed files with 94 additions and 29 deletions
38
machine.py
38
machine.py
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@ -628,8 +628,6 @@ class PDP11:
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if self.r[self.SP] < lim:
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if not (self.straps & self.STRAPBITS.YELLOW):
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self.logger.info(f"YELLOW ZONE, {list(map(oct, self.r))}")
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# definitely in at least a yellow condition
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self.straps |= self.STRAPBITS.YELLOW
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# how about red?
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if self.r[self.SP] + 32 < lim: # uh oh - below the yellow!
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@ -638,6 +636,8 @@ class PDP11:
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# and this trap is executed
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self.r[self.SP] = 4 # !! just enough room for...
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raise PDPTraps.AddressError(cpuerr=self.CPUERR_BITS.REDZONE)
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else:
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self.straps |= self.STRAPBITS.YELLOW
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def get_synchronous_trap(self, abort_trap):
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"""Return a synchronous trap, or possibly None.
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@ -724,18 +724,7 @@ class PDP11:
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self.psw = newps
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self.psw_prevmode = saved_curmode # i.e., override newps<13:12>
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prepushSP = self.r[6]
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try:
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self.stackpush(saved_psw)
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self.stackpush(self.r[self.PC])
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except PDPTrap as e:
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# again this is a pretty egregious error it means the kernel
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# stack is not mapped, or the stack pointer is odd, or similar
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# very bad mistakes by the kernel code. It is a fatal halt
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# NOTE: The stack register is restored
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self.logger.info(f"Trap pushing trap onto stack")
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self.r[6] = prepushSP
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self.halted = self.HALTED_STACK
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self._trappush(self.r[self.PC], saved_psw)
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# The error register records (accumulates) reasons (if given)
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self.error_register |= trap.cpuerr
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@ -805,6 +794,27 @@ class PDP11:
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self.r[6] = self.u16add(self.r[6], 2)
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return w
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# this is special because stack limit checking is disabled
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# during pushes of trap/interrupt frames. Any other types of
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# traps during a stack trap push are a fatal CPU halt and represent
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# a serious kernel programming error (invalid kernel stack)
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def _trappush(self, pc, psw):
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try:
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# NOTE: The stack pointer is only modified if
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# both of these succeed with no mmu/addressing traps
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self.mmu.wordRW_KD(self.u16add(self.r[self.SP], -2), psw)
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self.mmu.wordRW_KD(self.u16add(self.r[self.SP], -4), pc)
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except PDPTrap as e:
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# again this is a pretty egregious error it means the kernel
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# stack is not mapped, or the stack pointer is odd, or similar
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# very bad mistakes by the kernel code. It is a fatal halt
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self.logger.info(f"Trap ({e}) pushing trap {trap} onto stack")
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self.logger.info(f"Machine state: {self.machinestate()}")
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self.logger.info("HALTING")
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self.halted = self.HALTED_STACK
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else:
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self.r[self.SP] = self.u16add(self.r[self.SP], -4)
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class PDP1170(PDP11):
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85
pdptests.py
85
pdptests.py
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@ -1309,13 +1309,7 @@ class TestMethods(unittest.TestCase):
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p.run(pc=aa)
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self.assertEqual(p.r[0], 3) # confirm made it all the way through
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def test_stacklim1(self):
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# Set the stack at the top of the yellow zone and then use it.
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# This test should cause loopcount (3) YELLOW synchronous traps.
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# Behavior and expected results verified by running identical
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# machine code in SIMH
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p = self.make_pdp()
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def _stacklimcode(self, go_red=False):
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# memory usage:
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# 0o4000.. is the test code
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# 0o6000.. is the trap handler
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@ -1324,17 +1318,27 @@ class TestMethods(unittest.TestCase):
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# r5 is used to walk through the 0o7000+ storage, it is initialized
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# in the test code and used in the trap handler
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p = self.make_pdp()
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with ASM() as tr:
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# record...
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tr.mov('r2', '(r5)+') # ...separator/entry number
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tr.mov('sp', '(r5)+') # ...the sp
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tr.mov('(sp)', '(r5)+') # ...the trap-saved pc
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tr.mov(tr.ptr(0o177766), '(r5)+') # ...cpu error register
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tr.mov('r2', '(r5)+') # ...separator/entry number
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tr.mov('r2', '(r5)+') # ...separator/entry number
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tr.mov('sp', '(r5)+') # ...the sp
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tr.mov('(sp)', '(r5)+') # ...the trap-saved pc
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tr.mov(tr.ptr(0o177766), 'r1') # (will be used later)
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tr.mov('r1', '(r5)+') # ...cpu error register
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tr.mov('r2', '(r5)+') # ...separator/entry number
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# indicate successfully completed the above, bump entry number
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tr.inc('r2')
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# but if RED trap, stop here.
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tr.bit(p.CPUERR_BITS.REDZONE, 'r1')
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tr.beq('rtt')
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tr.halt()
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tr.label('rtt')
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tr.rtt()
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tra = 0o6000
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self.loadphysmem(p, tr.instructions(), tra)
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@ -1355,7 +1359,7 @@ class TestMethods(unittest.TestCase):
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a.mov(tra, a.ptr(0o4))
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a.mov(0o340, a.ptr(0o6))
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loopcount = 3
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loopcount = 3 if not go_red else 30 # will never get to 30
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a.mov(loopcount, 'r0')
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a.label('push')
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a.clr('-(sp)')
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@ -1364,10 +1368,22 @@ class TestMethods(unittest.TestCase):
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aa = 0o4000
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self.loadphysmem(p, a.instructions(), aa)
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p.r[p.PC] = aa
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return p
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p.run(pc=aa)
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def test_stacklim1(self):
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# Set the stack at the top of the yellow zone and then use it.
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# This test should cause loopcount (3) YELLOW synchronous traps.
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# Behavior and expected results verified by running identical
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# machine code in SIMH
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# obtained by running above in SIMH
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# r5 is used to walk through the 0o7000+ storage, it is initialized
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# in the test code and used in the trap handler
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p = self._stacklimcode()
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p.run()
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# obtained by running machine code in SIMH
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expected_7000 = [
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# MARKER SP PC CPUERR MARKER
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0o066000, 0o000372, 0o004052, 0o000010, 0o066000,
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@ -1380,6 +1396,45 @@ class TestMethods(unittest.TestCase):
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with self.subTest(i=i, val=val):
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self.assertEqual(val, p.physmem[recbase + i])
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def test_stacklim_red(self):
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p = self._stacklimcode(go_red=True)
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p.run()
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# Behavior/results verified by running machine code on SIMH;
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# however, SIMH halts the simulation on the red stack trap and
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# requires intervention to continue into the actual trap handler.
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# Doing that (i.e., "CONTINUE") leads to these same results.
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self.assertEqual(p.r[1], 0o14) # RED|YELLOW
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self.assertEqual(p.r[2], 0o66021) # known magic iteration marker
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self.assertEqual(p.r[6], 0) # stack should be at zero
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# obtained by running machine code in SIMH
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expected_7000 = [
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# MARKER SP PC CPUERR MARKER
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0o066000, 0o000372, 0o004052, 0o000010, 0o066000,
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0o066001, 0o000370, 0o004052, 0o000010, 0o066001,
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0o066002, 0o000366, 0o004052, 0o000010, 0o066002,
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0o066003, 0o000364, 0o004052, 0o000010, 0o066003,
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0o066004, 0o000362, 0o004052, 0o000010, 0o066004,
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0o066005, 0o000360, 0o004052, 0o000010, 0o066005,
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0o066006, 0o000356, 0o004052, 0o000010, 0o066006,
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0o066007, 0o000354, 0o004052, 0o000010, 0o066007,
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0o066010, 0o000352, 0o004052, 0o000010, 0o066010,
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0o066011, 0o000350, 0o004052, 0o000010, 0o066011,
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0o066012, 0o000346, 0o004052, 0o000010, 0o066012,
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0o066013, 0o000344, 0o004052, 0o000010, 0o066013,
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0o066014, 0o000342, 0o004052, 0o000010, 0o066014,
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0o066015, 0o000340, 0o004052, 0o000010, 0o066015,
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0o066016, 0o000336, 0o004052, 0o000010, 0o066016,
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0o066017, 0o000334, 0o004052, 0o000010, 0o066017,
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0o066020, 0o000000, 0o004052, 0o000014, 0o066020,
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0]
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recbase = 0o7000//2 # word address in phys mem
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for i, val in enumerate(expected_7000):
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with self.subTest(i=i, val=val):
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self.assertEqual(val, p.physmem[recbase + i])
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def test_ubmap(self):
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p = self.make_pdp()
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