From 75f25eccb013d2531a1528f8d9ea63db97499761 Mon Sep 17 00:00:00 2001
From: Neil Webber <neil@webber.com>
Date: Fri, 29 Sep 2023 21:36:28 -0500
Subject: [PATCH] simple register optimization in clr

---
 op00.py | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/op00.py b/op00.py
index 1a122db..3aae647 100644
--- a/op00.py
+++ b/op00.py
@@ -65,7 +65,12 @@ def op00_50_clr(cpu, inst, opsize=2):
     cpu.psw_n = cpu.psw_v = cpu.psw_c = 0
     cpu.psw_z = 1
 
-    cpu.operandx(inst & 0o77, 0, opsize=opsize)
+    dstb6 = (inst & 0o77)
+    # optimize the common register case
+    if opsize == 2 and dstb6 < 8:
+        cpu.r[dstb6] = 0
+    else:
+        cpu.operandx(dstb6, 0, opsize=opsize)
 
 
 def op00_51_com(cpu, inst, opsize=2):