minor cleanups
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parent
0c6256571a
commit
98510af5e7
1 changed files with 10 additions and 16 deletions
24
rp.py
24
rp.py
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@ -141,46 +141,40 @@ class RPRM:
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self.command_history.pop(-1)
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self.command_history.pop(-1)
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self.command_history.insert(0, (value, self.statestring()))
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self.command_history.insert(0, (value, self.statestring()))
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self.logger.debug(f"RP: writing CS1 to {oct(value)}; "
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f"state: {self.statestring()}")
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self._cs1 = value
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self._cs1 = value
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self.logger.debug(f"RP: CS1 set to {oct(self._cs1)}")
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self.logger.debug(f"RP: CS1 set to {oct(self._cs1)}")
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if self._cs1 & 0x4000:
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self.logger.debug(f"LOOK!!!! XXX")
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if self._cs1 & self.HPCS1_BITS.RDY:
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if self._cs1 & self.HPCS1_BITS.RDY:
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self.AS = 1 # this is very bogus but maybe works for now
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self.AS = 1 # this is very bogus but maybe works for now
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# TRE/ERROR always cleared on next op
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cmd = self._cs1 & self.HPCS1_BITS.FN # NOTE: not shifted
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if value & self.HPCS1_BITS.GO:
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gobit = self._cs1 & self.HPCS1_BITS.GO
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self._cs1 &= ~self.HPCS1_BITS.TRE
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if gobit:
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# clear the command, the go bit, and also TRE/ERROR (per book)
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self._cs1 &= ~(cmd | self.HPCS1_BITS.GO | self.HPCS1_BITS.TRE)
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match value & self.HPCS1_BITS.FN, value & self.HPCS1_BITS.GO:
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match cmd, gobit:
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case 0, go:
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case 0, _:
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self._cs1 &= ~go
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pass
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case 0o06 | 0o12 | 0o16 | 0o20 | 0o22 as fcode, go:
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case 0o06 | 0o12 | 0o16 | 0o20 | 0o22 as fcode, _:
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self.logger.debug(f"RP: operation {oct(fcode)} ignored.")
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self.logger.debug(f"RP: operation {oct(fcode)} ignored.")
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self.logger.debug(self.statestring())
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self.logger.debug(self.statestring())
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self._cs1 &= ~(go | fcode)
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self._cs1 |= self.HPCS1_BITS.RDY
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self._cs1 |= self.HPCS1_BITS.RDY
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if self._cs1 & self.HPCS1_BITS.IE:
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if self._cs1 & self.HPCS1_BITS.IE:
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self.ub.intmgr.simple_irq(5, 0o254)
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self.ub.intmgr.simple_irq(5, 0o254)
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case 0o30, 1: # SEARCH
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case 0o30, 1: # SEARCH
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self._cs1 &= ~0o31
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self._cs1 |= self.HPCS1_BITS.RDY
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self._cs1 |= self.HPCS1_BITS.RDY
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self.CC = self.DC
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self.CC = self.DC
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if self._cs1 & self.HPCS1_BITS.IE:
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if self._cs1 & self.HPCS1_BITS.IE:
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self.ub.intmgr.simple_irq(5, 0o254)
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self.ub.intmgr.simple_irq(5, 0o254)
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case 0o60, 1:
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case 0o60, 1:
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self._cs1 &= ~0o61
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self.writecmd()
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self.writecmd()
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if self._cs1 & self.HPCS1_BITS.IE:
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if self._cs1 & self.HPCS1_BITS.IE:
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self.ub.intmgr.simple_irq(5, 0o254)
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self.ub.intmgr.simple_irq(5, 0o254)
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case 0o70, 1:
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case 0o70, 1:
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self._cs1 &= ~0o71
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self.readcmd()
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self.readcmd()
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if self._cs1 & self.HPCS1_BITS.IE:
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if self._cs1 & self.HPCS1_BITS.IE:
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self.ub.intmgr.simple_irq(5, 0o254)
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self.ub.intmgr.simple_irq(5, 0o254)
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