clock tests and adc
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Neil Webber
parent
29af35d50d
commit
9b0c1b906f
1 changed files with 164 additions and 14 deletions
178
pdptests.py
178
pdptests.py
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@ -25,11 +25,13 @@ from types import SimpleNamespace
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import breakpoints as BKP
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from machine import PDP1170
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from unibus import BusCycle
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from kw11 import KW11
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from kl11 import KL11
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from branches import BRANCH_CODES
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from pdptraps import PDPTraps
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import unittest
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import random
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import time
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import os
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import io
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import hashlib
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@ -38,6 +40,13 @@ import boot
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from pdpasmhelper import InstructionBlock
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# subclass of KW11 to allow for selectable HZ rate
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class KW11HZ(KW11):
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def __init__(self, *args, hz, **kwargs):
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self.HZ = hz
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super().__init__(*args, **kwargs)
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class TestMethods(unittest.TestCase):
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PDPLOGLEVEL = 'INFO'
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@ -45,9 +54,11 @@ class TestMethods(unittest.TestCase):
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# used to create various instances, collects all the options
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# detail into this one place... mostly this is about loglevel
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@classmethod
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def make_pdp(cls, memwords=64*1024):
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def make_pdp(cls, memwords=64*1024, loglevel=None):
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if loglevel is None:
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loglevel = cls.PDPLOGLEVEL
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m128 = [0] * memwords
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return PDP1170(loglevel=cls.PDPLOGLEVEL, physmem=m128)
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return PDP1170(loglevel=loglevel, physmem=m128)
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@staticmethod
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def ioaddr(p, offs):
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@ -200,7 +211,7 @@ class TestMethods(unittest.TestCase):
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self.loadphysmem(p, a, instloc)
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return p, instloc
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def u64mapped_pdp(self, p=None, /):
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def u64mapped_pdp(self, p=None, /, *pdpargs, **pdpkwargs):
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# Make a PDP11 with:
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# * kernel space mapped to first 56K of memory (straight through)
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# * top of kernel space mapped to I/O page
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@ -209,7 +220,7 @@ class TestMethods(unittest.TestCase):
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# No I/D separation.
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#
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if p is None:
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p = self.make_pdp()
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p = self.make_pdp(*pdpargs, **pdpkwargs)
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cn = self.usefulconstants()
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@ -2414,6 +2425,110 @@ class TestMethods(unittest.TestCase):
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for i, t in enumerate(cbx.arglog):
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self.assertEqual(t, gold[i])
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def test_adc(self):
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p = self.make_pdp()
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a = InstructionBlock()
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a.clr('r1')
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a.mov(0o177777, 'r0')
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# NOTE WELL: INC DOES NOT SET C (!!!)
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a.add(1, 'r0')
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a.adc('r1')
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a.halt()
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self.loadphysmem(p, a, 0o10000)
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p.run(pc=0o10000)
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self.assertEqual(p.r[0], 0)
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self.assertEqual(p.r[1], 1)
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# not automatically tested
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def clocktests_basic(self):
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# test clock overhead
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# memory layout
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# 0o100 VECTOR for KW11 interrupt handler
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# 0o102 PSW for KW11 interrupt handler
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#
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# 0o10000 stack (grows down)
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# 0o10000 start address (set up clock, vectors, etc)
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# 0o20000 interrupt handler
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#
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# REGISTER USAGE
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# r0-r3 scratch
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# r3 count down (# of interrupts to take until HALT)
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# r4:r5 32-bit count up performance tracker (r5 high)
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mc = InstructionBlock()
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mc_addr = 0o10000
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ih = InstructionBlock()
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ih_addr = 0o20000
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mc.mov(mc_addr, 'sp')
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mc.mov(0o340, mc.ptr(0o177776)) # PSW .. pri 7
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mc.mov(ih_addr, mc.ptr(0o100))
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mc.mov(0o340, mc.ptr(0o102))
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mc.mov(10, 'r3')
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mc.clr('r4')
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mc.clr('r5')
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# enable interrupts and start the counter loop
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mc.mov(0o100, mc.ptr(0o177546))
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mc.clr(mc.ptr(0o177776))
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mc.label('loop')
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mc.inc('r4') # NOTE: INC does not set C (!!)
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mc.bne('loop')
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mc.inc('r5')
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mc.br('loop')
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ih.dec('r3')
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ih.beq('done')
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ih.rti()
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ih.label('done')
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ih.halt()
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# this test is a little questionable in that what it assumes
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# is that an increasing line clock frequency will correspond to
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# an increase in overhead, and the
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#
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# self.assertTrue(thisrun < prev)
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#
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# test depends on that (i.e., fewer increments get to happen if the
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# clock interrupt is going off more often). Obviously, random
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# performance interference issues in the test environment could
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# cause a spurious failure.
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#
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prev = 0x7fffffff
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for hz in [2, 5, 10, 25, 50, 100]:
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p = self.make_pdp()
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clk = KW11HZ(p.ub, hz=hz)
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self.loadphysmem(p, mc, mc_addr)
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self.loadphysmem(p, ih, ih_addr)
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p.run(pc=mc_addr)
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thisrun = (p.r[5] << 16) | p.r[4]
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with self.subTest(hz=hz, prev=prev, thisrun=thisrun):
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self.assertTrue(thisrun < prev)
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prev = thisrun
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# not automatically tested
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def clocktests_hz(self):
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for hz in [5, 10, 25, 50, 100]:
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p = self.make_pdp()
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clk = KW11HZ(p.ub, hz=hz)
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arbitrary_delay = 1
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time.sleep(arbitrary_delay)
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stamps = list(clk.tslog)
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# However many time stamps there are, the average delay over
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# those readings should be 1/hz seconds. It won't be that,
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# of course, but see if it is plausible.
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calculated_hz = (len(stamps) - 1) / (stamps[-1] - stamps[0])
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# it will (presumably!) always run slow, and this is the
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# empirically-determined reasonable slop factor
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minratio = 0.8
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with self.subTest(hz=hz, calculated_hz=calculated_hz):
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self.assertTrue(calculated_hz/hz > minratio)
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def test_breakpoints1(self):
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# test the steps=N breakpoint capability
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@ -2710,7 +2825,8 @@ class TestMethods(unittest.TestCase):
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# are all just dummied up right now
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# this is not a unit test, invoke it using timeit etc
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def speed_test_setup(self, instwords, /, *, loopcount=200, mmu=True):
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def speed_test_setup(self, instwords, /, *,
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loopcount=200, usemmu=True, hz=0):
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"""Set up a test run of the instwords (1 word or 2)
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Returns tuple: p, pc, per .. see speed_test_run()
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@ -2718,28 +2834,52 @@ class TestMethods(unittest.TestCase):
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If len == 2 (i.e., an instruction + operand), 24 instructions + SOB
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"""
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p, pc = self.u64mapped_pdp()
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# use loglevel WARNING to avoid a zillion start/halt logs
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p, pc = self.u64mapped_pdp(loglevel='WARNING')
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# the returned pdp is loaded with instructions for setting up
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# the mmu; only do them if that's what is wanted
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#
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# NOTE: the test code is run in USER mode Because Reasons
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# (was experimenting with virtual caches and this was helpful).
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# NOTE: the test code is run in USER mode.
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if usemmu:
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if hz:
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clk = KW11HZ(p.ub, hz=hz)
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p.associate_device(clk, 'KW')
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if mmu:
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p.run(pc=pc) # set up all those mappings
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usermode_base = 0o10000 # phys 0o210000 maps here in USER mode
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user_physloc = 0o210000
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if hz:
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ihloc = 0o4000
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# the interrupt handler itself
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ih = InstructionBlock()
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ih.rti()
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for a2, w in enumerate(ih):
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p.mmu.wordRW(ihloc + (2 * a2), w)
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# set up the vector
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p.mmu.wordRW(0o100, ihloc)
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p.mmu.wordRW(0o102, 0o340)
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# start the clock!
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p.mmu.wordRW(0o177546, 0o100)
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else:
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if hz:
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raise ValueError("Use of KW11 requires MMU")
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user_physloc = 0o20000
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usermode_base = user_physloc
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# kernel startup code at 0o5000 (NOTE: ih was at 0o4000)
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kloc = 0o5000
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# this is the tiny kernel code used to set up and start
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# each major iteration of the user mode timing code. The one-time
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# overhead of these few instructions is irrelevant in the timing test.
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k = InstructionBlock()
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k.mov(0o20000, 'sp') # establish proper kernel stack
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k.mov(0o140340, '-(sp)') # USER mode, no interrupts
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k.mov(0o140000, '-(sp)') # USER mode, spl 0
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k.mov(usermode_base, '-(sp)') # pc start for loop/USER code
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# these environmental "knowns" are available for the test inst
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k.mov(0o1000, 'r5') # usable writeable addr
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@ -2747,7 +2887,6 @@ class TestMethods(unittest.TestCase):
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k.clr('r1')
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k.rtt() # off to the races!
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kloc = 0o4000
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for a2, w in enumerate(k):
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p.mmu.wordRW(kloc + (2 * a2), w)
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@ -2826,9 +2965,11 @@ if __name__ == "__main__":
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parser = argparse.ArgumentParser()
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parser.add_argument('-p', '--performance', action="store_true")
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parser.add_argument('--clocktest', action="store_true")
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parser.add_argument('-i', '--instruction', default=movr1r0, type=asminst,
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help="Test instruction, in octal. E.g.: 010203")
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parser.add_argument('--nommu', action="store_true")
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parser.add_argument('--hz', type=int, default=0)
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parser.add_argument('tests', nargs="*")
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args = parser.parse_args()
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@ -2851,7 +2992,8 @@ if __name__ == "__main__":
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instwords = args.instruction
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loopcount = 20
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p, pc, per = t.speed_test_setup(
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instwords, loopcount=loopcount, mmu=mmu)
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instwords, loopcount=loopcount, usemmu=mmu, hz=args.hz)
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number = 1000000 // (loopcount * per)
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ta = timeit.repeat(stmt='t.speed_test_run(p, pc)',
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number=number, globals=globals(), repeat=50)
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@ -2859,4 +3001,12 @@ if __name__ == "__main__":
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ws = list(map(lambda w: f"{oct(w)[2:]:0>6s}", args.instruction))
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print(f"Instruction {ws} took {tnsec} nsecs")
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else:
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unittest.main()
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argv = None
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if args.clocktest:
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argv = [parser.prog]
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tests = [s for s in dir(TestMethods)
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if s.startswith('clocktests_')]
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argv = [parser.prog] + ['TestMethods.' + s for s in tests]
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if tests:
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print(f"Tests to run: {tests}")
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unittest.main(argv=argv)
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