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more debugging info for PLF format traps

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This commit is contained in:
Neil Webber 2023-09-05 22:58:58 -05:00
parent 797ccc3273
commit b8ca7b4c13
1 changed files with 3 additions and 1 deletions
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4
mmu.py
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@ -532,7 +532,9 @@ class MemoryMgmt:
def _raisetrap(self, trapflag, vaddr, xkey): def _raisetrap(self, trapflag, vaddr, xkey):
"""Raise an MMU trap. Commits regmods and updates reason in MMR0.""" """Raise an MMU trap. Commits regmods and updates reason in MMR0."""
if trapflag == self.MMR0_BITS.ABORT_PLENGTH: if trapflag == self.MMR0_BITS.ABORT_PLENGTH:
self.cpu.logger.debug(f"PLF trap @ {oct(vaddr)}, {xkey=}") self.cpu.logger.debug(
f"PLF trap @ {oct(vaddr)}, {xkey=} "
f"{self.MMR0=} {self.cpu.machinestate()}")
self._MMR1commit() self._MMR1commit()
self.MMR0 |= (trapflag | self.MMR0 |= (trapflag |
xkey.segno << 1 | # bits <3:1> xkey.segno << 1 | # bits <3:1>