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fix backwards A/W bits

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This commit is contained in:
Neil Webber 2023-09-19 17:29:45 -05:00
parent 2b3dd0e2ab
commit cad7658511
1 changed files with 2 additions and 2 deletions
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4
mmu.py
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@ -334,8 +334,8 @@ class MemoryMgmt:
# there are no further A/W bit updates to worry about (so they
# can be cached at that point).
W_update = 0o200 if cycle == _CYCLE.WRITE else 0o000
A_update = 0o100 if straps else 0o000
W_update = 0o100 if cycle == _CYCLE.WRITE else 0o000
A_update = 0o200 if straps else 0o000
AW_update = (W_update | A_update)