more cleanup

This commit is contained in:
Neil Webber 2023-09-15 12:09:04 -04:00
parent 5b55a5b206
commit cb9cafc3fb

View file

@ -681,15 +681,17 @@ class TestMethods(unittest.TestCase):
# #
# For UP: # For UP:
# using ED=0 (segments grow upwards), create a user DSPACE mapping # using ED=0 (segments grow upwards), create a user DSPACE mapping
# where segment zero has length 0, segment 1 has 16 words, # where segment zero has length ("PLF") 0, segment 1 has length 1,
# segment 2 has 32 ... etc and then check that valid addresses # etc... and then check that valid addresses map correctly and
# map correctly and invalid ones fault correctly. # invalid ones fault correctly. Note a subtle semantic of the PDP
# page length field: to be invalid (in an upward growing segment)
# the address has to be GREATER than the computed block number.
# Thus a length of "zero" still has 1 valid block of words.
# #
# For DOWN: # For DOWN:
# using ED=1 ("dirbit" = 0o10) segments grow downwards, with the # using ED=1 ("dirbit" = 0o10) segments grow downwards, with the
# same 0, 16, 32, .. progression. So segment 0 still has 0 # same 0, 1, 2 .. progression (of valid "blocks") but they
# valid words, segment 1 ENDS with 16 valid words, segment 2 # are at the end of the segments.
# ENDS with 32 valid words, etc.
# this programs the MMU as above, according to dirbit (0 = up) # this programs the MMU as above, according to dirbit (0 = up)
# NOTE: the physical memory is filled in elsewhere # NOTE: the physical memory is filled in elsewhere
@ -745,21 +747,23 @@ class TestMethods(unittest.TestCase):
for dirbit in (0o00, 0o10): for dirbit in (0o00, 0o10):
p = self.make_pdp() p = self.make_pdp()
# trap handler for MMU faults; puts 0o666 into r5 and halts
# trap handler for MMU faults; puts 0o666 into r5 aand halts
trap_h_location = 0o3000 trap_h_location = 0o3000
with ASM() as th: with ASM() as th:
th.mov(0o666, 'r5') th.mov(0o666, 'r5')
trap0_offs = th.label('Trap0')
th.halt() th.halt()
th.clr('(sp)') # just know the loop starts at zero
th.rtt()
self.loadphysmem(p, th.instructions(), trap_h_location) self.loadphysmem(p, th.instructions(), trap_h_location)
# poke the trap handler vector (250) # poke the trap handler vector (250)
self.loadphysmem(p, [trap_h_location, 0], 0o250) pcps = [trap_h_location, 0]
# the trap handler for "trap 0" is just a halt (which is a zero) self.loadphysmem(p, pcps, 0o250)
# it resides at 0o3100 # same for the "trap 0" handler but skip to trap0_offs
self.loadphysmem(p, [0], 0o3100) pcps[0] += (trap0_offs*2)
self.loadphysmem(p, [0o3100, 0], 0o34) self.loadphysmem(p, pcps, 0o34)
# set the physical memory that will be mapped to user D # set the physical memory that will be mapped to user D
# space to this pattern so the test can verify the mapping # space to this pattern so the test can verify the mapping
@ -778,36 +782,35 @@ class TestMethods(unittest.TestCase):
# mapping is correct) # mapping is correct)
user_phys_ISPACEaddr = 0o20000 user_phys_ISPACEaddr = 0o20000
with ASM() as u: with ASM() as u:
# this value never occurs in user DSPACE (because every
# word location has been written with an even value)
# so this is a sentinel for whether the read happened
user_noval = 1
u.mov(user_noval, 'r1')
u.clr('r5') # sentinel becomes 0o42 or 0o666
u.mov('(r0)+', 'r1') u.mov('(r0)+', 'r1')
u.mov(0o42, 'r5') u.mov(0o42, 'r5')
u.trap(0) u.trap(0)
u.halt() # never get here, this is illegal
self.loadphysmem(p, u.instructions(), user_phys_ISPACEaddr) self.loadphysmem(p, u.instructions(), user_phys_ISPACEaddr)
a = mmusetup(dirbit) a = mmusetup(dirbit)
a.bis(1, a.ptr(cn.MMR3)) # enable I/D sep just for USER a.bis(1, a.ptr(cn.MMR3)) # enable I/D sep just for USER
a.mov(1, a.ptr(cn.MMR0)) # turn on MMU a.mov(1, a.ptr(cn.MMR0)) # turn on MMU
a.halt() a.mov(0o20000, 'sp') # establish kernel stack
testcase_offs = a.label('TESTCASE') * 2
# this is the kernel code that will be run per-test case
a.mov(0o20000, 'sp') # reestablish stack each time
a.clr('r5') # sentinel becomes 0o42 or 0o666
# this value never occurs in user DSPACE (because every
# word location has been written with an even value)
# so this is a sentinel for whethe the read happened
user_noval = 1
a.mov(user_noval, 'r1')
a.mov(0o140340, '-(sp)') # push user-ish PSW to K stack a.mov(0o140340, '-(sp)') # push user-ish PSW to K stack
a.clr('-(sp)') # new user PC = 0 a.clr('-(sp)') # new user PC = 0
a.clr('r0') # user test expects r0 to start zero
a.halt()
rtt_offs = a.label('RTT') * 2
a.rtt() a.rtt()
addr = 0o4000 addr = 0o4000
self.loadphysmem(p, a.instructions(), addr) self.loadphysmem(p, a.instructions(), addr)
p.run(pc=addr) # note HALT prior to testcase_offs p.run(pc=addr) # note HALT prior to RTT
def good(dirbit, segno, o): def good(dirbit, segno, o):
if dirbit: if dirbit:
@ -818,9 +821,8 @@ class TestMethods(unittest.TestCase):
return o <= maxvalidoffset return o <= maxvalidoffset
for segno in range(8): for segno in range(8):
p.r[0] = segno * 8192
for o in range(4096): for o in range(4096):
p.run(pc=addr + testcase_offs) p.run() # picks up at rtt pc
physval = (checksum - physval = (checksum -
((segno * 8192) + (o * 2))) & 0o177777 ((segno * 8192) + (o * 2))) & 0o177777
if good(dirbit, segno, o*2): if good(dirbit, segno, o*2):