more stacklim tests, more SIMH conformity
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1 changed files with 74 additions and 14 deletions
88
pdptests.py
88
pdptests.py
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@ -1288,37 +1288,97 @@ class TestMethods(unittest.TestCase):
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p.run(pc=base_address)
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p.run(pc=base_address)
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self.assertEqual(p.r[0], 0)
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self.assertEqual(p.r[0], 0)
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def test_stacklim(self):
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def test_stacklim0(self):
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# verify that simply *having* an illegal SP doesn't trap
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p = self.make_pdp()
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with ASM() as a:
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a.clr('r0') # will be used to verify progress
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# none of these bad stack pointers should cause
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# a YELLOW trap as they are never used as stacks...
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a.clr('sp') # really it's already zero...
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a.inc('r0') # show made it to here
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a.mov(1, 'sp') # odd SP, very bad idea
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a.inc('r0') # show made it to here
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a.mov(0o100, 'sp') # still too low
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a.inc('r0') # show made it to here
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a.halt()
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aa = 0o4000
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self.loadphysmem(p, a.instructions(), aa)
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p.run(pc=aa)
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self.assertEqual(p.r[0], 3) # confirm made it all the way through
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def test_stacklim1(self):
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# Set the stack at the top of the yellow zone and then use it.
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# This test should cause loopcount (3) YELLOW synchronous traps.
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# Behavior and expected results verified by running identical
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# machine code in SIMH
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p = self.make_pdp()
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p = self.make_pdp()
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magic = 0o123456
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# memory usage:
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# build the trap handler for testing stacklim
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# 0o4000.. is the test code
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# 0o6000.. is the trap handler
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# 0o7000.. is the log of various values collected in the trap handler
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# r5 is used to walk through the 0o7000+ storage, it is initialized
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# in the test code and used in the trap handler
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with ASM() as tr:
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with ASM() as tr:
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tr.mov('(sp)', 'r5')
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# record...
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tr.mov(magic, 'r0')
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tr.mov('r2', '(r5)+') # ...separator/entry number
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tr.mov(tr.ptr(0o177766), 'r1')
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tr.mov('sp', '(r5)+') # ...the sp
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tr.halt()
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tr.mov('(sp)', '(r5)+') # ...the trap-saved pc
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tr.mov(tr.ptr(0o177766), '(r5)+') # ...cpu error register
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tr.mov('r2', '(r5)+') # ...separator/entry number
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# indicate successfully completed the above, bump entry number
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tr.inc('r2')
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tr.rtt()
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tra = 0o6000
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tra = 0o6000
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self.loadphysmem(p, tr.instructions(), tra)
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self.loadphysmem(p, tr.instructions(), tra)
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recordmagic = 0o66000
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with ASM() as a:
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with ASM() as a:
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a.mov(0o400, 'sp')
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a.mov(0o400, 'sp')
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a.mov(0o7000, 'r5')
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a.mov(recordmagic, 'r2')
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# dirty up the (to be pushed to) stack to verify writes happened
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a.mov(0o370, 'r0')
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a.mov('r0', '(r0)+')
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a.mov('r0', '(r0)+')
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a.mov('r0', '(r0)+')
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a.mov('r0', '(r0)+')
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# install the trap handler
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a.mov(tra, a.ptr(0o4))
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a.mov(tra, a.ptr(0o4))
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a.mov(0o340, a.ptr(0o6))
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a.mov(0o340, a.ptr(0o6))
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a.clr('r0')
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loopcount = 3
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a.mov(loopcount, 'r0')
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a.label('push')
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a.clr('-(sp)')
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a.clr('-(sp)')
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a.label('fault')
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a.sob('r0', 'push')
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a.halt()
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a.halt()
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aa = 0o4000
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aa = 0o4000
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self.loadphysmem(p, a.instructions(), aa)
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self.loadphysmem(p, a.instructions(), aa)
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p.run(pc=aa)
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p.run(pc=aa)
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self.assertEqual(p.r[0], magic)
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self.assertEqual(p.r[1], p.CPUERR_BITS.YELLOW)
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self.assertEqual(p.r[5], aa + a.getlabel('fault'))
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# this stack result was hand-verified in SIMH
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# obtained by running above in SIMH
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self.assertEqual(p.r[6], 0o372)
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expected_7000 = [
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# MARKER SP PC CPUERR MARKER
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0o066000, 0o000372, 0o004052, 0o000010, 0o066000,
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0o066001, 0o000370, 0o004052, 0o000010, 0o066001,
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0o066002, 0o000366, 0o004052, 0o000010, 0o066002,
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0]
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recbase = 0o7000//2 # word address in phys mem
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for i, val in enumerate(expected_7000):
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with self.subTest(i=i, val=val):
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self.assertEqual(val, p.physmem[recbase + i])
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def test_ubmap(self):
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def test_ubmap(self):
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p = self.make_pdp()
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p = self.make_pdp()
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