invis
This commit is contained in:
Neil Webber
parent
fd03a30e4c
commit
d07363b983
1 changed files with 40 additions and 25 deletions
65
mmu.py
65
mmu.py
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@ -258,9 +258,15 @@ class MemoryMgmt:
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if self._22bit:
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self.iopage_base |= (15 << 18) # ... and 4 more
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def v2p(self, vaddr, mode, space, reading):
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def v2p(self, vaddr, mode, space, reading, *, invis=False):
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"""Convert a 16-bit virtual address to physical.
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NOTE: Raises traps, updates A/W bits, & sets straps as needed.
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invis=True when being used for logging or other examinations that
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should not alter any machine state, including MMU state.
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NOTE: raises PDPTraps.MMU for untranslatable addresses
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NOTE: If not invis, updates A/W bits & sets straps as needed.
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* Raises traps, updates A/W bits, & sets straps as needed.
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NOTE: 'reading' MUST be True or False, not anything else.
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"""
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@ -332,15 +338,15 @@ class MemoryMgmt:
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# handler modifies the APR to disable the management trap then
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# of course future lookups will be eligible for the cache then.
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straps = self._v2p_accesschecks(pdr, vaddr, xkey)
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straps = self._v2p_accesschecks(pdr, vaddr, xkey, invis)
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# the actual translation...
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bn = (vaddr >> 6) & 0o177
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plf = (pdr >> 8) & 0o177
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if (pdr & 0o10) and bn < plf:
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self._raisetrap(self.MMR0_BITS.ABORT_PLENGTH, vaddr, xkey)
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self._raisetrap(self.MMR0_BITS.ABORT_PLENGTH, vaddr, xkey, invis)
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elif (pdr & 0o10) == 0 and bn > plf:
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self._raisetrap(self.MMR0_BITS.ABORT_PLENGTH, vaddr, xkey)
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self._raisetrap(self.MMR0_BITS.ABORT_PLENGTH, vaddr, xkey, invis)
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# "Attention" (not "Access") and "Written" bits updates.
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# The W bit is indeed a "memory was written" bit.
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@ -352,21 +358,20 @@ class MemoryMgmt:
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# there are no further A/W bit updates to worry about (so they
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# can be cached at that point).
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W_update = 0o000 if reading else 0o100
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A_update = 0o200 if straps else 0o000
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if not invis:
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self.cpu.straps |= straps
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W_update = 0o000 if reading else 0o100
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A_update = 0o200 if straps else 0o000
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AW_update = (W_update | A_update)
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AW_update = (W_update | A_update)
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if (pdr & AW_update) != AW_update:
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self._putapr(xkey, (par, pdr | AW_update))
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if (pdr & AW_update) != AW_update:
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self._putapr(xkey, (par, pdr | AW_update))
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dib = vaddr & 0o77
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pa = ((par + bn) << 6) | dib
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self.cpu.straps |= straps
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# only non-trapping can be cached
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if straps == 0:
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if straps == 0 and not invis:
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self._encache(tuplexkey, pdr, pa - vaddr)
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return pa
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@ -412,7 +417,7 @@ class MemoryMgmt:
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foldednth = (xkey.mode * 2) + self._foldspaces(xkey.mode, xkey.space)
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self.APR[foldednth][xkey.segno] = list(apr)
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def _v2p_accesschecks(self, pdr, vaddr, xkey):
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def _v2p_accesschecks(self, pdr, vaddr, xkey, invis):
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"""Raise traps or set post-instruction traps as appropriate.
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Returns straps flags (if any required).
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@ -454,14 +459,15 @@ class MemoryMgmt:
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f"{list(map(oct, self.cpu.r))}"
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f", {oct(self.cpu.psw)}"
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f", PDR={oct(pdr)} {reading=}")
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self._raisetrap(self.MMR0_BITS.ABORT_NR, vaddr, xkey)
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self._raisetrap(self.MMR0_BITS.ABORT_NR, vaddr, xkey, invis)
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# control mode 1 is an abort if writing, mgmt trap if read
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case 1 if reading:
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straps = self.cpu.STRAPBITS.MEMMGT
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case 1 | 2 if not reading:
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self._raisetrap(self.MMR0_BITS.ABORT_RDONLY, vaddr, xkey)
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self._raisetrap(
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self.MMR0_BITS.ABORT_RDONLY, vaddr, xkey, invis)
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# control mode 4 is mgmt trap on any access (read or write)
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case 4:
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@ -473,14 +479,15 @@ class MemoryMgmt:
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return straps
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def wordRW(self, vaddr, value=None, /, *, mode=None, space=ISPACE):
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def wordRW(self, vaddr, value=None, /, *,
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mode=None, space=ISPACE, _invis=False):
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"""Read/write a word at virtual address vaddr.
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If value is None, perform a read and return a 16-bit value
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If value is not None, perform a write; return None.
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"""
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pa = self.v2p(vaddr, mode, space, value is None)
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pa = self.v2p(vaddr, mode, space, value is None, invis=_invis)
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if pa >= self.iopage_base:
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return self.ub.mmio.wordRW(pa & self.cpu.IOPAGE_MASK, value)
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else:
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@ -544,17 +551,25 @@ class MemoryMgmt:
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self.cpu.physRW(pa & ~1, wv)
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return None
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# because faults will change MMR registers and CPUERR... this exists
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# so debugging/logging tools (e.g., machinestate()) can access
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# memory without disturbing MMU/cpu state if a fault is caused.
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def _invisread(self, a):
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"""For debugging; read invisibly w/out modifying any MMU/CPU state."""
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return self.wordRW(a, _invis=True)
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def wordRW_KD(self, a, v=None, /):
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"""Convenienence; version of wordRW for kernel/dspace."""
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return self.wordRW(a, v, mode=self.cpu.KERNEL, space=self.DSPACE)
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def _raisetrap(self, trapflag, vaddr, xkey):
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def _raisetrap(self, trapflag, vaddr, xkey, invis):
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"""Raise an MMU trap. Commits regmods and updates reason in MMR0."""
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self._MMR1commit()
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self.MMR0 |= (trapflag |
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xkey.segno << 1 | # bits <3:1>
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xkey.space << 4 | # bit 4
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xkey.mode << 5) # bits <6:5>
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if not invis:
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self._MMR1commit()
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self.MMR0 |= (trapflag |
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xkey.segno << 1 | # bits <3:1>
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xkey.space << 4 | # bit 4
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xkey.mode << 5) # bits <6:5>
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# XXX gotta figure out how to set this for Odd Addresses and
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# T bit conditions, but otherwise Bit 7 is not set. From handbook:
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