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PDR_A fix, but not sure right yet

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This commit is contained in:
Neil Webber 2023-09-19 11:59:07 -05:00
parent d78fb6e8ec
commit d23ac358f0
1 changed files with 13 additions and 11 deletions
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24
mmu.py
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@ -166,15 +166,10 @@ class MemoryMgmt:
@MMR0.setter @MMR0.setter
def MMR0(self, value): def MMR0(self, value):
self.cpu.logger.debug(f"MMR0 being set to {oct(value)}")
self._mmr0 = value self._mmr0 = value
self._mmu_relo_enabled = (value & self.MMR0_BITS.RELO_ENABLE) self._mmu_relo_enabled = (value & self.MMR0_BITS.RELO_ENABLE)
self._mmu_trap_enabled = (value & self.MMR0_BITS.TRAP_ENABLE) self._mmu_trap_enabled = (value & self.MMR0_BITS.TRAP_ENABLE)
self._mmr12_frozen = (value & self.MMR0_BITS.FREEZER_TRAPS) self._mmr12_frozen = (value & self.MMR0_BITS.FREEZER_TRAPS)
# XXX
if self._mmr12_frozen:
self.cpu.logger.debug(f"MMR12 FROZEN {self.MMR1=} {self.MMR2=}")
self.segcache = {} self.segcache = {}
self.__rebaseIO() self.__rebaseIO()
@ -329,13 +324,20 @@ class MemoryMgmt:
elif (pdr & 0o10) == 0 and bn > plf: elif (pdr & 0o10) == 0 and bn > plf:
self._raisetrap(self.MMR0_BITS.ABORT_PLENGTH, vaddr, xkey) self._raisetrap(self.MMR0_BITS.ABORT_PLENGTH, vaddr, xkey)
# "Access" and "Written" bits updates. Subtle note: if this entry # "Attention" (not "Access") and "Written" bits updates.
# gets cached, then by definition the corresponding AW updates # The W bit is indeed a "memory was written" bit.
# already happened (here). So the "found it in cache" logic up top # The A bit, however, is not "access" but rather only set when
# of this function needn't worry about AW bit updates. # there is a memory management trap (not abort) related to the access.
#
# Entries can only be cached if they did not cause a strap.
# By definition, at that point (because reads/writes are separated)
# there are no further A/W bit updates to worry about (so they
# can be cached at that point).
AW_update = 0o300 if cycle == _CYCLE.WRITE else 0o200 W_update = 0o200 if cycle == _CYCLE.WRITE else 0o000
# XXX ^^^^^ not sure if a write should be 0o300 or naked 0o100 A_update = 0o100 if straps else 0o000
AW_update = (W_update | A_update)
if (pdr & AW_update) != AW_update: if (pdr & AW_update) != AW_update:
self._putapr(xkey, (par, pdr | AW_update)) self._putapr(xkey, (par, pdr | AW_update))