more updown tests
This commit is contained in:
Neil Webber
parent
cb9cafc3fb
commit
e9b71fecd5
1 changed files with 181 additions and 113 deletions
294
pdptests.py
294
pdptests.py
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@ -62,15 +62,19 @@ class TestMethods(unittest.TestCase):
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# Kernel instruction space PDR registers
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ns.KISD0 = cls.ioaddr(p, p.mmu.APR_KERNEL_OFFS)
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ns.KISD7 = ns.KISD0 + 0o16
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# Kernel data space PDR registers
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ns.KDSD0 = ns.KISD0 + 0o20
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ns.KDSD7 = ns.KDSD0 + 0o16
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# Kernel instruction space PAR registers
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ns.KISA0 = ns.KDSD0 + 0o20
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ns.KISA7 = ns.KISA0 + 0o16
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# Kernel data space PAR registers
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ns.KDSA0 = ns.KISA0 + 0o20
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ns.KDSA7 = ns.KDSA0 + 0o16
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# User mode similar
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ns.UISD0 = cls.ioaddr(p, p.mmu.APR_USER_OFFS)
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@ -660,17 +664,24 @@ class TestMethods(unittest.TestCase):
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def test_mmu_updown(self):
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# test the page length field support in both up and down directions
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# XXX whether it was wise to code this test as a magnum opus
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# of assembler prowess is well open to debate. On the plus
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# side, it certainly exercises a bunch of features besides
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# just testing the MMU page length functionality.
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cn = self.usefulconstants()
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p = self.make_pdp()
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# Two tests - up and down.
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#
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# In both tests, KERNEL I space page 0 is mapped to physical 0
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# and I/D separation is NOT enabled for KERNEL.
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# and KERNEL I space page 7 is mapped to the I/O page.
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# I/D separation is NOT enabled for KERNEL.
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#
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#
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# USER I space is mapped to 0o20000.
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# All 64K of USER D space is mapped to 64K of physical memory
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# ranging from 0o200000 (not a typo) to 0o
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# from 0o200000 (not a typo) .. 0o400000 (not a typo), but with
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# from 0o200000 (not a typo) to 0o400000 (not a typo), but with
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# a bizarre segment length scheme according to UP or DOWN phase of
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# the test as below. I/D separation is (obviously) enabled for USER.
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# All 64K of that memory is filled with sequential words such
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@ -693,139 +704,185 @@ class TestMethods(unittest.TestCase):
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# same 0, 1, 2 .. progression (of valid "blocks") but they
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# are at the end of the segments.
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# this programs the MMU as above, according to dirbit (0 = up)
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# NOTE: the physical memory is filled in elsewhere
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def mmusetup(dirbit): # "dirbit" as in PDR direction bit
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with ASM() as a:
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a.mov(0o20000, 'sp') # start system stack at 8k
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# KERNEL I SPACE
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# PAR to physical 0
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# PDR 77406 = read/write, full length
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a.clr(a.ptr(cn.KISA0))
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a.mov(0o077406, a.ptr(cn.KISD0))
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# these instructions do initialization common to both up/down cases
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kernel_addr = 0o4000 # arbitrary start for all this
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with ASM() as a:
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a.mov(0o20000, 'sp') # start system stack at 8k
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# KERNEL I SPACE
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# PAR 0 to physical 0
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# PAR 7 to physical 760000 and 22bit not turned on
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#
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# PDR 77406 = read/write, full length
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a.clr(a.ptr(cn.KISA0))
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a.mov(0o760000 >> 6, a.ptr(cn.KISA7))
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a.mov(0o077406, a.ptr(cn.KISD0))
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a.mov(0o077406, a.ptr(cn.KISD7))
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# USER I SPACE
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a.mov(0o20000 >> 6, a.ptr(cn.UISA0))
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a.mov(0o077406, a.ptr(cn.UISD0))
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# USER I SPACE
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a.mov(0o20000 >> 6, a.ptr(cn.UISA0))
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a.mov(0o077406, a.ptr(cn.UISD0))
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# USER D SPACE ...
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a.mov(cn.UDSD0, 'r3') # will walk through D0 .. D7
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# NOTE: A0 .. A7 is 040(r3)
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a.clr('r0') # r0: segno*2 = (0, 2, 4, .., 14)
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a.mov(0o2000, 'r4') # phys addr base (0o200000>>6)
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# USER D SPACE going UP...
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a.mov(cn.UDSD0, 'r3') # will walk through D0 .. D7
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# NOTE: A0 .. A7 is 040(r3)
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a.clr('r0') # r0: segno*2 = (0, 2, 4, .., 14)
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a.mov(0o2000, 'r4') # phys addr base (0o200000>>6)
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a.label('PARloop')
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a.label('PARloop')
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a.mov('r4', '040(r3)') # set U PAR; don't bump r3 yet
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a.add(0o200, 'r4') # 0o200 = 8192>>6
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a.mov('r4', '040(r3)') # set U PAR; don't bump r3 yet
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a.add(0o200, 'r4') # 0o200 = 8192>>6
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# compute segno * 8 in r2 (r0 starts as segno*2)
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a.mov('r0', 'r2')
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a.ash(3, 'r2')
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a.mov('r0', 'r2') # r2 = segno*2
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a.ash(3, 'r2') # r2 = segno*16
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a.swab('r2') # really (segno*16)<<8
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a.add(0o06, 'r2') # ACF r/w segment
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a.mov('r2', '(r3)+') # set U PDR
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a.inc('r0') # bump r0 by two
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a.inc('r0')
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a.cmp('r0', 16) # and loop until done all 8 segments
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a.blt('PARloop')
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if dirbit:
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# pln = 0o177 - (segno * 16)
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a.mov(0o177, 'r1')
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a.sub('r2', 'r1')
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a.mov('r1', 'r2')
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a.swab('r2')
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a.add(0o10, 'r2') # the downward growing case
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else:
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# pln = segno * 16 ... already in r2
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# pln << 8
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a.swab('r2')
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a.add(0o06, 'r2')
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a.mov('r2', '(r3)+') # set U PDR
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a.inc('r0')
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a.inc('r0')
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a.cmp('r0', 16)
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a.blt('PARloop')
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return a
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for dirbit in (0o00, 0o10):
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p = self.make_pdp()
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# trap handler for MMU faults; puts 0o666 into r5 and halts
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trap_h_location = 0o3000
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with ASM() as th:
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th.mov(0o666, 'r5')
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trap0_offs = th.label('Trap0')
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th.halt()
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th.clr('(sp)') # just know the loop starts at zero
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th.rtt()
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self.loadphysmem(p, th.instructions(), trap_h_location)
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# poke the trap handler vector (250)
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pcps = [trap_h_location, 0]
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self.loadphysmem(p, pcps, 0o250)
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# same for the "trap 0" handler but skip to trap0_offs
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pcps[0] += (trap0_offs*2)
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self.loadphysmem(p, pcps, 0o34)
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# set the physical memory that will be mapped to user D
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# space to this pattern so the test can verify the mapping
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checksum = 0o123456 # arbitrary
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user_phys_DSPACEbase = 0o200000
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words = (checksum - (user_phys_DSPACEbase + o) & 0o177777
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for o in range(0, 65536, 2))
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self.loadphysmem(p, words, user_phys_DSPACEbase)
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# user mode program:
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# read the given address: mov (r0)+,r1
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# puts 0o42 into r5 (flag that everything worked)
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# trap 0 back to kernel
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# Test can then verify correct value in r5 (indicating
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# MMU aborted or not) and correct value in r1 (indicating
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# mapping is correct)
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user_phys_ISPACEaddr = 0o20000
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with ASM() as u:
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# this value never occurs in user DSPACE (because every
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# word location has been written with an even value)
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# so this is a sentinel for whether the read happened
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user_noval = 1
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u.mov(user_noval, 'r1')
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u.clr('r5') # sentinel becomes 0o42 or 0o666
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u.mov('(r0)+', 'r1')
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u.mov(0o42, 'r5')
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u.trap(0)
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u.halt() # never get here, this is illegal
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self.loadphysmem(p, u.instructions(), user_phys_ISPACEaddr)
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a = mmusetup(dirbit)
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a.bis(1, a.ptr(cn.MMR3)) # enable I/D sep just for USER
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a.mov(1, a.ptr(cn.MMR0)) # turn on MMU
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a.mov(0o20000, 'sp') # establish kernel stack
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a.mov(0o140340, '-(sp)') # push user-ish PSW to K stack
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a.clr('-(sp)') # new user PC = 0
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a.clr('r0') # user test expects r0 to start zero
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# this halt will be right before the first run of user mode test
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a.halt()
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rtt_offs = a.label('RTT') * 2
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# the subsequent p.run() picks up here and starts the user code!
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a.rtt()
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addr = 0o4000
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self.loadphysmem(p, a.instructions(), addr)
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# these instructions are the trap handlers for both
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# the MMU abort and the trap 0 "all good". The only difference
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# is that only the MMU abort puts 666 into r5.
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a.label('TrapMMU')
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a.mov(0o666, 'r5')
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a.label('Trap0')
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a.halt()
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p.run(pc=addr) # note HALT prior to RTT
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# when test code starts again with p.run(), restarts here...
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a.clr('(sp)') # just knows the user loop starts at zero
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a.rtt() # back for another iteration
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def good(dirbit, segno, o):
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if dirbit:
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minvalidoffset = 8192 - (64 + ((segno * 64) * 16))
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return o >= minvalidoffset
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else:
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maxvalidoffset = 63 + ((segno * 64) * 16)
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return o <= maxvalidoffset
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# these instructions will be used to switch over
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# to the DOWN phase of the test. Similar to the UP but
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# don't have to do the PARs (they stay the same) and the
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# pln calculations are different.
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a.label('DOWN')
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a.mov(cn.UDSD0, 'r3')
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a.clr('r0')
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a.label('PARloopDOWN')
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# compute segno * 8 in r2 (r0 starts as segno*2)
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a.mov('r0', 'r2')
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a.ash(3, 'r2')
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# pln = 0o177 - (segno * 16)
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a.mov(0o177, 'r1')
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a.sub('r2', 'r1')
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a.mov('r1', 'r2')
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a.swab('r2')
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a.add(0o16, 'r2') # the downward growing case
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a.mov('r2', '(r3)+') # set U PDR
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a.inc('r0')
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a.inc('r0')
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a.cmp('r0', 16)
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a.blt('PARloopDOWN')
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# this halt will be right before the first run of user mode test
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a.halt()
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a.clr('r0') # initial loop condition
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a.clr('(sp)') # just knows the user loop starts at zero
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a.rtt()
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# Now for something extra frosty... relocate just segment 4
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# (arbitrarily chosen) of the user memory to a different
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# physical page and run the test again to ensure it still works.
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# This will make use of KERNEL A1 and A2 segments to map the
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# relocation (note: I space because no sep I/D for kernel here)
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a.label('BONUS')
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# copy UDSA4 into KISA1 - mapping old segment into kernel space
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a.mov(a.ptr(cn.UDSA0 + 4*2), a.ptr(cn.KISA0 + 2)) # i.e., A1
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# the new location for this data will be physical 0o600000
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# (not a typo) which becomes 0o6000 in the PAR
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a.mov(0o6000, a.ptr(cn.KISA0 + 4)) # i.e., A2
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# the standard PDR access/full-length/etc bits
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a.mov(0o077406, a.ptr(cn.KISD0 + 2))
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a.mov(0o077406, a.ptr(cn.KISD0 + 4))
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# count r0, source address r1, destination r2
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a.mov(4096, 'r0')
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a.mov(8192, 'r1')
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a.mov(8192*2, 'r2')
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a.mov('(r1)+', '(r2)+')
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a.literal(0o077002) # SOB to the copy
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# switch the user page to the new mapping
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a.mov(0o6000, a.ptr(cn.UDSA0 + 4*2))
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# and the standard initialization/resume dance
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a.halt()
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a.clr('r0')
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a.clr('(sp)') # just knows the user loop starts at zero
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a.rtt()
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# poke the trap handler vector (250)
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pcps = [kernel_addr + (a.labels['TrapMMU'] * 2), 0]
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self.loadphysmem(p, pcps, 0o250)
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# same for the "trap 0" handler but skip to trap0_offs
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pcps = [kernel_addr + (a.labels['Trap0'] * 2), 0]
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self.loadphysmem(p, pcps, 0o34)
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# all those kernel instructions
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self.loadphysmem(p, a.instructions(), kernel_addr)
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# user mode program:
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# read the given address: mov (r0)+,r1
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# puts 0o42 into r5 (flag that everything worked)
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# trap 0 back to kernel
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# Test can then verify correct value in r5 (indicating
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# MMU aborted or not) and correct value in r1 (indicating
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# mapping is correct)
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user_phys_ISPACEaddr = 0o20000
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with ASM() as u:
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# this value never occurs in user DSPACE (because every
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# word location has been written with an even value)
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# so this is a sentinel for whether the read happened
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user_noval = 1
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u.mov(user_noval, 'r1')
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u.clr('r5') # sentinel becomes 0o42 or 0o666
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u.mov('(r0)+', 'r1')
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u.mov(0o42, 'r5')
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u.trap(0)
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u.halt() # never get here, this is illegal
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self.loadphysmem(p, u.instructions(), user_phys_ISPACEaddr)
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# set the physical memory that will be mapped to user D
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# space to this pattern so the test can verify the mapping
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checksum = 0o123456 # arbitrary
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user_phys_DSPACEbase = 0o200000
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words = (checksum - (user_phys_DSPACEbase + o) & 0o177777
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for o in range(0, 65536, 2))
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self.loadphysmem(p, words, user_phys_DSPACEbase)
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# finally ready to run the kernel setup instructions
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p.run(pc=kernel_addr)
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# this will be used for both up/down testing, based on goodf
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def _test(goodf):
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for segno in range(8):
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for o in range(4096):
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p.run() # picks up at rtt pc
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physval = (checksum -
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((segno * 8192) + (o * 2))) & 0o177777
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if good(dirbit, segno, o*2):
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if goodf(segno, o*2):
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r5_expected = 0o42
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r1_expected = physval
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else:
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@ -834,6 +891,17 @@ class TestMethods(unittest.TestCase):
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self.assertEqual(p.r[1], r1_expected)
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self.assertEqual(p.r[5], r5_expected)
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# run the UP test:
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_test(lambda _segno, _o: _o <= (63 + ((_segno * 64) * 16)))
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# run the code to convert over to DOWN MMU format, and then the test
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p.run(pc=kernel_addr + (a.labels['DOWN'] * 2))
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_test(lambda _segno, _o: _o >= 8192 - (64 + ((_segno * 64) * 16)))
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# last but not least, the BONUS test
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p.run(pc=kernel_addr + (a.labels['BONUS'] * 2))
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_test(lambda _segno, _o: _o >= 8192 - (64 + ((_segno * 64) * 16)))
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def test_ubmap(self):
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p = self.make_pdp()
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