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huge semantic mistake in movb ... fixed

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This commit is contained in:
Neil Webber 2023-10-28 13:35:10 -05:00
parent 482b25d07a
commit fbd057450c
1 changed files with 10 additions and 3 deletions
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13
op4.py
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@ -98,9 +98,16 @@ def op11_movb(cpu, inst):
cpu.psw_z = (val == 0) cpu.psw_z = (val == 0)
cpu.psw_n = (val & 0o200) cpu.psw_n = (val & 0o200)
# No optimization on the write side, because doing so would require # avoid call to the more-general operandx for mode 0, direct register
# duplicating the sign-extend logic here. Yuck. # not only as an optimization, but because unlike other byte operations
cpu.operandx(inst & 0o0077, val, opsize=1) # in register-direct mode, MOVB does a sign-extend.
dst = inst & 0o0077
if (dst < 8): # i.e., mode 0
if val > 127:
val |= 0o177400
cpu.r[dst] = val
else:
cpu.operandx(dst, val, opsize=1)
def op02_cmp(cpu, inst, opsize=2): def op02_cmp(cpu, inst, opsize=2):