IMLAC: Add breakpoints for memory reads and writes.
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1ea82bd127
commit
021413a2d7
3 changed files with 16 additions and 8 deletions
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@ -57,7 +57,7 @@ static uint16 ION;
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/* ROM state. */
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static int rom_type = ROM_NONE;
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static int halt;
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static t_stat stop_reason;
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uint16 memmask = 017777;
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typedef struct {
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@ -175,12 +175,17 @@ static void memaddr (uint16 addr)
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static void memrd (void)
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{
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MB = M[MA];
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if (sim_brk_summ && sim_brk_test(MA, SWMASK('R')))
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stop_reason = STOP_DBKPT;
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}
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static void memwr (void)
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{
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if (rom_type == ROM_NONE || (MA & 0177740) != 040)
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if (rom_type == ROM_NONE || (MA & 0177740) != 040) {
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M[MA] = MB;
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if (sim_brk_summ && sim_brk_test(MA, SWMASK('W')))
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stop_reason = STOP_DBKPT;
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}
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}
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static void cpu_class1 (uint16 insn)
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@ -200,7 +205,8 @@ static void cpu_class1 (uint16 insn)
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AC |= DS;
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}
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halt = !(insn & 0100000);
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if ((insn & 0100000) == 0)
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stop_reason = STOP_HALT;
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}
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static void cpu_ral (int n)
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@ -443,7 +449,7 @@ t_stat sim_instr (void)
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if ((reason = build_dev_tab ()) != SCPE_OK)
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return reason;
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halt = 0;
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stop_reason = 0;
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for (;;) {
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AIO_CHECK_EVENT;
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@ -470,8 +476,8 @@ t_stat sim_instr (void)
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return SCPE_STEP;
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}
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if (halt)
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return STOP_HALT;
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if (stop_reason)
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return stop_reason;
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if (ion_delay && --ion_delay == 0) {
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sim_debug (DBG_IRQ, &irq_dev, "Interrupts on\n");
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@ -569,7 +575,7 @@ static t_bool cpu_is_pc_a_subroutine_call (t_addr **ret_addrs)
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static t_stat
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cpu_reset (DEVICE *dptr)
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{
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sim_brk_types = SWMASK('D') | SWMASK('E');
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sim_brk_types = SWMASK('D') | SWMASK('E') | SWMASK('R') | SWMASK('W');
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sim_brk_dflt = SWMASK ('E');
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sim_vm_is_subroutine_call = &cpu_is_pc_a_subroutine_call;
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return SCPE_OK;
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@ -33,7 +33,8 @@
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#define STOP_HALT 1
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#define STOP_IBKPT 2
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#define STOP_ACCESS 3
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#define STOP_DBKPT 3
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#define STOP_ACCESS 4
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#define FLAG_PTR 010000
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#define FLAG_PTP 000400
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@ -57,6 +57,7 @@ const char *sim_stop_messages[SCPE_BASE] = {
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"Unknown error",
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"HALT instruction",
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"Breakpoint",
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"Watchpoint",
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"Invalid access",
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};
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