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PDP8: Zeroed result exponent in double precision (COVERITY)

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Bob Supnik 2022-06-16 16:13:46 -07:00 • committed by Mark Pizzolato
parent 28fd79ef06
commit 07ea411d3e
2 changed files with 8 additions and 2 deletions
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1
PDP8/pdp8_cpu.c
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@ -25,6 +25,7 @@
cpu central processor cpu central processor
21-Oct-21 RMS Fixed bug in reporting device conflicts (Hans-Bernd Eggenstein)
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY) 07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
09-Mar-17 RMS Fixed PCQ_ENTRY for interrupts (COVERITY) 09-Mar-17 RMS Fixed PCQ_ENTRY for interrupts (COVERITY)
13-Feb-17 RMS RESET clear L'AC, per schematics 13-Feb-17 RMS RESET clear L'AC, per schematics

9
PDP8/pdp8_fpp.c
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@ -1,6 +1,6 @@
/* pdp8_fpp.c: PDP-8 floating point processor (FPP8A) /* pdp8_fpp.c: PDP-8 floating point processor (FPP8A)
Copyright (c) 2007-2021, Robert M Supnik Copyright (c) 2007-2022, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
fpp FPP8A floating point processor fpp FPP8A floating point processor
11-Mar-22 RMS Zeroed result exponent in double precision (COVERITY)
05-Jan-22 RHM Fix fencepost error in FP multiply for extended 05-Jan-22 RHM Fix fencepost error in FP multiply for extended
precision precision
21-Oct-21 RMS Added device number display 21-Oct-21 RMS Added device number display
@ -842,6 +843,7 @@ if (fpp_sta & FPS_DP) { /* dp? */
uint32 cout = fpp_fr_add (z.fr, x.fr, y.fr, EXTEND);/* z = a + b */ uint32 cout = fpp_fr_add (z.fr, x.fr, y.fr, EXTEND);/* z = a + b */
uint32 zsign = z.fr[0] & FPN_FRSIGN; uint32 zsign = z.fr[0] & FPN_FRSIGN;
cout = (cout? 04000: 0); /* make sign bit */ cout = (cout? 04000: 0); /* make sign bit */
z.exp = 0; /* not used in DP */
/* overflow is indicated when signs are equal and overflow does not /* overflow is indicated when signs are equal and overflow does not
match the result sign bit */ match the result sign bit */
fpp_copy (a, &z); /* result is z */ fpp_copy (a, &z); /* result is z */
@ -897,8 +899,10 @@ if ((fpp_fr_test(y.fr, 0, EXACT-1) == 0) && (y.fr[EXACT-1] < 2)) {
y.exp = 0; y.exp = 0;
y.fr[EXACT-1] = 0; y.fr[EXACT-1] = 0;
} }
if (fpp_sta & FPS_DP) /* dp? */ if (fpp_sta & FPS_DP) { /* dp? */
fpp_fr_mul (z.fr, x.fr, y.fr, TRUE); /* mult frac */ fpp_fr_mul (z.fr, x.fr, y.fr, TRUE); /* mult frac */
z.exp = 0; /* not used in DP */
}
else { /* fp or ep */ else { /* fp or ep */
fpp_norm (&x, EXACT); fpp_norm (&x, EXACT);
fpp_norm (&y, EXACT); fpp_norm (&y, EXACT);
@ -934,6 +938,7 @@ if (fpp_sta & FPS_DP) { /* dp? */
fpp_dump_apt (fpp_apta, FPS_IOVX); /* error */ fpp_dump_apt (fpp_apta, FPS_IOVX); /* error */
return; return;
} }
z.exp = 0; /* not used in DP */
fpp_copy (a, &z); /* result is z */ fpp_copy (a, &z); /* result is z */
} }
else { /* fp or ep */ else { /* fp or ep */