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sigma: Add "Sigma 7 BigMem" as a model variant

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BigMem is a Sigma 9 memory management retrofit to the Sigma 7.
This commit is contained in:
Bob Supnik 2017-03-20 08:02:57 -07:00 • committed by Mark Pizzolato
parent c26c6ea501
commit 0cc2a469b2
2 changed files with 14 additions and 8 deletions
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9
sigma/sigma_cpu.c
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@ -316,6 +316,7 @@ MTAB cpu_mod[] = {
{ CPUF_MODEL, CPUF_S5, "Sigma 5", "SIGMA5", &cpu_set_type }, { CPUF_MODEL, CPUF_S5, "Sigma 5", "SIGMA5", &cpu_set_type },
{ CPUF_MODEL, CPUF_S6, "Sigma 6", "SIGMA6", &cpu_set_type }, { CPUF_MODEL, CPUF_S6, "Sigma 6", "SIGMA6", &cpu_set_type },
{ CPUF_MODEL, CPUF_S7, "Sigma 7", "SIGMA7", &cpu_set_type }, { CPUF_MODEL, CPUF_S7, "Sigma 7", "SIGMA7", &cpu_set_type },
{ CPUF_MODEL, CPUF_S7B, "Sigma 7 BigMem", "SIGMA7B", & cpu_set_type },
// { CPUF_MODEL, CPUF_S8, "Sigma 8", "SIGMA8", &cpu_set_type }, // { CPUF_MODEL, CPUF_S8, "Sigma 8", "SIGMA8", &cpu_set_type },
// { CPUF_MODEL, CPUF_S9, "Sigma 9", "SIGMA9", &cpu_set_type }, // { CPUF_MODEL, CPUF_S9, "Sigma 9", "SIGMA9", &cpu_set_type },
// { CPUF_MODEL, CPUF_550, "550", "550", &cpu_set_type }, // { CPUF_MODEL, CPUF_550, "550", "550", &cpu_set_type },
@ -396,6 +397,8 @@ cpu_var_t cpu_tab[] = {
CC1|CC2, CPUF_STR|CPUF_MAP|CPUF_WLK|CPUF_DEC, CPUF_FP|CPUF_LAMS }, CC1|CC2, CPUF_STR|CPUF_MAP|CPUF_WLK|CPUF_DEC, CPUF_FP|CPUF_LAMS },
{ 0x080E0000, 0xC8FFFE0F, 0x0FC, PAMASK17, 14, 8, /* S7 */ { 0x080E0000, 0xC8FFFE0F, 0x0FC, PAMASK17, 14, 8, /* S7 */
CC1|CC2, CPUF_STR|CPUF_MAP|CPUF_WLK, CPUF_FP|CPUF_DEC|CPUF_LAMS }, CC1|CC2, CPUF_STR|CPUF_MAP|CPUF_WLK, CPUF_FP|CPUF_DEC|CPUF_LAMS },
{ 0x080E0000, 0xC8FFFE0F, 0x0FC, PAMASK20, 14, 8, /* S7B */
CC1|CC2, CPUF_STR|CPUF_MAP|CPUF_WLK, CPUF_FP|CPUF_DEC|CPUF_LAMS },
{ 0x084E0000, 0xC8FF00C7, 0x0FC, PAMASK17, 14, 8, /* S8 */ { 0x084E0000, 0xC8FF00C7, 0x0FC, PAMASK17, 14, 8, /* S8 */
CC1|CC2|CC3, CPUF_STR|CPUF_FP|CPUF_WLK|CPUF_LAMS, 0 }, CC1|CC2|CC3, CPUF_STR|CPUF_FP|CPUF_WLK|CPUF_LAMS, 0 },
{ 0x08060000, 0xC8400007, 0x0FC, PAMASK22, 14, 8, /* S9 */ { 0x08060000, 0xC8400007, 0x0FC, PAMASK22, 14, 8, /* S9 */
@ -442,7 +445,8 @@ while (reason == 0) { /* loop until stop */
if (int_hireq < NO_INT) { /* interrupt req? */ if (int_hireq < NO_INT) { /* interrupt req? */
uint32 sav_hi, vec, wd, op; uint32 sav_hi, vec, wd, op;
vec = io_ackn_int (sav_hi = int_hireq); /* get vector */ sav_hi = int_hireq; /* save level */
vec = io_ackn_int (int_hireq); /* get vector */
if (vec == 0) { /* illegal vector? */ if (vec == 0) { /* illegal vector? */
reason = STOP_ILLVEC; /* something wrong */ reason = STOP_ILLVEC; /* something wrong */
break; break;
@ -478,7 +482,8 @@ while (reason == 0) { /* loop until stop */
if (PSW_QRX9 && (PC & PSW1_XA)) /* S9 real ext && ext? */ if (PSW_QRX9 && (PC & PSW1_XA)) /* S9 real ext && ext? */
rpc = (PSW2 & PSW2_EA) | (PC & ~PSW1_XA); /* 22b phys address */ rpc = (PSW2 & PSW2_EA) | (PC & ~PSW1_XA); /* 22b phys address */
else rpc = PC; /* standard 17b PC */ else rpc = PC; /* standard 17b PC */
PC = cpu_add_PC (old_PC = PC, 1); /* increment PC */ old_PC = PC; /* save PC */
PC = cpu_add_PC (PC, 1); /* increment PC */
if (((tr = ReadW (rpc << 2, &ir, VI)) != 0) || /* fetch inst, err? */ if (((tr = ReadW (rpc << 2, &ir, VI)) != 0) || /* fetch inst, err? */
((tr = cpu_one_inst (rpc, ir)) != 0)) { /* exec inst, error? */ ((tr = cpu_one_inst (rpc, ir)) != 0)) { /* exec inst, error? */
if (tr & TR_FL) { /* trap? */ if (tr & TR_FL) { /* trap? */

13
sigma/sigma_defs.h
View file

@ -97,10 +97,11 @@
#define CPU_V_S5 0 #define CPU_V_S5 0
#define CPU_V_S6 1 #define CPU_V_S6 1
#define CPU_V_S7 2 #define CPU_V_S7 2
#define CPU_V_S8 3 /* not supported */ #define CPU_V_S7B 3
#define CPU_V_S9 4 /* not supported */ #define CPU_V_S8 4 /* not supported */
#define CPU_V_550 5 /* not supported */ #define CPU_V_S9 5 /* not supported */
#define CPU_V_560 6 /* not supported */ #define CPU_V_550 6 /* not supported */
#define CPU_V_560 7 /* not supported */
#define CPU_S5 (1u << CPU_V_S5) #define CPU_S5 (1u << CPU_V_S5)
#define CPU_S6 (1u << CPU_V_S6) #define CPU_S6 (1u << CPU_V_S6)
#define CPU_S7 (1u << CPU_V_S7) #define CPU_S7 (1u << CPU_V_S7)
@ -113,10 +114,10 @@
#define QCPU_S5 (cpu_model == CPU_V_S5) #define QCPU_S5 (cpu_model == CPU_V_S5)
#define QCPU_S9 (cpu_model == CPU_V_S9) #define QCPU_S9 (cpu_model == CPU_V_S9)
#define QCPU_5X0 ((1u << cpu_model) & (CPU_550|CPU_560)) #define QCPU_5X0 ((1u << cpu_model) & (CPU_550|CPU_560))
#define QCPU_S567 ((1u << cpu_model) & (CPU_S5|CPU_S6|CPU_S7)) #define QCPU_S567 ((1u << cpu_model) & (CPU_S5|CPU_S6|CPU_S7|CPU_S7B))
#define QCPU_S89 ((1u << cpu_model) & (CPU_S8|CPU_S9)) #define QCPU_S89 ((1u << cpu_model) & (CPU_S8|CPU_S9))
#define QCPU_S89_5X0 ((1u << cpu_model) & (CPU_S8|CPU_S9|CPU_550|CPU_560)) #define QCPU_S89_5X0 ((1u << cpu_model) & (CPU_S8|CPU_S9|CPU_550|CPU_560))
#define QCPU_BIGM ((1u << cpu_model) & (CPU_S9|CPU_550|CPU_560)) #define QCPU_BIGM ((1u << cpu_model) & (CPU_S7B|CPU_S9|CPU_550|CPU_560))
#define CPU_MUNIT_SIZE (1u << 15) /* mem unit size */ #define CPU_MUNIT_SIZE (1u << 15) /* mem unit size */