B5500: Changes to allow DCMCP to use DTC device.
Also changed how interrupts are generated. When a line changes state and interrupt should be generated. Once this is read no further notification should be posted. If no characters are written in a record the DTC should transition to IDLE state.
This commit is contained in:
Richard Cornwell
Mark Pizzolato
parent
44f523a036
commit
0e1f84357c
1 changed files with 45 additions and 16 deletions
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@ -282,8 +282,12 @@ t_stat dtc_srv(UNIT * uptr)
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm inqury found %d %d ",
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm inqury found %d %d ",
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line, buf);
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line, buf);
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if (line != -1) {
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if (line != -1) {
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chan_set_eof(chan);
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if ((dtc_lstatus[line] & BufSMASK) == BufWriteRdy) {
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sim_debug(DEBUG_DETAIL, &dtc_dev, " writerdy ");
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chan_set_eof(chan);
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sim_debug(DEBUG_DETAIL, &dtc_dev, " writerdy ");
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} else {
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sim_debug(DEBUG_DETAIL, &dtc_dev, " idle ");
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}
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} else if (buf != -1) {
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} else if (buf != -1) {
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chan_set_read(chan);
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chan_set_read(chan);
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sim_debug(DEBUG_DETAIL, &dtc_dev, " readrdy ");
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sim_debug(DEBUG_DETAIL, &dtc_dev, " readrdy ");
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@ -311,6 +315,9 @@ t_stat dtc_srv(UNIT * uptr)
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chan_set_eof(chan);
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chan_set_eof(chan);
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sim_debug(DEBUG_DETAIL, &dtc_dev, " writerdy ");
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sim_debug(DEBUG_DETAIL, &dtc_dev, " writerdy ");
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break;
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break;
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case BufIdle:
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sim_debug(DEBUG_DETAIL, &dtc_dev, " idle ");
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break;
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default:
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default:
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chan_set_error(chan);
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chan_set_error(chan);
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sim_debug(DEBUG_DETAIL, &dtc_dev, " busy ");
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sim_debug(DEBUG_DETAIL, &dtc_dev, " busy ");
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@ -368,7 +375,6 @@ t_stat dtc_srv(UNIT * uptr)
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/* Ok to start filling */
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/* Ok to start filling */
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case BufIdle:
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case BufIdle:
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case BufWriteRdy:
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case BufWriteRdy:
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dtc_lstatus[line] = BufWrite;
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dtc_bufptr[line] = 0;
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dtc_bufptr[line] = 0;
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dtc_bsize[line] = 0;
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dtc_bsize[line] = 0;
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm write start %d\n",
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm write start %d\n",
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@ -388,24 +394,31 @@ t_stat dtc_srv(UNIT * uptr)
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if (dtc_lstatus[line] & BufAbnormal) {
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if (dtc_lstatus[line] & BufAbnormal) {
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chan_set_wcflg(chan);
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chan_set_wcflg(chan);
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}
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}
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dtc_lstatus[line] = BufOutBusy;
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/* Empty write, clears flags */
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if (dtc_bsize[line] == 0) {
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sim_debug(DEBUG_DETAIL, &dtc_dev, "empty\n");
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if ((dtc_lstatus[line] & BufSMASK) != BufIdle) {
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dtc_lstatus[line] = BufIRQ|BufIdle;
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IAR |= IRQ_12;
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}
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/* Check if we filled up buffer */
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/* Check if we filled up buffer */
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if (dtc_bsize[line] >= dtc_blimit[line]) {
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} else if (dtc_bsize[line] >= dtc_blimit[line]) {
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dtc_lstatus[line] = BufOutBusy;
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chan_set_gm(chan);
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chan_set_gm(chan);
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sim_debug(DEBUG_DETAIL, &dtc_dev, "full ");
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sim_debug(DEBUG_DETAIL, &dtc_dev, "full ");
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/* Empty write, clears flags */
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} else if (dtc_bsize[line] == 0) {
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sim_debug(DEBUG_DETAIL, &dtc_dev, "empty\n");
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dtc_lstatus[line] = BufIdle;
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} else {
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} else {
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dtc_lstatus[line] |= BufGM;
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dtc_lstatus[line] = BufOutBusy|BufGM;
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sim_debug(DEBUG_DETAIL, &dtc_dev, "gm ");
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sim_debug(DEBUG_DETAIL, &dtc_dev, "gm ");
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}
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}
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sim_debug(DEBUG_DETAIL, &dtc_dev, "\n");
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sim_debug(DEBUG_DETAIL, &dtc_dev, "\n");
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for (ttu = 1; line > 15; ttu++)
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line -= 15;
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chan_set_wc(chan, (ttu << 5) | line);
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chan_set_end(chan);
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chan_set_end(chan);
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uptr->u5 = DTC_RDY;
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uptr->u5 = DTC_RDY;
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return SCPE_OK;
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return SCPE_OK;
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} else {
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} else {
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dtc_lstatus[line] = BufWrite;
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dtc_buf[line][dtc_bufptr[line]++] = ch & 077;
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dtc_buf[line][dtc_bufptr[line]++] = ch & 077;
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sim_debug(DEBUG_DATA, &dtc_dev, "Datacomm write data %d %02o %d\n",
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sim_debug(DEBUG_DATA, &dtc_dev, "Datacomm write data %d %02o %d\n",
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line, ch&077, dtc_bufptr[line]);
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line, ch&077, dtc_bufptr[line]);
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@ -464,14 +477,18 @@ t_stat dtc_srv(UNIT * uptr)
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if (dtc_lstatus[line] & BufAbnormal)
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if (dtc_lstatus[line] & BufAbnormal)
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chan_set_wcflg(chan);
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chan_set_wcflg(chan);
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if (dtc_ldsc[line].conn == 0) /* connected? */
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if (dtc_ldsc[line].conn == 0) /* connected? */
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dtc_lstatus[line] = BufNotReady;
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dtc_lstatus[line] = BufIRQ|BufNotReady;
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else
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else
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dtc_lstatus[line] = BufIdle;
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dtc_lstatus[line] = BufIRQ|BufIdle;
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dtc_bsize[line] = 0;
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dtc_bsize[line] = 0;
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chan_set_end(chan);
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uptr->u5 = DTC_RDY;
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm read done %d\n",
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sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm read done %d\n",
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line);
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line);
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for (ttu = 1; line > 15; ttu++)
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line -= 15;
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chan_set_wc(chan, (ttu << 5) | line);
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chan_set_end(chan);
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uptr->u5 = DTC_RDY;
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IAR |= IRQ_12;
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return SCPE_OK;
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return SCPE_OK;
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} else {
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} else {
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sim_debug(DEBUG_DATA, &dtc_dev, "Datacomm read data %d %02o %d\n",
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sim_debug(DEBUG_DATA, &dtc_dev, "Datacomm read data %d %02o %d\n",
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@ -559,6 +576,16 @@ dtco_srv(UNIT * uptr)
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"Datacomm recieve ENQ %d\n", ln);
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"Datacomm recieve ENQ %d\n", ln);
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t = 0;
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t = 0;
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break;
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break;
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case '\003': /* ^B send STX */
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dtc_lstatus[ln] &= ~BufSMASK;
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dtc_lstatus[ln] |= BufIRQ|BufReadRdy|BufAbnormal;
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dtc_buf[ln][0] = 0;
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dtc_buf[ln][1] = 017;
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dtc_buf[ln][2] = 077;
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dtc_bsize[ln] = 1;
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IAR |= IRQ_12;
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t = 0;
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break;
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case '}':
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case '}':
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dtc_buf[ln][dtc_bufptr[ln]++] = 017;
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dtc_buf[ln][dtc_bufptr[ln]++] = 017;
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dtc_lstatus[ln] |= BufAbnormal;
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dtc_lstatus[ln] |= BufAbnormal;
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@ -574,6 +601,7 @@ dtco_srv(UNIT * uptr)
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dtc_bsize[ln] = dtc_bufptr[ln];
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dtc_bsize[ln] = dtc_bufptr[ln];
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IAR |= IRQ_12;
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IAR |= IRQ_12;
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t = 0;
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t = 0;
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c1 = 0;
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sim_debug(DEBUG_DETAIL, &dtc_dev,
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sim_debug(DEBUG_DETAIL, &dtc_dev,
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"Datacomm recieve %d return\n", ln);
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"Datacomm recieve %d return\n", ln);
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break;
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break;
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@ -593,7 +621,7 @@ dtco_srv(UNIT * uptr)
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}
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}
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c1 = 0;
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c1 = 0;
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sim_debug(DEBUG_DATA, &dtc_dev,
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sim_debug(DEBUG_DATA, &dtc_dev,
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"Datacomm recieve %d backspace\n", ln);
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"Datacomm recieve %d backspace %d\n", ln, dtc_bufptr[ln]);
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break;
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break;
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case '?':
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case '?':
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sim_debug(DEBUG_DATA, &dtc_dev,
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sim_debug(DEBUG_DATA, &dtc_dev,
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@ -604,7 +632,8 @@ dtco_srv(UNIT * uptr)
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break;
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break;
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default:
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default:
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sim_debug(DEBUG_DATA, &dtc_dev,
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sim_debug(DEBUG_DATA, &dtc_dev,
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"Datacomm recieve %d %02x %c %02o\n", ln, c, c, c1);
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"Datacomm recieve %d %02x %c %02o %d\n", ln, c, c, c1,
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dtc_bufptr[ln]);
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}
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}
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if (t && c1) {
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if (t && c1) {
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tmxr_putc_ln(&dtc_ldsc[ln], con_to_ascii[c1]);
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tmxr_putc_ln(&dtc_ldsc[ln], con_to_ascii[c1]);
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