diff --git a/doc/simh.doc b/doc/simh.doc index 10dbf0ef..bb5de8b5 100644 --- a/doc/simh.doc +++ b/doc/simh.doc @@ -1,26 +1,26 @@ {\rtf1\adeflang1025\ansi\ansicpg1252\uc1\adeff0\deff0\stshfdbch31505\stshfloch31506\stshfhich31506\stshfbi0\deflang1033\deflangfe1033\themelang1033\themelangfe0\themelangcs0{\fonttbl{\f0\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f1\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604020202020204}Arial;} {\f2\fbidi \fmodern\fcharset0\fprq1{\*\panose 02070309020205020404}Courier New;}{\f3\fbidi \froman\fcharset2\fprq2{\*\panose 05050102010706020507}Symbol;}{\f10\fbidi \fnil\fcharset2\fprq2{\*\panose 05000000000000000000}Wingdings;} {\f11\fbidi \fmodern\fcharset128\fprq1{\*\panose 02020609040205080304}MS Mincho{\*\falt MS ??};}{\f34\fbidi \froman\fcharset0\fprq2{\*\panose 02040503050406030204}Cambria Math;}{\f37\fbidi \fswiss\fcharset0\fprq2{\*\panose 020f0502020204030204}Calibri;} -{\f38\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604030504040204}Tahoma;}{\f42\fbidi \fmodern\fcharset128\fprq1{\*\panose 02020609040205080304}@MS Mincho;}{\flomajor\f31500\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;} +{\f38\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604030504040204}Tahoma;}{\f39\fbidi \fmodern\fcharset128\fprq1{\*\panose 00000000000000000000}@MS Mincho;}{\flomajor\f31500\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;} {\fdbmajor\f31501\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\fhimajor\f31502\fbidi \froman\fcharset0\fprq2{\*\panose 02040503050406030204}Cambria;} {\fbimajor\f31503\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\flominor\f31504\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;} {\fdbminor\f31505\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\fhiminor\f31506\fbidi \fswiss\fcharset0\fprq2{\*\panose 020f0502020204030204}Calibri;} -{\fbiminor\f31507\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f43\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\f44\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;} -{\f46\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\f47\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\f48\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\f49\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);} -{\f50\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\f51\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\f53\fbidi \fswiss\fcharset238\fprq2 Arial CE;}{\f54\fbidi \fswiss\fcharset204\fprq2 Arial Cyr;} -{\f56\fbidi \fswiss\fcharset161\fprq2 Arial Greek;}{\f57\fbidi \fswiss\fcharset162\fprq2 Arial Tur;}{\f58\fbidi \fswiss\fcharset177\fprq2 Arial (Hebrew);}{\f59\fbidi \fswiss\fcharset178\fprq2 Arial (Arabic);} -{\f60\fbidi \fswiss\fcharset186\fprq2 Arial Baltic;}{\f61\fbidi \fswiss\fcharset163\fprq2 Arial (Vietnamese);}{\f63\fbidi \fmodern\fcharset238\fprq1 Courier New CE;}{\f64\fbidi \fmodern\fcharset204\fprq1 Courier New Cyr;} -{\f66\fbidi \fmodern\fcharset161\fprq1 Courier New Greek;}{\f67\fbidi \fmodern\fcharset162\fprq1 Courier New Tur;}{\f68\fbidi \fmodern\fcharset177\fprq1 Courier New (Hebrew);}{\f69\fbidi \fmodern\fcharset178\fprq1 Courier New (Arabic);} -{\f70\fbidi \fmodern\fcharset186\fprq1 Courier New Baltic;}{\f71\fbidi \fmodern\fcharset163\fprq1 Courier New (Vietnamese);}{\f155\fbidi \fmodern\fcharset0\fprq1 MS Mincho Western{\*\falt MS ??};} -{\f153\fbidi \fmodern\fcharset238\fprq1 MS Mincho CE{\*\falt MS ??};}{\f154\fbidi \fmodern\fcharset204\fprq1 MS Mincho Cyr{\*\falt MS ??};}{\f156\fbidi \fmodern\fcharset161\fprq1 MS Mincho Greek{\*\falt MS ??};} -{\f157\fbidi \fmodern\fcharset162\fprq1 MS Mincho Tur{\*\falt MS ??};}{\f160\fbidi \fmodern\fcharset186\fprq1 MS Mincho Baltic{\*\falt MS ??};}{\f383\fbidi \froman\fcharset238\fprq2 Cambria Math CE;} -{\f384\fbidi \froman\fcharset204\fprq2 Cambria Math Cyr;}{\f386\fbidi \froman\fcharset161\fprq2 Cambria Math Greek;}{\f387\fbidi \froman\fcharset162\fprq2 Cambria Math Tur;}{\f390\fbidi \froman\fcharset186\fprq2 Cambria Math Baltic;} -{\f391\fbidi \froman\fcharset163\fprq2 Cambria Math (Vietnamese);}{\f413\fbidi \fswiss\fcharset238\fprq2 Calibri CE;}{\f414\fbidi \fswiss\fcharset204\fprq2 Calibri Cyr;}{\f416\fbidi \fswiss\fcharset161\fprq2 Calibri Greek;} -{\f417\fbidi \fswiss\fcharset162\fprq2 Calibri Tur;}{\f420\fbidi \fswiss\fcharset186\fprq2 Calibri Baltic;}{\f421\fbidi \fswiss\fcharset163\fprq2 Calibri (Vietnamese);}{\f423\fbidi \fswiss\fcharset238\fprq2 Tahoma CE;} -{\f424\fbidi \fswiss\fcharset204\fprq2 Tahoma Cyr;}{\f426\fbidi \fswiss\fcharset161\fprq2 Tahoma Greek;}{\f427\fbidi \fswiss\fcharset162\fprq2 Tahoma Tur;}{\f428\fbidi \fswiss\fcharset177\fprq2 Tahoma (Hebrew);} -{\f429\fbidi \fswiss\fcharset178\fprq2 Tahoma (Arabic);}{\f430\fbidi \fswiss\fcharset186\fprq2 Tahoma Baltic;}{\f431\fbidi \fswiss\fcharset163\fprq2 Tahoma (Vietnamese);}{\f432\fbidi \fswiss\fcharset222\fprq2 Tahoma (Thai);} -{\f465\fbidi \fmodern\fcharset0\fprq1 @MS Mincho Western;}{\f463\fbidi \fmodern\fcharset238\fprq1 @MS Mincho CE;}{\f464\fbidi \fmodern\fcharset204\fprq1 @MS Mincho Cyr;}{\f466\fbidi \fmodern\fcharset161\fprq1 @MS Mincho Greek;} -{\f467\fbidi \fmodern\fcharset162\fprq1 @MS Mincho Tur;}{\f470\fbidi \fmodern\fcharset186\fprq1 @MS Mincho Baltic;}{\flomajor\f31508\fbidi \froman\fcharset238\fprq2 Times New Roman CE;} +{\fbiminor\f31507\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f40\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\f41\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;} +{\f43\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\f44\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\f45\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\f46\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);} +{\f47\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\f48\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\f50\fbidi \fswiss\fcharset238\fprq2 Arial CE;}{\f51\fbidi \fswiss\fcharset204\fprq2 Arial Cyr;} +{\f53\fbidi \fswiss\fcharset161\fprq2 Arial Greek;}{\f54\fbidi \fswiss\fcharset162\fprq2 Arial Tur;}{\f55\fbidi \fswiss\fcharset177\fprq2 Arial (Hebrew);}{\f56\fbidi \fswiss\fcharset178\fprq2 Arial (Arabic);} +{\f57\fbidi \fswiss\fcharset186\fprq2 Arial Baltic;}{\f58\fbidi \fswiss\fcharset163\fprq2 Arial (Vietnamese);}{\f60\fbidi \fmodern\fcharset238\fprq1 Courier New CE;}{\f61\fbidi \fmodern\fcharset204\fprq1 Courier New Cyr;} +{\f63\fbidi \fmodern\fcharset161\fprq1 Courier New Greek;}{\f64\fbidi \fmodern\fcharset162\fprq1 Courier New Tur;}{\f65\fbidi \fmodern\fcharset177\fprq1 Courier New (Hebrew);}{\f66\fbidi \fmodern\fcharset178\fprq1 Courier New (Arabic);} +{\f67\fbidi \fmodern\fcharset186\fprq1 Courier New Baltic;}{\f68\fbidi \fmodern\fcharset163\fprq1 Courier New (Vietnamese);}{\f152\fbidi \fmodern\fcharset0\fprq1 MS Mincho Western{\*\falt MS ??};} +{\f150\fbidi \fmodern\fcharset238\fprq1 MS Mincho CE{\*\falt MS ??};}{\f151\fbidi \fmodern\fcharset204\fprq1 MS Mincho Cyr{\*\falt MS ??};}{\f153\fbidi \fmodern\fcharset161\fprq1 MS Mincho Greek{\*\falt MS ??};} +{\f154\fbidi \fmodern\fcharset162\fprq1 MS Mincho Tur{\*\falt MS ??};}{\f157\fbidi \fmodern\fcharset186\fprq1 MS Mincho Baltic{\*\falt MS ??};}{\f380\fbidi \froman\fcharset238\fprq2 Cambria Math CE;} +{\f381\fbidi \froman\fcharset204\fprq2 Cambria Math Cyr;}{\f383\fbidi \froman\fcharset161\fprq2 Cambria Math Greek;}{\f384\fbidi \froman\fcharset162\fprq2 Cambria Math Tur;}{\f387\fbidi \froman\fcharset186\fprq2 Cambria Math Baltic;} +{\f388\fbidi \froman\fcharset163\fprq2 Cambria Math (Vietnamese);}{\f410\fbidi \fswiss\fcharset238\fprq2 Calibri CE;}{\f411\fbidi \fswiss\fcharset204\fprq2 Calibri Cyr;}{\f413\fbidi \fswiss\fcharset161\fprq2 Calibri Greek;} +{\f414\fbidi \fswiss\fcharset162\fprq2 Calibri Tur;}{\f417\fbidi \fswiss\fcharset186\fprq2 Calibri Baltic;}{\f418\fbidi \fswiss\fcharset163\fprq2 Calibri (Vietnamese);}{\f420\fbidi \fswiss\fcharset238\fprq2 Tahoma CE;} +{\f421\fbidi \fswiss\fcharset204\fprq2 Tahoma Cyr;}{\f423\fbidi \fswiss\fcharset161\fprq2 Tahoma Greek;}{\f424\fbidi \fswiss\fcharset162\fprq2 Tahoma Tur;}{\f425\fbidi \fswiss\fcharset177\fprq2 Tahoma (Hebrew);} +{\f426\fbidi \fswiss\fcharset178\fprq2 Tahoma (Arabic);}{\f427\fbidi \fswiss\fcharset186\fprq2 Tahoma Baltic;}{\f428\fbidi \fswiss\fcharset163\fprq2 Tahoma (Vietnamese);}{\f429\fbidi \fswiss\fcharset222\fprq2 Tahoma (Thai);} +{\f432\fbidi \fmodern\fcharset0\fprq1 @MS Mincho Western;}{\f430\fbidi \fmodern\fcharset238\fprq1 @MS Mincho CE;}{\f431\fbidi \fmodern\fcharset204\fprq1 @MS Mincho Cyr;}{\f433\fbidi \fmodern\fcharset161\fprq1 @MS Mincho Greek;} +{\f434\fbidi \fmodern\fcharset162\fprq1 @MS Mincho Tur;}{\f437\fbidi \fmodern\fcharset186\fprq1 @MS Mincho Baltic;}{\flomajor\f31508\fbidi \froman\fcharset238\fprq2 Times New Roman CE;} {\flomajor\f31509\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\flomajor\f31511\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\flomajor\f31512\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;} {\flomajor\f31513\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\flomajor\f31514\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\flomajor\f31515\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;} {\flomajor\f31516\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fdbmajor\f31518\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\fdbmajor\f31519\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;} @@ -192,23 +192,23 @@ Body Text Indent 2 Char;}{\s36\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum 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\fi-720\li720\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Writing a Simulator for the SIMH System -\par }\pard \ltrpar\qc \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Revised }{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid14693620 -\hich\af1\dbch\af31505\loch\f1 03}{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid10051909 -}{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid14693620 \hich\af1\dbch\af31505\loch\f1 Jan}{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 +\par }\pard \ltrpar\qc \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Revised }{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid2634434 +\hich\af1\dbch\af31505\loch\f1 15}{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid10051909 -}{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 May}{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 -201}{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid14693620 \hich\af1\dbch\af31505\loch\f1 3}{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for SIMH }{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid10051909 \hich\af1\dbch\af31505\loch\f1 V4.0}{\rtlch\fcs1 \ab\af1\afs32 \ltrch\fcs0 \b\f1\fs32\insrsid4550150 \par }\pard\plain \ltrpar\s36\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af2\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af2\hich\af2\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 @@ -240,358 +240,595 @@ me of Robert M Supnik shall not be used in advertising or otherwise to promote t \dbch\af11\insrsid4550150 \page }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\field\fldedit{\*\fldinst {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TOC \\o }}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 1.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Overview\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 -PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546199 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003100390039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 4}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 2.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 -\af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Data Types\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546200 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200300030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 4}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 -\af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 VM Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546201 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200300031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 5}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 +\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 1.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 +\b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Overview\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 +_Toc356355607 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600300037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 4}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 2.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 +\b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Data Types\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 +_Toc356355608 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600300038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 4}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 +\b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +VM Organization\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 +_Toc356355609 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600300039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 5}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 -\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 -\b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 CPU Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546202 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200300032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1}{ +\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 CPU Organization\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 +PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355610 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { -\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Time Base\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546203 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200300033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Step Function\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _To\hich\af0\dbch\af31505\loch\f0 c347546204 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200300034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Memory Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546205 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200300035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 7}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Interrupt Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546206 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200300036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 7}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.5}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 I/O Dispatching\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546207 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200300037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 8}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.6}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Instruction Execution\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546208 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200300038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 8}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 +\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Time Base +\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355611 +\\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Step Function\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 +_Toc356355612 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 6}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Memory Organization\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF +\hich\af0\dbch\af31505\loch\f0 _Toc356355613 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 7}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.1.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Interrupt Organization\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF +\hich\af0\dbch\af31505\loch\f0 _Toc356355614 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 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\hich\af0\dbch\af31505\loch\f0 +I/O Dispatching\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 +_Toc356355615 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 8}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 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\af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 8}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 -\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 -\b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Peripheral Device Organization\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546209 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200300039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 9}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.2}{ +\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 P\hich\af0\dbch\af31505\loch\f0 eripheral Device Organization\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355617 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 9}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 +\b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { -\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Device Timing\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546210 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200310030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 10}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Clock Calibration\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546211 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200310031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 11}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Idling\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546212 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200310032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 11}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Data I/O\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546213 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200310033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 12}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 +\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.2.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Device Timing\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 +_Toc356355618 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 10}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.2.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Clock Calibration\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF +\hich\af0\dbch\af31505\loch\f0 _Toc356355619 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600310039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 11}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.2.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Idling +\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355620 +\\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 11}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 3.2.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Data I/O +\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355621 +\\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 12}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 -\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 -\ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Data Structures\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546214 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200310034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 13}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 +\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.}{ +\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Data Structures\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355622 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320032000000}}}{\fldrslt {\rtlch\fcs1 \af0 +\ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 13}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 +\b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 -\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 -\b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 sim_device Structure\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546215 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200310035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 13}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1}{ +\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 sim_device Structure\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 +PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355623 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600320033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 13}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { -\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Awidth and Aincr\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546216 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200310036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Device Flags\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546217 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200310037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Context\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546218 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200310038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Examine and Deposit Routines\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546219 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200310039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 15}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.5}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Reset Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546220 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200320030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 16}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.6}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Boot Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546221 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200320031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 16}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.7}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Attach and Detach Routines\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546222 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200320032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 16}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.8}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Memory Size Change Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546223 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 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\ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.9}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Debug Controls\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 +_Toc356355632 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 17}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.10}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Device Specific Help support\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF +\hich\af0\dbch\af31505\loch\f0 _Toc356355633 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 18}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.11}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Help Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 +_Toc356355634 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 18}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.1.12}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Attach Help Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF +\hich\af0\dbch\af31505\loch\f0 _Toc356355635 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 19}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 -\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.\hich\af0\dbch\af31505\loch\f0 2}{ -\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 sim_unit Structure\tab }{\field\flddirty{\*\fldinst { -\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546228 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200320038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 19}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.2}{ +\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 sim_unit Structure\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 +PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355636 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 19}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { -\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.2.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Unit Flags\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546229 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200320039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.2.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Service Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546230 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200330030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 +\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.2.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Unit Flags +\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355637 +\\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.2.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Service Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 +_Toc356355638 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 -\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.3}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 -\b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 sim_reg Structure\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546231 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200330031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.3}{ +\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 sim_reg Structure\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 +PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355639 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600330039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 20}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { -\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.3.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Register Flags\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546232 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200330032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 22}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 +\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.3.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Register Flags\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 +_Toc356355640 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 22}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 -\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 -\b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 sim_mtab Structure\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546233 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200330033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 22}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4}{ +\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 s\hich\af0\dbch\af31505\loch\f0 im_mtab Structure\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355641 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 22}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s25\ql \li400\ri0\widctlpar\tx1200\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin400\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 { -\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Validation Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546234 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200330034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Display Routine\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546235 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200330035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Help Flags\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546236 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200330036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Example arguments in the }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 mstring}{ -\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF -\hich\af0\dbch\af31505\loch\f0 _Toc347546237 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200330037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.5}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Help field\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546238 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200330038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 +\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4.1}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Validation Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF +\hich\af0\dbch\af31505\loch\f0 _Toc356355642 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4.2}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Display Routine\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 +_Toc356355643 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Help Flags +\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355644 +\\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340034000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 24}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4.4}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Example arguments in the }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 mstring}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc3563556\hich\af0\dbch\af31505\loch\f0 45 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340035000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 +\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.4.5}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 +\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 Help field +\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355646 +\\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340036000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 -\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.5}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 -\b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Other Data Structures\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546239 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200330039000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 +\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 4.5}{ +\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Other Data Structures\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 +PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355647 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340037000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s23\ql \li0\ri0\sb120\widctlpar\tx600\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \ab\ai\af0\afs24\alang1025 \ltrch\fcs0 -\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.}{\rtlch\fcs1 \ab0\ai0\af31507\afs22 -\ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 VM Provided Routines\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 -\af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546240 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200340030000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 +\b\i\fs24\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 5.}{ +\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 \b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 +\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 VM Provided Routines\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 +\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355648 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 +\ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600340038000000}}}{\fldrslt {\rtlch\fcs1 \af0 +\ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 +\b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 -\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.1}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 -\b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Instruction Execution\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546241 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200340031000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 25}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.2}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Binary Load a\hich\af0\dbch\af31505\loch\f0 nd Dump\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 -\hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546242 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200340032000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 26}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.3}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Symbolic Examination and Deposit\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546243 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200340033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 26}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 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\hich\af0\dbch\af31505\loch\f0 27}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.4.3}{\rtlch\fcs1 \af31507\afs22 \ltrch\fcs0 \f31506\fs22\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 -\ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Command Input and Post-Processing\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 -\hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546247 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield 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\ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\ai0\af31507\afs22 \ltrch\fcs0 +\b0\i0\f31506\fs22\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \par }\pard\plain \ltrpar\s24\ql \li200\ri0\sb120\widctlpar\tx800\tqr\tldot\tx9350\wrapdefault\faauto\adjustright\rin0\lin200\itap0 \rtlch\fcs1 \ab\af0\afs22\alang1025 \ltrch\fcs0 -\b\fs22\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.1}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 -\b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Terminal Input/Output Formatting Library\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 -\af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 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\ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 Disk Emulation Library\tab }{\field\flddirty{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 -\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc347546253 \\\hich\af0\dbch\af31505\loch\f0 h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 {\*\datafield -08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300340037003500340036003200350033000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \lang1024\langfe1024\noproof\insrsid9796111 \hich\af0\dbch\af31505\loch\f0 35}}}\sectd \ltrsect -\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\lang1024\langfe1024\noproof\insrsid9796111 -\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 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\tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Terminal Input/Output Formatting Library\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +\hich\af0\dbch\af31505\loch\f0 PAGEREF \hich\af0\dbch\af31505\loch\f0 _Toc356355658 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield +08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063003300350036003300350035003600350038000000}}}{\fldrslt {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\hich\af0\dbch\af31505\loch\f0 28}}}\sectd \ltrsect\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 \b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434\charrsid2774735 \hich\af0\dbch\af31505\loch\f0 6.2}{\rtlch\fcs1 \ab0\af31507 \ltrch\fcs0 +\b0\f31506\cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 +Terminal Multiplexer Emulation Library\tab }{\field{\*\fldinst {\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 \hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 PAGEREF +\hich\af0\dbch\af31505\loch\f0 _Toc356355659 \\h\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\revised\lang1024\langfe1024\revauth1\revdttm1729460511\noproof\insrsid2634434 {\*\datafield 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+\hich\af0\dbch\af31505\loch\f0 Data Types\tab \hich\af0\dbch\af31505\loch\f0 4}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 \b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 +\b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 VM Organization\tab \hich\af0\dbch\af31505\loch\f0 5}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 \b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 CPU Organization\tab \hich\af0\dbch\af31505\loch\f0 6}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Time Base\tab \hich\af0\dbch\af31505\loch\f0 6}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Step Function\tab \hich\af0\dbch\af31505\loch\f0 6}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.3}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Memory Organization\tab \hich\af0\dbch\af31505\loch\f0 7}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.4}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Interrupt Organization\tab \hich\af0\dbch\af31505\loch\f0 7}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.5}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 I/O Dispatching\tab \hich\af0\dbch\af31505\loch\f0 8}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.1.6}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Instruction Execution\tab \hich\af0\dbch\af31505\loch\f0 8}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Peripheral Device Organization\tab \hich\af0\dbch\af31505\loch\f0 9}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Device Timing\tab \hich\af0\dbch\af31505\loch\f0 10}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Clock Calibration\tab \hich\af0\dbch\af31505\loch\f0 11}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.3}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Idling\tab \hich\af0\dbch\af31505\loch\f0 11}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 3.2.4}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Data I/O\tab \hich\af0\dbch\af31505\loch\f0 12}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 +\b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Data Structures\tab \hich\af0\dbch\af31505\loch\f0 13}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 \b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 sim_device Structure\tab \hich\af0\dbch\af31505\loch\f0 13}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Awidth and Aincr\tab \hich\af0\dbch\af31505\loch\f0 15}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Device Flags\tab \hich\af0\dbch\af31505\loch\f0 15}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 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\deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Examine and Deposit Routines\tab \hich\af0\dbch\af31505\loch\f0 15}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.5}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Reset Routine\tab \hich\af0\dbch\af31505\loch\f0 16}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.6}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Boot Routine\tab \hich\af0\dbch\af31505\loch\f0 16}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.7}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Attach and Detach Routines\tab \hich\af0\dbch\af31505\loch\f0 16}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.8}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Memory Size Change Routine\tab \hich\af0\dbch\af31505\loch\f0 17}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.9}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Debug Controls\tab \hich\af0\dbch\af31505\loch\f0 17}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.10}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Device Specific Help support\tab \hich\af0\dbch\af31505\loch\f0 18}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.11}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Help Routine\tab \hich\af0\dbch\af31505\loch\f0 18}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.1.12}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Attach Help Routine\tab \hich\af0\dbch\af31505\loch\f0 19}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.2}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 sim_unit Structure\tab \hich\af0\dbch\af31505\loch\f0 19}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.2.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Unit Flags\tab \hich\af0\dbch\af31505\loch\f0 20}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.2.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Service Routine\tab \hich\af0\dbch\af31505\loch\f0 20}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.3}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 sim_reg Structure\tab \hich\af0\dbch\af31505\loch\f0 20}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.3.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Register Flags\tab \hich\af0\dbch\af31505\loch\f0 22}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 sim_mtab Structure\tab \hich\af0\dbch\af31505\loch\f0 22}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Validation Routine\tab \hich\af0\dbch\af31505\loch\f0 24}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Display Routine\tab \hich\af0\dbch\af31505\loch\f0 24}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.3}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Help Flags\tab \hich\af0\dbch\af31505\loch\f0 24}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.4}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Example arguments in the }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 mstring}{ +\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab \hich\af0\dbch\af31505\loch\f0 25}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.4.5}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Help field\tab \hich\af0\dbch\af31505\loch\f0 25}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 4.5}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Other Data Structures\tab \hich\af0\dbch\af31505\loch\f0 25}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 +\b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 VM Provided Routines\tab \hich\af0\dbch\af31505\loch\f0 25}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 \b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.1}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Instruction Execution\tab \hich\af0\dbch\af31505\loch\f0 25}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.2}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Binary Load and Dump\tab \hich\af0\dbch\af31505\loch\f0 26}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.3}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Symbolic Examination and Deposit\tab \hich\af0\dbch\af31505\loch\f0 26}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.4}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Optional Interfaces\tab \hich\af0\dbch\af31505\loch\f0 27}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.4.1}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Once Only Initialization Routine\tab \hich\af0\dbch\af31505\loch\f0 27}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 + +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.4.2}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Address Input and Display\tab \hich\af0\dbch\af31505\loch\f0 27}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.4.3}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Command Input and Post-Processing\tab \hich\af0\dbch\af31505\loch\f0 27}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 + +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 5.4.4}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 +\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 VM-Specific Commands\tab \hich\af0\dbch\af31505\loch\f0 28}{\rtlch\fcs1 \af0\afs22 \ltrch\fcs0 \deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 +\b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Other SCP Facilities\tab \hich\af0\dbch\af31505\loch\f0 28}{\rtlch\fcs1 \ab\ai\af0\afs22 \ltrch\fcs0 \b\i\deleted\f31506\fs22\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.1}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Terminal Input/Output Formatting Library\tab \hich\af0\dbch\af31505\loch\f0 28}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 + +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.2}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Terminal Multiplexer Emulation Library\tab \hich\af0\dbch\af31505\loch\f0 29}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 + +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.3}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Magnetic Tape Emulation Library\tab \hich\af0\dbch\af31505\loch\f0 34}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.4}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Disk Emulation Library\tab \hich\af0\dbch\af31505\loch\f0 35}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434\charrsid16122207 \hich\af0\dbch\af31505\loch\f0 6.5}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 +\b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 \tab }{\rtlch\fcs1 \af0 \ltrch\fcs0 \deleted\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\hich\af0\dbch\af31505\loch\f0 Breakpoint Support\tab \hich\af0\dbch\af31505\loch\f0 37}{\rtlch\fcs1 \ab\af0 \ltrch\fcs0 \b\deleted\f31506\lang1024\langfe1024\revauthdel1\revdttmdel1729460511\noproof\insrsid9796111\delrsid2634434 +\par }}}\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 \sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \page -\par {\*\bkmkstart _Toc347546199}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355607}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Overview{\*\bkmkend _Toc347546199} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Overview{\*\bkmkend _Toc356355607} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 SIMH (history simulators) is a set of portable programs, writt\hich\af1\dbch\af31505\loch\f1 -en in C, which simulate various historically interesting computers. This document describes how to design, write, and check out a new simulator for SIMH. It is not an introduction to either the philosophy or external operation of SIMH, and the reader sh -\hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 -uld be familiar with both of those topics before proceeding. Nor is it a guide to the internal design or operation of SIMH, except insofar as those areas interact with simulator design. Instead, this manual presents and explains the form, meaning, and o -\hich\af1\dbch\af31505\loch\f1 p\hich\af1\dbch\af31505\loch\f1 -eration of the interfaces between simulators and the SIMH simulator control package. It also offers some suggestions for utilizing the services SIMH offers and explains the constraints that all simulators operating within SIMH will experience. +\par \hich\af1\dbch\af31505\loch\f1 +SIMH (history simulators) is a set of portable programs, written in C, which simulate various historically interesting computers. This document describes how to design, write, and check out a new simulator for SIMH. It is not an introducti +\hich\af1\dbch\af31505\loch\f1 +on to either the philosophy or external operation of SIMH, and the reader should be familiar with both of those topics before proceeding. Nor is it a guide to the internal design or operation of SIMH, except insofar as those areas interact with simulator +\hich\af1\dbch\af31505\loch\f1 \hich\af1\dbch\af31505\loch\f1 +design. Instead, this manual presents and explains the form, meaning, and operation of the interfaces between simulators and the SIMH simulator control package. It also offers some suggestions for utilizing the services SIMH offers and explains the cons +\hich\af1\dbch\af31505\loch\f1 t\hich\af1\dbch\af31505\loch\f1 raints that all simulators operating within SIMH will experience. \par -\par \hich\af1\dbch\af31505\loch\f1 Some termi\hich\af1\dbch\af31505\loch\f1 nology: Each simulator consists of a standard }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 simulator control package}{\rtlch\fcs1 \af1 -\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (SCP and related libraries), which provides a control framework and utility routines for a simulator; and a unique }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 virtual machine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (VM), which implements the simulated processor and se\hich\af1\dbch\af31505\loch\f1 -lected peripherals. A VM consists of multiple }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 devices}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -, such as the CPU, paper tape reader, disk controller, etc. Each controller consists of a named state space (called }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 registers}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ) and one or more }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 units}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -. Each unit consists of a numbered state space (call\hich\af1\dbch\af31505\loch\f1 ed a }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 data set}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Some terminology: Each simulator consists of a standard }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 simulator control package}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 (SCP and related libraries), which provides a control framework and utility routines for a simulator; and a\hich\af1\dbch\af31505\loch\f1 unique }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 virtual machine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (VM), which implements the simulated processor and selected peripherals. A VM consists of multiple }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 devices}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +, such as the CPU, paper tape reader, disk controller, etc. Each controller consists of a named state space (called }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 register\hich\af1\dbch\af31505\loch\f1 s}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ) and one or more }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 units}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 . Each unit consists of a numbered state space (called a }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 data set}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ). }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 host computer}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is the system on which SIMH runs; the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 target computer}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is the system being simulated. \par -\par \hich\af1\dbch\af31505\loch\f1 SIMH is unabashedly based on the MIMIC simulation system, designed in the late 1960\hich\f1 \rquote \loch\f1 s by Len Fehskens, Mike McCarthy, and Bob Supnik. \hich\af1\dbch\af31505\loch\f1 This document is based on MIMIC +\par \hich\af1\dbch\af31505\loch\f1 SIMH is unabashedly based on the MIMIC simulation system, \hich\af1\dbch\af31505\loch\f1 designed in the late 1960\hich\f1 \rquote \loch\f1 s by Len Fehskens, Mike McCarthy, and Bob Supnik. This document is based on MIMIC \hich\f1 \rquote \loch\f1 \hich\f1 s published interface specification, \'93\loch\f1 \hich\f1 How to Write a Virtual Machine for the MIMIC Simulation System\'94\loch\f1 , by Len Fehskens and Bob Supnik. \par -\par {\*\bkmkstart _Toc347546200}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355608}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data Types{\*\bkmkend _Toc347546200} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data Types{\*\bkmkend _Toc356355608} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 SIMH is written in C. The host system must su\hich\af1\dbch\af31505\loch\f1 -pport (at least) 32-bit data types (64-bit data types for the PDP-10 and other large-word target systems). To cope with the vagaries of C data types, SIMH defines some unambiguous data types for its interfaces: +\par \hich\af1\dbch\af31505\loch\f1 +SIMH is written in C. The host system must support (at least) 32-bit data types (64-bit data types for the PDP-10 and other large-word target systems). To cope with the vagaries of C data types, SIMH defines some unambiguou +\hich\af1\dbch\af31505\loch\f1 s data types for its interfaces: \par -\par \tab \hich\af1\dbch\af31505\loch\f1 SIMH data type\tab \tab \tab interpretation in typical\hich\af1\dbch\af31505\loch\f1 32-bit C +\par \tab \hich\af1\dbch\af31505\loch\f1 SIMH data type\tab \tab \tab interpretation in typical 32-bit C \par \par \tab \hich\af1\dbch\af31505\loch\f1 int8, uint8\tab \tab \tab signed char, unsigned char \par \tab \hich\af1\dbch\af31505\loch\f1 int16, uint16\tab \tab \tab signed short, unsigned short \par \tab \hich\af1\dbch\af31505\loch\f1 int32, uint32\tab \tab \tab signed int, unsigned int -\par \tab \hich\af1\dbch\af31505\loch\f1 t_int64, t_uint64\tab \tab \tab long long, _int64 (system specific) +\par \tab \hich\af1\dbch\af31505\loch\f1 t_int64, t_uint64\tab \tab \tab long long, _int64\hich\af1\dbch\af31505\loch\f1 (system specific) \par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab \tab \tab simulated address, uint32 or t_uint64 -\par \tab \hich\af1\dbch\af31505\loch\f1 t_value\tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 simulated value, uint32 or t_uint64 +\par \tab \hich\af1\dbch\af31505\loch\f1 t_value\tab \tab \tab \tab simulated value, uint32 or t_uint64 \par \tab \hich\af1\dbch\af31505\loch\f1 t_svalue\tab \tab \tab simulated signed value, int32 or t_int64 \par \tab \hich\af1\dbch\af31505\loch\f1 t_mtrec\tab \tab \tab \tab mag tape record length, uint32 \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab \tab \tab status code, int -\par \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab \tab \tab true/false value, int +\par \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab \tab \tab true/\hich\af1\dbch\af31505\loch\f1 false value, int \par -\par \hich\af1\dbch\af31505\loch\f1 [The inconsistency in naming t_int64 and t_uint64 is due to\hich\af1\dbch\af31505\loch\f1 Microsoft VC++, which uses int64 as a structure name member in the master Windows definitions file.] +\par \hich\af1\dbch\af31505\loch\f1 [The inconsistency in naming t_int64 and t_uint64 is due to Microsoft VC++, which uses int64 as a structure name member in the master Windows definitions file.] \par \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 In addition, SIMH defines structures for each of its major data elements: @@ -603,46 +840,46 @@ pport (at least) 32-bit data types (64-bit data types for the PDP-10 and other l \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 command definition structure \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEBTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 debug table entry structure \par -\par {\*\bkmkstart _Toc347546201}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355609}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM Organization{\*\bkmkend _Toc347546201} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM Organizatio\hich\af1\dbch\af31505\loch\f1 n{\*\bkmkend _Toc356355609} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 A virtual machine (VM) is a collection of devices bound toget\hich\af1\dbch\af31505\loch\f1 -her through their internal logic. Each device is named and corresponds more or less to a hunk of hardware on the real machine; for example: +\par \hich\af1\dbch\af31505\loch\f1 A virtual machine (VM) is a collection of devices bound together through their internal logic. Each device is named and corresponds more or less to a hunk of hardware on the real machine; for example: \par \par \tab \hich\af1\dbch\af31505\loch\f1 VM device\tab \tab \tab Real machine hardware \par \par \tab \hich\af1\dbch\af31505\loch\f1 CPU\tab \tab \tab \tab central processor and main memory -\par \tab \hich\af1\dbch\af31505\loch\f1 PTR\tab \tab \tab \tab paper tape reader controller\hich\af1\dbch\af31505\loch\f1 and paper tape reader +\par \tab \hich\af1\dbch\af31505\loch\f1 PTR\tab \tab \tab \tab paper tape reader controller and paper tape reader \par \tab \hich\af1\dbch\af31505\loch\f1 TTI\tab \tab \tab \tab console keyboard \par \tab \hich\af1\dbch\af31505\loch\f1 TTO\tab \tab \tab \tab console output \par \tab \hich\af1\dbch\af31505\loch\f1 DKP\tab \tab \tab \tab disk pack controller and drives \par -\par \hich\af1\dbch\af31505\loch\f1 There may be more than one device per physical hardware entity, as for the console; but for each user-accessible device there must be at least o\hich\af1\dbch\af31505\loch\f1 -ne. One of these devices will have the pre-eminent responsibility for directing simulated operations. Normally, this is the CPU, but it could be a higher-level entity, such as a bus master. +\par \hich\af1\dbch\af31505\loch\f1 There may be more than one device per physical hardware entity, as \hich\af1\dbch\af31505\loch\f1 +for the console; but for each user-accessible device there must be at least one. One of these devices will have the pre-eminent responsibility for directing simulated operations. Normally, this is the CPU, but it could be a higher-level entity, such as +\hich\af1\dbch\af31505\loch\f1 a\hich\af1\dbch\af31505\loch\f1 bus master. \par -\par \hich\af1\dbch\af31505\loch\f1 The VM actually runs as a subroutine of the simulator control p\hich\af1\dbch\af31505\loch\f1 ackage (SCP). It provides a master routine for running simulated programs and other routines and data structures to implement SCP -\hich\f1 \rquote \loch\f1 s command and control functions. The interfaces between a VM and SCP are relatively few: +\par \hich\af1\dbch\af31505\loch\f1 The VM actually runs as a subroutine of the simulator control package (SCP). It provides a master routine for running simulated programs and other routines and data structures to implement SCP\hich\f1 \rquote \loch\f1 +s command and control functions. The interfaces\hich\af1\dbch\af31505\loch\f1 between a VM and SCP are relatively few: \par \par \tab \hich\af1\dbch\af31505\loch\f1 Interface\tab \tab \tab Function \par -\par \tab \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_n\hich\af1\dbch\af31505\loch\f1 ame[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab -\hich\af1\dbch\af31505\loch\f1 simulator name string +\par \tab \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_name[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 simulator name string + \par \tab \hich\af1\dbch\af31505\loch\f1 REG *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_pc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to simulated program counter \par \tab \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 maximum number of words in an instruction \par \tab \hich\af1\dbch\af31505\loch\f1 DEVICE *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 table of pointers to simulated devices, NULL terminated -\par \tab \hich\af1\dbch\af31505\loch\f1 char *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_messages[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 table of p -\hich\af1\dbch\af31505\loch\f1 ointers to error messages +\par \tab \hich\af1\dbch\af31505\loch\f1 char *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_messages[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 +table of pointers to error messages \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 (\'85\loch\f1 )\tab \tab binary loader subroutine \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_inst}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (void)\tab \tab instruction execution subroutine \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 (\'85\loch\f1 )\tab \tab -symbolic instruction parse subroutine +\hich\af1\dbch\af31505\loch\f1 symbolic instruction parse subroutine \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 (\'85\loch\f1 )\tab \tab symbolic instruction print subroutine \par @@ -650,35 +887,36 @@ symbolic instruction print subroutine \par \par \tab \hich\af1\dbch\af31505\loch\f1 Interface\tab \tab \tab \tab Function \par -\par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ) (void)\tab \tab -pointer to once-only initialization routine for VM +\par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim\hich\af1\dbch\af31505\loch\f1 _vm_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +) (void)\tab \tab pointer to once-only initialization routine for VM \par \tab \hich\af1\dbch\af31505\loch\f1 t_addr (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 ) -\tab \hich\af1\dbch\af31505\loch\f1 pointer to address parsing routine +\tab pointer to address parsing routine \par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 ) \tab pointer to address output routine \par \tab \hich\af1\dbch\af31505\loch\f1 char (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 *sim_vm_read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 )\tab -\tab pointer to command input routine +\tab pointer to command input ro\hich\af1\dbch\af31505\loch\f1 utine \par \tab \hich\af1\dbch\af31505\loch\f1 void (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_post}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 ) (\'85\loch\f1 )\tab \tab pointer to command post-processing routine -\par \tab \hich\af1\dbch\af31505\loch\f1 CTAB }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 *sim_vm_cmd}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 pointe -\hich\af1\dbch\af31505\loch\f1 r to simulator-specific command table +\par \tab \hich\af1\dbch\af31505\loch\f1 CTAB }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 *sim_vm_cmd}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 +pointer to simulator-specific command table \par \par \hich\af1\dbch\af31505\loch\f1 There is no required organization for VM code. The following convention has been used so far. Let name be the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 -\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 of the real system (i1401 for the IBM 1401; i1620 for the IBM 1620; pdp1 for the PDP-1; pdp18b for t\hich\af1\dbch\af31505\loch\f1 he other 18-bit PDP\hich\f1 \rquote \loch\f1 -s; pdp8 for the PDP-8; pdp11 for the PDP-11; nova for Nova; hp2100 for the HP 21XX; h316 for the Honeywell 315/516; gri for the GRI-909; pdp10 for the PDP-10; vax for the VAX; sds for the SDS-940): +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 of the real system (i1401 for the IBM 1401; i1620 for the IBM 1620; pdp1 for the PDP-1; pdp18b for the other 18-bit PDP\hich\f1 \rquote \loch\f1 +s; pdp8 for the PDP-8; pdp11 for the PDP-11; nova for Nova; hp2100 for the HP 21XX; h316 for the Honeywell 315/516; gri for the GRI-90\hich\af1\dbch\af31505\loch\f1 9\hich\af1\dbch\af31505\loch\f1 +; pdp10 for the PDP-10; vax for the VAX; sds for the SDS-940): \par \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 .h contains definitions for th\hich\af1\dbch\af31505\loch\f1 e particular simulator +\hich\af1\dbch\af31505\loch\f1 .h contains definitions for the particular simulator \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 _sys.c contains all the SCP interfaces except the instruction simulator \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 _cpu.c contains the instruction simulator and CPU data structures +\hich\af1\dbch\af31505\loch\f1 _cpu.c contains the instruction simulator and \hich\af1\dbch\af31505\loch\f1 CPU data structures \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 _stddev.c contains the peripherals which were standard with the real syste\hich\af1\dbch\af31505\loch\f1 m. +\hich\af1\dbch\af31505\loch\f1 _stddev.c contains the peripherals which were standard with the real system. \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \ai\af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls2\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls2\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 _lp.c contains the line printer. @@ -690,23 +928,24 @@ s; pdp8 for the PDP-8; pdp11 for the PDP-11; nova for Nova; hp2100 for the HP 21 \par \par \tab \hich\af1\dbch\af31505\loch\f1 Source module\tab \tab header file\tab \tab module \par -\par \tab \hich\af1\dbch\af31505\loch\f1 scp.c\tab \tab \tab scp.h\tab \tab \tab control\hich\af1\dbch\af31505\loch\f1 package +\par \tab \hich\af1\dbch\af31505\loch\f1 scp.c\tab \tab \tab scp.h\tab \tab \tab control package \par \tab \hich\af1\dbch\af31505\loch\f1 sim_console.c\tab \tab sim_console.h\tab \tab terminal I/O library \par \tab \hich\af1\dbch\af31505\loch\f1 sim_fio.c\tab \tab sim_fio.h\tab \tab file I/O library -\par \tab \hich\af1\dbch\af31505\loch\f1 sim_timer.c\tab \tab sim_timer.h\tab \tab timer library +\par \tab \hich\af1\dbch\af31505\loch\f1 sim_timer\hich\af1\dbch\af31505\loch\f1 .c\tab \tab sim_timer.h\tab \tab timer library \par \tab \hich\af1\dbch\af31505\loch\f1 sim_sock.c\tab \tab sim_sock.h\tab \tab socket I/O library \par \tab \hich\af1\dbch\af31505\loch\f1 sim_ether.c\tab \tab sim_ether.h\tab \tab Ethernet I/O library -\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid399520 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 sim_serial.c\tab \tab sim_ser\hich\af1\dbch\af31505\loch\f1 ial.h\tab -\tab Serial Port I/O library +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid399520 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 sim_serial.c\tab \tab sim_serial.h\tab \tab Serial Port I/O library + \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 sim_tmxr.c\tab \tab sim_tmxr.h\tab \tab terminal multiplexer simulation library -\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid399520 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 sim_disk.c\tab \tab sim_disk.h\tab \tab disk simulation library +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid399520 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 sim_disk.c\tab \tab si\hich\af1\dbch\af31505\loch\f1 m_disk.h\tab \tab +disk simulation library \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 sim_tape.c\tab \tab sim_tape.h\tab \tab magtape simulation library -\par {\*\bkmkstart _Toc347546202}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355610}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CPU Organization{\*\bkmkend _Toc347546202} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CPU Organization{\*\bkmkend _Toc356355610} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 Most CPU\hich\f1 \rquote \hich\af1\dbch\af31505\loch\f1 s perform at least the following functions: +\par \hich\af1\dbch\af31505\loch\f1 Most CPU\hich\f1 \rquote \loch\f1 s perform at least the following functions: \par \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Time keeping @@ -715,71 +954,72 @@ s; pdp8 for the PDP-8; pdp11 for the PDP-11; nova for Nova; hp2100 for the HP 21 \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Address decoding \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 -\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Execution of non-I/O instructions +\pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Execu\hich\af1\dbch\af31505\loch\f1 tion of non-I/O instructions \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 I/O command processing \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls3\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls3\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Interrupt processing \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 Instruction execution is actually the least complicated part of\hich\af1\dbch\af31505\loch\f1 the design; memory and I/O organization should be tackled first. -\par {\*\bkmkstart _Toc347546203}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par \hich\af1\dbch\af31505\loch\f1 Instruction execution is actually the least complicated part of the design; memory and I/O organization should be tackled first. +\par {\*\bkmkstart _Toc356355611}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Time Base{\*\bkmkend _Toc347546203} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Time Base{\*\bkmkend _Toc356355611} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 In order to simulate asynchronous events, such as I/O completion, the VM must define and keep a time base. This can be accurate (for example, nano\hich\af1\dbch\af31505\loch\f1 -seconds of execution) or arbitrary (for example, number of instructions executed), but it must be used consistently throughout the VM. All existing VM\hich\f1 \rquote \loch\f1 s count time in instructions. +\par \hich\af1\dbch\af31505\loch\f1 +In order to simulate asynchronous events, such as I/O completion, the VM must define and keep a time base. This can be accurate (for example, nanoseconds of execution) or arbitrary (for example, number of instructions executed), but it must be used consi +\hich\af1\dbch\af31505\loch\f1 s\hich\af1\dbch\af31505\loch\f1 tently throughout the VM. All existing VM\hich\f1 \rquote \loch\f1 s count time in instructions. \par \par \hich\af1\dbch\af31505\loch\f1 The CPU is responsible for counting down the event counter }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and calling the asynchronous event controller }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . SCP does the record keeping for timing. -\par {\*\bkmkstart _Toc347546204}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355612}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Step Function{\*\bkmkend _Toc347546204} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Step Function{\*\bkmkend _Toc356355612} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 SCP implements a stepping function using the step command. STEP counts down a specified number of tim\hich\af1\dbch\af31505\loch\f1 -e units (as described in section 3.1.1) and then stops simulation. The VM can override the STEP command\hich\f1 \rquote \loch\f1 s counts by calling routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -sim_cancel_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 : +\par \hich\af1\dbch\af31505\loch\f1 SCP implements a stepping function using the step command. STEP counts down a specified number of time units (as described in section 3.1.1) and then stops simulation. The VM can override the STEP command\hich\f1 \rquote +\loch\f1 s coun\hich\af1\dbch\af31505\loch\f1 ts by calling routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_cancel_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 : + \par \par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls25\adjustright\rin0\lin720\itap0 { \rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat sim_cancel_step (void) \hich\f1 \endash \loch\f1 cancel STEP count down. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 The VM can then inspect variable }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to s -\hich\af1\dbch\af31505\loch\f1 ee if a STEP command is in progress. If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - is non-zero, it represents the number of steps to execute. The VM can count down }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 using its own counting method, such as cycles, instructions, or memory references. -\par {\*\bkmkstart _Toc347546205}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par \hich\af1\dbch\af31505\loch\f1 The VM can then inspect variable }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + to see if a STEP command is in progress. If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is non-zero, it represents the number of steps to execute. T\hich\af1\dbch\af31505\loch\f1 he VM can count down }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_step}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 using its own counting method, such as cycles, instructions, or memory references. +\par {\*\bkmkstart _Toc356355613}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Organi\hich\af1\dbch\af31505\loch\f1 zation{\*\bkmkend _Toc347546205} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Organization{\*\bkmkend _Toc356355613} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 -The criterion for memory layout is very simple: use the SIMH data type that is as large as (or if necessary, larger than), the word length of the real machine. Note that the criterion is word length, not addressability: the PDP-11 has -\hich\af1\dbch\af31505\loch\f1 - byte addressable memory, but it is a 16-bit machine, and its memory is defined as uint16 M[]. It may seem tempting to define memory as a union of int8 and int16 data types, but this would make the resulting VM endian-dependent. Instead, the VM should b -\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 based on the underlying word size of the real machine, and byte manipulation should be done explicitly. Examples: +\par \hich\af1\dbch\af31505\loch\f1 The criterion for memory layout is very simple: use the SIMH data type that is as large as\hich\af1\dbch\af31505\loch\f1 + (or if necessary, larger than), the word length of the real machine. Note that the criterion is word length, not addressability: the PDP-11 has byte addressable memory, but it is a 16-bit machine, and its memory is defined as uint16 M[]. It may seem te +\hich\af1\dbch\af31505\loch\f1 m\hich\af1\dbch\af31505\loch\f1 +pting to define memory as a union of int8 and int16 data types, but this would make the resulting VM endian-dependent. Instead, the VM should be based on the underlying word size of the real machine, and byte manipulation should be done explicitly. Exam +\hich\af1\dbch\af31505\loch\f1 p\hich\af1\dbch\af31505\loch\f1 les: \par \par \tab \hich\af1\dbch\af31505\loch\f1 Simulator\tab \tab memory size\tab \tab memory declaration \par \par \tab \hich\af1\dbch\af31505\loch\f1 IBM 1620\tab \tab 5-bit\tab \tab \tab uint8 \par \tab \hich\af1\dbch\af31505\loch\f1 IBM 1401\tab \tab 7-bit\tab \tab \tab uint8 \par \tab \hich\af1\dbch\af31505\loch\f1 PDP-8\tab \tab \tab 12-bit\tab \tab \tab uint16 -\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-11, Nova\tab \tab 16-b\hich\af1\dbch\af31505\loch\f1 it\tab \tab \tab uint16 +\par \tab \hich\af1\dbch\af31505\loch\f1 PDP-11, Nova\tab \tab 16-bit\tab \tab \tab uint16 \par \tab \hich\af1\dbch\af31505\loch\f1 PDP-1\tab \tab \tab 18-bit\tab \tab \tab uint32 \par \tab \hich\af1\dbch\af31505\loch\f1 VAX\tab \tab \tab 32-bit\tab \tab \tab uint32 \par \tab \hich\af1\dbch\af31505\loch\f1 PDP-10, IBM 7094\tab 36-bit\tab \tab \tab t_uint64 -\par {\*\bkmkstart _Toc347546206}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355614}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Interrupt Organization{\*\bkmkend _Toc347546206} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Interrupt Organization{\*\bkmkend _Toc356355614} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 The design of the VM\hich\f1 \rquote \loch\f1 s interrupt structure is a complex interaction between efficiency and fidelity to t\hich\af1\dbch\af31505\loch\f1 he hardware. If the VM\hich\f1 \rquote \loch\f1 -s interrupt structure is too abstract, interrupt driven software may not run. On the other hand, if it follows the hardware too literally, it may significantly reduce simulation speed. One rule I can offer is to minimize the fetc -\hich\af1\dbch\af31505\loch\f1 h\hich\af1\dbch\af31505\loch\f1 --phase cost of interrupts, even if this complicates the (much less frequent) evaluation of the interrupt system following an I/O operation or asynchronous event. Another is not to over-generalize; even if the real hardware could support 64 or 256 interru -\hich\af1\dbch\af31505\loch\f1 p\hich\af1\dbch\af31505\loch\f1 ting devices, the simulators will be running much smaller configurations. I\hich\f1 \rquote \loch\f1 ll start with a simple interrupt structure and then offer suggestions for generalization. - +\par \hich\af1\dbch\af31505\loch\f1 The design of the VM\hich\f1 \rquote \loch\f1 s interrupt structure is a complex interaction between efficiency and fidelity to the hardware. If the VM\hich\f1 \rquote \loch\f1 +s interrupt structure is too abstract, interrupt driven software may not run. On the o\hich\af1\dbch\af31505\loch\f1 +ther hand, if it follows the hardware too literally, it may significantly reduce simulation speed. One rule I can offer is to minimize the fetch-phase cost of interrupts, even if this complicates the (much less frequent) evaluation of the interrupt syste +\hich\af1\dbch\af31505\loch\f1 m\hich\af1\dbch\af31505\loch\f1 + following an I/O operation or asynchronous event. Another is not to over-generalize; even if the real hardware could support 64 or 256 interrupting devices, the simulators will be running much smaller configurations. I\hich\f1 \rquote \loch\f1 +ll start with a simple interrupt \hich\af1\dbch\af31505\loch\f1 s\hich\af1\dbch\af31505\loch\f1 tructure and then offer suggestions for generalization. \par \par \hich\af1\dbch\af31505\loch\f1 In the simplest structure, interrupt requests correspond to device flags and are kept in\hich\af1\dbch\af31505\loch\f1 an interrupt request variable, with one flag per bit. The fetch-phase evaluation of interrupts consists of two steps: are interrupts enabled, and is there an interrupt outstanding? If all the interrupt requests are kept as single-bit flags in a variabl @@ -815,9 +1055,9 @@ ending flag is created, and it is evaluated by subroutine call whenever a change \par \hich\af1\dbch\af31505\loch\f1 If required for interrupt processing, the highest priority interrupting device can be determined by scanning the interrupt request variable from high priority to low until a set bit is found. The bit position can then be back-mapped through a tabl \hich\af1\dbch\af31505\loch\f1 e to determine the address or interrupt vector of the interrupting device. -\par {\*\bkmkstart _Toc347546207}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355615}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 I/O Dispatching{\*\bkmkend _Toc347546207} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 I/O Dispatching{\*\bkmkend _Toc356355615} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 I/O dispatching consists of four steps: @@ -838,9 +1078,9 @@ If required for interrupt processing, the highest priority interrupting device c zed, the CPU must locate the device subroutine. The simplest way is a large switch statement with hardwired subroutine calls. More modular is to call through a dispatch table, with NULL entries representing non-existent devices; this also simplifies supp \hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 rt for modifiable device addresses and configurable devices. Before calling the device routine, the CPU usually breaks down the I/O command into standard fields. This simplifies writing the peripheral simulator. -\par {\*\bkmkstart _Toc347546208}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.6\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355616}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.1.6\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction Execution{\*\bkmkend _Toc347546208} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction Execution{\*\bkmkend _Toc356355616} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 Instruction execution is the responsibility of VM subroutine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 @@ -889,9 +1129,9 @@ In general, code should reflect the hardware being simulated. This is usually s \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls5\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls5\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The VM should provide some debugging aids. The existing CPU\hich\f1 \rquote \loch\f1 s all provide multiple instruction breakpoints, a PC change queue, error stops on invalid instructions or operations, and symbolic examination and modification of memory. -\par {\*\bkmkstart _Toc347546209}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355617}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Periphe\hich\af1\dbch\af31505\loch\f1 ral Device Organization{\*\bkmkend _Toc347546209} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Periphe\hich\af1\dbch\af31505\loch\f1 ral Device Organization{\*\bkmkend _Toc356355617} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 The basic elements of a VM are devices, each corresponding roughly to a real chunk of hardware. A device consists of register-based state and one or more units. Thus, a multi-drive disk subsystem is a single device ( @@ -926,9 +1166,9 @@ ng and device I/O. Except for the console, all I/O devices are simulated as hos \par \hich\af1\dbch\af31505\loch\f1 Command decoding is fairly obvious. At least one section of the peripheral code module will be devoted to processing directives issued by the CPU. Typically, the command decoder will be responsible for register and flag manipulation, and for issuing or \hich\af1\dbch\af31505\loch\f1 c\hich\af1\dbch\af31505\loch\f1 anceling I/O requests. The former is easy, but the later requires a thorough understanding of device timing. -\par {\*\bkmkstart _Toc347546210}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355618}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Timing{\*\bkmkend _Toc347546210} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Timing{\*\bkmkend _Toc356355618} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 The principal problem in I/O device simulation is imitating asynchronous operations in a sequential\hich\af1\dbch\af31505\loch\f1 @@ -1003,9 +1243,9 @@ oves all timed out units from the active queue and calls the appropriate device \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls7\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . This variable counts down the first outstanding timed event. If there are no timed events outstanding, SCP counts \hich\af1\dbch\af31505\loch\f1 \hich\f1 down a \'93\loch\f1 \hich\f1 null interval\'94\loch\f1 of 10,000 time units. -\par {\*\bkmkstart _Toc347546211}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355619}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Clock Calibration{\*\bkmkend _Toc347546211} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Clock Calibration{\*\bkmkend _Toc356355619} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 The timing mechanism described in the previous section is approximate. Devices, such as real-time clocks, which track wall time will be inaccurate. SCP provid\hich\af1\dbch\af31505\loch\f1 @@ -1035,46 +1275,47 @@ es routines to synchronize multiple simulated clocks (to a maximum of 8) to wall \par \par \tab \hich\af1\dbch\af31505\loch\f1 sim_activate (&clk_unit, sim_rtcb_calb (clk_ticks_per_second, clkno); \par -\par \hich\af1\dbch\af31505\loch\f1 The real-time clock is usually simulated clock 0; other clocks are used for polling asynchronous multiplexers or intervals timers. -\par {\*\bkmkstart _Toc347546212}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par \hich\af1\dbch\af31505\loch\f1 The real-time clock is usually simulated clock 0; other clocks are used for \hich\af1\dbch\af31505\loch\f1 polling asynchronous multiplexers or intervals timers. +\par {\*\bkmkstart _Toc356355620}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Idling{\*\bkmkend _Toc347546212} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Idling{\*\bkmkend _Toc356355620} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 If a VM implements a free-running, calibrated clock of 100Hz or less, then the VM can\hich\af1\dbch\af31505\loch\f1 - also implement idling. Idling is a way of pausing simulation when no real work is happening, without losing clock calibration. The VM must detect when it is idle; it can then inform the host of this situation by calling }{\rtlch\fcs1 \ab\af1 -\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 : +\par \hich\af1\dbch\af31505\loch\f1 If a VM implements a free-running, calibrated clock of 100Hz or less, then the VM can also implement idling. Idling is a way of pausing simulation when no real \hich\af1\dbch\af31505\loch\f1 +work is happening, without losing clock calibration. The VM must detect when it is idle; it can then inform the host of this situation by calling }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 : \par \par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls26\adjustright\rin0\lin720\itap0 { \rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 (int32 clk, t_bool one_tick) \hich\f1 \endash \loch\f1 attempt to idle the VM until the next scheduled I/O event, using simulated clock }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -clk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 as the time base, and decrement }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 by an appropriate number of cycles. If a calibrated timer is not available, or the time until\hich\af1\dbch\af31505\loch\f1 the next event is less than 1ms, decrement }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\hich\af1\dbch\af31505\loch\f1 (int32 clk, t_bool one_tick) \hich\f1 \endash \loch\f1 attempt to idle the VM until the next scheduled I\hich\af1\dbch\af31505\loch\f1 /O event, using simulated clock }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 clk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 as the time base, and decrement }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 by an appropriate number of cycles. If a calibrated timer is not available, or the time until the next event is less than 1ms, decrement }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_interval}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 by 1 if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 one_tick}{ -\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is TRUE; otherwise, leave sim_interval unchanged. +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is TRUE\hich\af1\dbch\af31505\loch\f1 ; otherwise, leave sim_interval unchanged. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 returns TRUE if the VM actually idled, FALSE if it did not. \par -\par \hich\af1\dbch\af31505\loch\f1 Because idling and throttling are mutually exclusive, the VM \hich\af1\dbch\af31505\loch\f1 must inform SCP when idling is turned on or off: +\par \hich\af1\dbch\af31505\loch\f1 Because idling and throttling are mutually exclusive, the VM must inform SCP when idling is turned on or off: \par \par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault\faauto\ls26\adjustright\rin0\lin720\itap0 { \rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_set_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 informs SCP that idling is enabled. +\hich\af1\dbch\af31505\loch\f1 (UNIT *up\hich\af1\dbch\af31505\loch\f1 tr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 informs SCP that idling is enabled. \par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 t_stat}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - sim_clr_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 informs SCP that idling is\hich\af1\dbch\af31505\loch\f1 disabled. + sim_clr_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 informs SCP that idling is disabled. \par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}\hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -sim_show_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1 displays whether idling is enabled or disabled, as seen by SCP. -\par {\*\bkmkstart _Toc347546213}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +sim_show_idle}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 displays whether idling is enabled or disabled, as seen by SCP. + +\par {\*\bkmkstart _Toc356355621}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.2.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data I/O{\*\bkmkend _Toc347546213} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data I/O{\*\bkmkend _Toc356355621} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 For most devices, timing is half the battle (for clocks it is the en\hich\af1\dbch\af31505\loch\f1 -tire war); the other half is I/O. Some devices are simulated on real hardware (for example, Ethernet controllers). Most I/O devices are simulated as files on the host file system in little-endian format. SCP provides facilities for associating files wi -\hich\af1\dbch\af31505\loch\f1 t\hich\af1\dbch\af31505\loch\f1 h units (ATTACH command) and for reading and writing data from and to devices in a endian- and size-independent way. +\par \hich\af1\dbch\af31505\loch\f1 For most devices, timing is half the battle (for clocks it is the entire war); the other half is I/O. Some devices are simulated on real hardware (f\hich\af1\dbch\af31505\loch\f1 +or example, Ethernet controllers). Most I/O devices are simulated as files on the host file system in little-endian format. SCP provides facilities for associating files with units (ATTACH command) and for reading and writing data from and to devices in +\hich\af1\dbch\af31505\loch\f1 \hich\af1\dbch\af31505\loch\f1 a endian- and size-independent way. \par -\par \hich\af1\dbch\af31505\loch\f1 For most devices, the VM designer does not have to be concerned about the formatting of simulated device files. I/O occurs in 1, 2, 4, or\hich\af1\dbch\af31505\loch\f1 - 8 byte quantities; SCP automatically chooses the correct data size and corrects for byte ordering. Specific issues: +\par \hich\af1\dbch\af31505\loch\f1 For most devices, the VM designer does not have to be concerned about the formatting of simulated device files. I/O occurs in 1, 2, 4, or 8 byte quantities; SCP automatically chooses the correct data size and corrects +\hich\af1\dbch\af31505\loch\f1 for byte ordering. Specific issues: \par \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls8\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls8\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 @@ -1140,28 +1381,28 @@ SIMH provides capabilities to access files >2GB (the int32 position limit). If \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls10\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls10\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_putchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (int32 char). This routine types the specified ASCII character to the console. If the console is attached to a Telnet connection, and the connection is lost, the routine returns SCPE_LOST. + (int32 char). This routine types the specified ASCII character to the console. If the console is attached to a Telnet connection, and the connection is lost, the routine \hich\af1\dbch\af31505\loch\f1 returns SCPE_LOST. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault{\*\pn \pnlvlcont\ilvl0\ls0\pnrnot0\pndec }\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs20 \ltrch\fcs0 \f3\fs20\insrsid4550150 \loch\af3\dbch\af31505\hich\f3 \'b7\tab}}\pard \ltrpar\ql \fi-360\li720\ri0\widctlpar\jclisttab\tx720\wrapdefault{\*\pn \pnlvlblt\ilvl0\ls10\pnrnot0 \pnf3\pnstart1\pnindent360\pnsp120\pnhang {\pntxtb \'b7}}\faauto\ls10\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_putchar_s}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (int32 char). This routine outputs the specified ASCII character to the console. If the console is attached to a Telnet connection, and the connection is lost, the routine returns SCPE_LOST; if the connection is backlogged, the routine returns SCPE_STA -\hich\af1\dbch\af31505\loch\f1 L\hich\af1\dbch\af31505\loch\f1 L. + (int32 char). This routine outputs the specified ASCII character to the console. If the console is attached to a Telnet connection, and the connection is lost, the routine returns SCPE_LOST; if the connection i\hich\af1\dbch\af31505\loch\f1 +s backlogged, the routine returns SCPE_STALL. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par {\*\bkmkstart _Toc347546214}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355622}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data Structures{\*\bkmkend _Toc347546214} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Data Structures{\*\bkmkend _Toc356355622} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 The devices, units, and registers that make up a VM are formally described through a set of data structures which interface the VM to the control portions of SCP. The devices themselves are pointed to by t -\hich\af1\dbch\af31505\loch\f1 he device list array }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -. Within a device, both units and registers are allocated contiguously as arrays of structures. In addition, many devices allow the user to set or clear options via a modifications table. +\par \hich\af1\dbch\af31505\loch\f1 The devices, units, and registers that make up a VM are formally described through a set of data structures which interface the VM to the control portions of SCP. \hich\af1\dbch\af31505\loch\f1 + The devices themselves are pointed to by the device list array }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +. Within a device, both units and registers are allocated contiguously as arrays of structures. In addition, many devices allow the user to set or clear options via a modificati\hich\af1\dbch\af31505\loch\f1 ons table. \par -\par \hich\af1\dbch\af31505\loch\f1 Note that a device must always \hich\af1\dbch\af31505\loch\f1 \hich\f1 -have at least one unit, even if that unit is not needed for simulation purposes. A device must always point to a valid register table, but the register table can consist of just the \'93\loch\f1 \hich\f1 end of table\'94\loch\f1 entry. -\par {\*\bkmkstart _Toc347546215}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par \hich\af1\dbch\af31505\loch\f1 \hich\f1 Note that a device must always have at least one unit, even if that unit is not needed for simulation purposes. A device must always point to a valid register table, but the register table can consist of just the +\'93\loch\f1 \hich\f1 end of table\'94\loch\f1 entry. +\par {\*\bkmkstart _Toc356355623}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_device Structure{\*\bkmkend _Toc347546215} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_device Structure{\*\bkmkend _Toc356355623} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 Devices are defined by the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_device}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure (typedef @@ -1171,19 +1412,19 @@ have at least one unit, even if that unit is not needed for simulation purposes. \par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *name;\tab \tab \tab \tab /* name */ \par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_unit \tab *units;\tab \tab \tab \tab /* units */ \par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_reg\tab *registers;\tab \tab \tab /* registers */ -\par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_mtab\tab *modifiers;\tab \tab \tab /* modifiers */ -\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab \hich\af1\dbch\af31505\loch\f1 numunits;\tab \tab \tab /* #units */ +\par \tab \hich\af1\dbch\af31505\loch\f1 struct si\hich\af1\dbch\af31505\loch\f1 m_mtab\tab *modifiers;\tab \tab \tab /* modifiers */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab numunits;\tab \tab \tab /* #units */ \par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab aradix;\tab \tab \tab \tab /* address radix */ \par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab awidth;\tab \tab \tab \tab /* address width */ \par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab aincr;\tab \tab \tab \tab /* addr increment */ \par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dradix;\tab \tab \tab \tab /* data radix */ -\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dwidth;\tab \tab \tab \tab /* data width */ -\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*examine)();\tab \tab \tab /* examine\hich\af1\dbch\af31505\loch\f1 routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab dwidth;\tab \tab \tab \tab /* data w\hich\af1\dbch\af31505\loch\f1 idth */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*examine)();\tab \tab \tab /* examine routine */ \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*deposit)();\tab \tab \tab /* deposit routine */ \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*reset)();\tab \tab \tab /* reset routine */ \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*boot)();\tab \tab \tab /* boot routine */ \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*attach)();\tab \tab \tab /* attach routine */ -\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*detach)();\tab \tab \tab /* detach routine */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*detach)();\tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* detach routine */ \par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *ctxt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 ;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /}{ \rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 * context */ \par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */ @@ -1192,9 +1433,9 @@ have at least one unit, even if that unit is not needed for simulation purposes. * debug flag names */ \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*msize)();\tab \tab \tab /* memory size change */ \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid399520 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *lname;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 -\b\f1\insrsid399520 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 logical name */ -\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*help)();}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 hel -\hich\af1\dbch\af31505\loch\f1 p routine */ +\b\f1\insrsid399520 \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 logic\hich\af1\dbch\af31505\loch\f1 al name */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*help)();}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 + help routine */ \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*attach_help)();}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /*}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 attach help routine */ \par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *help_ctxt;}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 @@ -1206,14 +1447,14 @@ have at least one unit, even if that unit is not needed for simulation purposes. \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 name}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 device name, string of all capital alphanumeric characters. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 units}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 -\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures,\hich\af1\dbch\af31505\loch\f1 or NULL if none. +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures, or NULL if none. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 registers}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures, or NULL if none. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 modifiers}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures, or NULL if none. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 numunits}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \tab number of units in this device. -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aradix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 radix for input and display of device addresses, 2 to -\hich\af1\dbch\af31505\loch\f1 16 inclusive. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aradix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 radix for inp\hich\af1\dbch\af31505\loch\f1 +ut and display of device addresses, 2 to 16 inclusive. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of a device address, 1 to 64 inclusive. \par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 increment between device addresses, normally 1; however, byte addressed devices with 16-bit words specify 2, with 32-bit words 4. @@ -1222,8 +1463,8 @@ have at least one unit, even if that unit is not needed for simulation purposes. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dwidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of device data, 1 to 64 inclusive. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 examine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of special device data read routine, or NULL if none is required. -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 deposit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of special device data write routine, -\hich\af1\dbch\af31505\loch\f1 or NULL if none is required. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 deposit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of special device data write \hich\af1\dbch\af31505\loch\f1 +routine, or NULL if none is required. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reset}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of device reset routine, or NULL if none is required. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 boot}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of device bootstrap routine, or NULL if none is required. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of special device attach routine, or NULL if none is required. @@ -1234,25 +1475,25 @@ have at least one unit, even if that unit is not needed for simulation purposes. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 device flags. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debug control flags. -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pointer to array of sim_debtab structures, or -\hich\af1\dbch\af31505\loch\f1 NULL if none. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pointer to array of sim_debtab struct\hich\af1\dbch\af31505\loch\f1 +ures, or NULL if none. \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid399520 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 msize}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of memory size change routine, or NULL if none is required. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 lname\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 pointer to logical name string. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 help}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of help routine, or NULL if none is required. -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 attach_help}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 address of attach help routine\hich\af1\dbch\af31505\loch\f1 -, or NULL if none is required. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 attach_help}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 address of attach help routine, or NULL if none +\hich\af1\dbch\af31505\loch\f1 is required. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 help_ctx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \tab \hich\af1\dbch\af31505\loch\f1 address of device specific context }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14750569 \hich\af1\dbch\af31505\loch\f1 which might be useful while displaying }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 help }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14750569 \par }\pard \ltrpar\ql \li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid14750569 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14750569 \hich\af1\dbch\af31505\loch\f1 for the current device, or NULL if }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid399520 \hich\af1\dbch\af31505\loch\f1 none is required. -\par {\*\bkmkstart _Toc347546216}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355624}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Awidth and Aincr{\*\bkmkend _Toc347546216} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Awidth and Aincr{\*\bkmkend _Toc356355624} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid4550150 \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 field specifies the wi\hich\af1\dbch\af31505\loch\f1 dth of the VM\hich\f1 \rquote \loch\f1 \hich\f1 s fundamental computer \'93\loch\f1 \hich\f1 word\'94\loch\f1 . For example, on the PDP-11, }{\rtlch\fcs1 \ab\af1 +\hich\af1\dbch\af31505\loch\f1 field specifies the width of the VM\hich\f1 \rquote \loch\f1 s f\hich\af1\dbch\af31505\loch\f1 \hich\f1 undamental computer \'93\loch\f1 \hich\f1 word\'94\loch\f1 . For example, on the PDP-11, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is 16b, even though memory is byte-addressable. The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 field specifies how many addressing units comprise the fundamental \'93\loch\f1 \hich\f1 word\'94\loch\f1 . For example, on the PDP-11, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is 2 (\hich\af1\dbch\af31505\loch\f1 @@ -1270,12 +1511,12 @@ have at least one unit, even if that unit is not needed for simulation purposes. }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the fundamental sizes and support unaligned data access in the examine/deposit routines. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 In a byte-addressable VM, SAVE and RESTORE will require (memory_size_bytes / }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 ) iterations to save or restore memory. Thus, it is significantly more efficient to use word-wide rather than byte-wide memory; but requirements for unaligned access can add\hich\af1\dbch\af31505\loch\f1 - significantly to the complexity of the examine and deposit routines. -\par {\*\bkmkstart _Toc347546217}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par \hich\af1\dbch\af31505\loch\f1 In a byte-addressable VM, SAVE and RESTORE will require (memory_size\hich\af1\dbch\af31505\loch\f1 _bytes / }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 aincr}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +) iterations to save or restore memory. Thus, it is significantly more efficient to use word-wide rather than byte-wide memory; but requirements for unaligned access can add significantly to the complexity of the examine and deposit routines. +\par {\*\bkmkstart _Toc356355625}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Flags{\*\bkmkend _Toc347546217} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device Flags{\*\bkmkend _Toc356355625} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 @@ -1283,13 +1524,13 @@ field contains indicators of current device status. SIMH defines }{\rtlch\fcs1 \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag name\tab \tab meaning if set \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DISABLE\tab \tab device \hich\af1\dbch\af31505\loch\f1 can be set enabled or disabled -\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DIS\tab \tab device is currently disabled +\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DISABLE\tab \tab device can be set enabled or disabled +\par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DIS\tab \tab device is currently disable\hich\af1\dbch\af31505\loch\f1 d \par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DYNM\tab \tab device requires call on }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 msize}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 routine to change memory size \par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DEBUG\tab \tab device supports SET DEBUG command \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 -\par \hich\af1\dbch\af31505\loch\f1 The flags field also contains an optional device type specification.\hich\af1\dbch\af31505\loch\f1 One of these may be specified when initializing the flags field: +\par \hich\af1\dbch\af31505\loch\f1 The flags field also contains an optional device type specification. One of these may be specified when initializing the flags field: \par \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \tab \hich\af1\dbch\af31505\loch\f1 DEV_DISK\tab \tab device uses sim_disk library attach \par \tab \hich\af1\dbch\af31505\loch\f1 DEV_TAPE\tab \tab device uses sim_tape library attach @@ -1297,83 +1538,86 @@ field contains indicators of current device status. SIMH defines }{\rtlch\fcs1 \par \tab \hich\af1\dbch\af31505\loch\f1 DEV_ETHER\tab \tab device uses sim_ether library attach \par \tab \hich\af1\dbch\af31505\loch\f1 DEV_DISPLAY\tab \tab device uses sim_video library attach \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 -\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -Starting at bit position DEV_V_UF, the remaining flags are device-specific. Device flags are automatically saved and restored; the device need not supply a register for these bits. -\par {\*\bkmkstart _Toc347546218}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Starting at bit\hich\af1\dbch\af31505\loch\f1 + position DEV_V_UF, the remaining flags are device-specific. Device flags are automatically saved and restored; the device need not supply a register for these bits. +\par {\*\bkmkstart _Toc356355626}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Co\hich\af1\dbch\af31505\loch\f1 ntext{\*\bkmkend _Toc347546218} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Context{\*\bkmkend _Toc356355626} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 The field contains a pointer to a VM-specific device context table, if required. SIMH never accesses this field. The context field allows VM-specific code to walk VM-specific data structures from the }{\rtlch\fcs1 \ab\af1 -\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 root pointer. -\par {\*\bkmkstart _Toc347546219}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par \hich\af1\dbch\af31505\loch\f1 The field contains a pointer to a VM-specific de\hich\af1\dbch\af31505\loch\f1 +vice context table, if required. SIMH never accesses this field. The context field allows VM-specific code to walk VM-specific data structures from the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices }{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 root pointer. +\par {\*\bkmkstart _Toc356355627}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Examine and Deposit Routines{\*\bkmkend _Toc347546219} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Examine and Deposit Routines{\*\bkmkend _Toc356355627} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 For devices which maintain their data sets as host files, SCP implements the examine and deposit da\hich\af1\dbch\af31505\loch\f1 -ta functions. However, devices which maintain their data sets as private state (for example, the CPU) must supply special examine and deposit routines. The calling sequences are: +\par \hich\af1\dbch\af31505\loch\f1 +For devices which maintain their data sets as host files, SCP implements the examine and deposit data functions. However, devices which maintain their data sets as private state (for example, the CPU) must supply special examine and deposit routines. Th +\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 calling sequences are: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 examine_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (t_val *eval_array, t_addr addr, UNIT *uptr, int32 \hich\af1\dbch\af31505\loch\f1 switches) \hich\f1 \endash \loch\f1 Copy }{ -\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 consecutive addresses for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 -\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , starting at }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 -\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , into }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 eval_array}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -. The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 variable has bit set if the n\hich\f1 \rquote \loch\f1 -th letter was specified as a switch to the examine command. +\hich\af1\dbch\af31505\loch\f1 examine_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (t_val *eval_array, t_addr addr, UNIT *uptr, int32 switches) \hich\f1 \endash \loch\f1 Copy }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 consecutive addresses for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , starting at }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , into }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 eval_array}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . The }{\rtlch\fcs1 +\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 variable has bit set if the n\hich\f1 \rquote \loch\f1 th letter was +\hich\af1\dbch\af31505\loch\f1 specified as a switch to the examine command. \par -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 deposit_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (t_val value, t_addr addr, UN -\hich\af1\dbch\af31505\loch\f1 IT *uptr, int32 switches) \hich\f1 \endash \loch\f1 Store the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 deposit_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (t_val value, t_addr addr, UNIT *uptr, int32 switches) \hich\f1 \endash \loch\f1 Store the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 in the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{ \rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 variable is the same as for the examine routine. -\par {\*\bkmkstart _Toc347546220}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355628}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Reset Routine{\*\bkmkend _Toc347546220} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Reset Routine{\*\bkmkend _Toc356355628} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 The reset routine implements the device reset function fo\hich\af1\dbch\af31505\loch\f1 r the RESET, RUN, and BOOT commands. Its calling sequence is: +\par \hich\af1\dbch\af31505\loch\f1 The reset routine implements the device reset function for the RESET, RUN, and BOOT commands. Its calling sequence is: \par \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reset_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (DEVICE *dptr) \hich\f1 \endash \loch\f1 Reset the specified device to its initial state. \par -\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -A typical reset routine clears all device flags and cancels any outstanding timing operations. Switch \loch\af1\dbch\af31505\hich\f1 \endash \loch\f1 p specifies a reset to power-up state. -\par {\*\bkmkstart _Toc347546221}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.6\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 A ty\hich\af1\dbch\af31505\loch\f1 +pical reset routine clears all device flags and cancels any outstanding timing operations. Switch \hich\f1 \endash \loch\f1 p specifies a reset to power-up state. +\par {\*\bkmkstart _Toc356355629}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.6\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Boot Routine{\*\bkmkend _Toc347546221} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Boot Routine{\*\bkmkend _Toc356355629} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 If a device responds to a BOOT command, the boot routine implements the bootstrapping function. Its calling sequence is: +\par \hich\af1\dbch\af31505\loch\f1 If a device responds to a BOOT command, the boot routine implements the\hich\af1\dbch\af31505\loch\f1 bootstrapping function. Its calling sequence is: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 boot_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 unit_num, DEVICE *dp\hich\af1\dbch\af31505\loch\f1 tr) \hich\f1 \endash \loch\f1 Bootstrap unit }{\rtlch\fcs1 \ai\af1 -\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 unit_num}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 on the device }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\hich\af1\dbch\af31505\loch\f1 boot_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 unit_num, DEVICE *dptr) \hich\f1 \endash \loch\f1 Bootstrap unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 unit_num}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 on the device }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 . \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 A typical bootstrap routine copies a bootstrap loader into main memory and sets the PC to the starting address of the loader. SCP then starts simulation at the specified address. -\par {\*\bkmkstart _Toc347546222}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.7\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par \hich\af1\dbch\af31505\loch\f1 A typical bootstrap routine copies\hich\af1\dbch\af31505\loch\f1 a bootstrap loader into main memory and sets the PC to the starting address of the loader. SCP then starts simulation at the specified address. +\par {\*\bkmkstart _Toc356355630}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.7\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Attac\hich\af1\dbch\af31505\loch\f1 h and Detach Routines{\*\bkmkend _Toc347546222} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Attach and Detach Routines{\*\bkmkend _Toc356355630} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 Normally, the ATTACH and DETACH commands are handled by SCP. However, devices which need to pre- or post-process these commands must supply special attach and detach routines. The calling sequences are: +\par \hich\af1\dbch\af31505\loch\f1 Normally, the ATTACH and DETACH commands are handl\hich\af1\dbch\af31505\loch\f1 +ed by SCP. However, devices which need to pre- or post-process these commands must supply special attach and detach routines. The calling sequences are: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 attach_\hich\af1\dbch\af31505\loch\f1 routine }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, char *file) \hich\f1 \endash \loch\f1 Attach the specified }{\rtlch\fcs1 \ai\af1 -\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 file}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{ -\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . -\par \hich\af1\dbch\af31505\loch\f1 Sim_switches contains the command switch; bit SIM_SW_REST indicates that attach is being called by the RESTORE command rather than the ATTACH command. +\hich\af1\dbch\af31505\loch\f1 attach_routine }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, char *file) \hich\f1 \endash \loch\f1 Attach the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 file}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 . +\par \hich\af1\dbch\af31505\loch\f1 Sim_swi\hich\af1\dbch\af31505\loch\f1 tches contains the command switch; bit SIM_SW_REST indicates that attach is being called by the RESTORE command rather than the ATTACH command. \par -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UN\hich\af1\dbch\af31505\loch\f1 -IT *uptr) \hich\f1 \endash \loch\f1 Detach unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash +\loch\f1 Detach unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 In practice, these routines usually invoke the standard SCP routines, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 attach_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 detach_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , respectively. For example, here are special attach and detach routines to update line printer error state: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 t_stat lpt_attach (UNIT *uptr, char *cptr) \{ -\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 t_stat r; +\par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 t_s\hich\af2\dbch\af31505\loch\f2 tat r; \par \hich\af2\dbch\af31505\loch\f2 if ((r = attach_unit (uptr, cptr)) != SCPE_OK) return r; \par \hich\af2\dbch\af31505\loch\f2 lpt_error = 0; \par \hich\af2\dbch\af31505\loch\f2 return SCPE_OK; @@ -1384,50 +1628,50 @@ IT *uptr) \hich\f1 \endash \loch\f1 Detach unit }{\rtlch\fcs1 \ai\af1 \ltrch\fc \par \tab \hich\af2\dbch\af31505\loch\f2 return detach_unit (uptr); \par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \} \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 If the VM specifies an ATTACH \hich\af1\dbch\af31505\loch\f1 -or DETACH routine, SCP bypasses its normal tests before calling the VM routine. Thus, a VM DETACH routine cannot be assured that the unit is actually attached and must test the unit flags if required. +\par \hich\af1\dbch\af31505\loch\f1 If the VM specifies an ATTACH or DETACH routine, SCP bypasses its normal tests\hich\af1\dbch\af31505\loch\f1 + before calling the VM routine. Thus, a VM DETACH routine cannot be assured that the unit is actually attached and must test the unit flags if required. \par -\par \hich\af1\dbch\af31505\loch\f1 SCP executes a DETACH ALL command as part of simulato\hich\af1\dbch\af31505\loch\f1 r exit. Normally, DETACH ALL only calls a unit\hich\f1 \rquote \loch\f1 s detach routine if the unit\hich\f1 \rquote \loch\f1 -s UNIT_ATT flag is set. During simulator exit, the detach routine is also called if the unit is not flagged as attachable (UNIT_ATTABLE is not set). This allows the detach rout\hich\af1\dbch\af31505\loch\f1 i\hich\af1\dbch\af31505\loch\f1 -ne of a non-attachable unit to function as a simulator-specific cleanup routine for the unit, device, or entire simulator. -\par {\*\bkmkstart _Toc347546223}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.8\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par \hich\af1\dbch\af31505\loch\f1 SCP executes a DETACH ALL command as part of simulator exit. Normally, DETACH ALL only calls a unit\hich\f1 \rquote \hich\af1\dbch\af31505\loch\f1 s detach routine if the unit\hich\f1 \rquote \loch\f1 +s UNIT_ATT flag is set. During simulator exit, the detach routine is also called if the unit is not flagged as attachable (UNIT_ATTABLE is not set). This allows the detach routine of a non-attachable unit to function as a si +\hich\af1\dbch\af31505\loch\f1 m\hich\af1\dbch\af31505\loch\f1 ulator-specific cleanup routine for the unit, device, or entire simulator. +\par {\*\bkmkstart _Toc356355631}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.8\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Size Change Routine{\*\bkmkend _Toc347546223} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Memory Size Change Routine{\*\bkmkend _Toc356355631} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 Most units instantiate any memory array at the maximum size possible. Th\hich\af1\dbch\af31505\loch\f1 is allows apparent memory size to be changed by varying the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 Most units instantiate any memory array at the maximum size possible. This allows apparent memory size to be changed by \hich\af1\dbch\af31505\loch\f1 varying the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - field in the unit structure. For some devices (like the VAX CPU), instantiating the maximum memory size would impose a significant resource burden if less memory was actually needed. These\hich\af1\dbch\af31505\loch\f1 - devices must provide a routine, the memory size change routine, for RESTORE to use if memory size must be changed: + field in the unit structure. For some devices (like the VAX CPU), instantiating the maximum memory size would impose a significant resource burden if less memory was actually needed. These devices must provide a routine, the memory size +\hich\af1\dbch\af31505\loch\f1 change routine, for RESTORE to use if memory size must be changed: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 change_mem_size}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 Change the capacity (memory size) of unit }{ \rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . The }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 a\hich\af1\dbch\af31505\loch\f1 nd }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 arguments are included for compatibility with the SET command\hich\f1 \rquote \loch\f1 s validation routine calling sequence. +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + arguments are included for compatibility\hich\af1\dbch\af31505\loch\f1 with the SET command\hich\f1 \rquote \loch\f1 s validation routine calling sequence. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par {\*\bkmkstart _Toc347546224}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.9\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355632}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.1.9\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Debug Controls{\*\bkmkend _Toc347546224} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Debug Controls{\*\bkmkend _Toc356355632} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 Devices can support debug printouts. Debug printouts are controlled by the SET \{NO\}DEBUG command,\hich\af1\dbch\af31505\loch\f1 which specifies where debug output should be printed; and by the SET \{NO\} DEBUG command, which enables or disables individual debug printouts. \par \par \hich\af1\dbch\af31505\loch\f1 If a device supports debug printouts, device flag DEV_DEBUG must be set. Field }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 is used for the debug control flags. If a device supports only a single debug on/off flag, then the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags}{\rtlch\fcs1 \af1 -\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field should be set to NULL. If a device supports multiple debug on/off flags, then the correspondence between bit positions in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 dctrl}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and debug \hich\af1\dbch\af31505\loch\f1 flag names is specified by table }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 debflags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to a continguous array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_debtab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 is used for the d\hich\af1\dbch\af31505\loch\f1 ebug control flags. If a device supports only a single debug on/off flag, then the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +debflags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field should be set to NULL. If a device supports multiple debug on/off flags, then the correspondence between bit positions in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dctrl}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and debug flag names is spec\hich\af1\dbch\af31505\loch\f1 ified by table }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 debflags}{\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to a continguous array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_debtab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 DEBTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ). Each sim_debtab structure specifies a single debug flag: \par \par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid16013944 \hich\af1\dbch\af31505\loch\f1 s}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 truct sim_debtab \{ \par \tab \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab name}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab \tab /}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 * flag name */ -\par \tab \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab mask;\tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* control bit */ +\par \tab \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab mask;\tab \tab \tab \tab /* control bit \hich\af1\dbch\af31505\loch\f1 */ \par \tab \tab \}\hich\af1\dbch\af31505\loch\f1 ; \par \par \hich\af1\dbch\af31505\loch\f1 The fields are the following: @@ -1450,7 +1694,7 @@ DEBUG command, which enables or disables individual debug printouts. \f1\lang1024\langfe1024\noproof\insrsid8352301\charrsid16013944 \hich\af1\dbch\af31505\loch\f1 the dptr is the DEVICE which has the corresponding dctl field.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8129972\charrsid16013944 \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8352301\charrsid16013944 -\par \hich\af1\dbch\af31505\loch\f1 Additionally support exists for displaying bit and bi\hich\af1\dbch\af31505\loch\f1 tfield values. Bit field values are defined using the BITFIELD}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\par \hich\af1\dbch\af31505\loch\f1 Additionally support exists for displaying bit and bitfield va\hich\af1\dbch\af31505\loch\f1 lues. Bit field values are defined using the BITFIELD}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8084824\charrsid16013944 \hich\af1\dbch\af31505\loch\f1 structure and the BIT macros to declare the bits and bitfields.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\lang1024\langfe1024\noproof\insrsid8352301\charrsid16013944 \par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8352301 @@ -1521,18 +1765,18 @@ DEBUG command, which enables or disables individual debug printouts. \f2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 }{\rtlch\fcs1 \af2 \ltrch\fcs0 \b\f2\lang1024\langfe1024\noproof\insrsid8084824\charrsid16013944 \hich\af2\dbch\af31505\loch\f2 sim_debug_bits}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 (uint32 dbits, DEVICE* dptr, BITFIELD* bitdefs, uint32 before, uint32 after, }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\cf2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 int}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\lang1024\langfe1024\noproof\insrsid8084824 \hich\af2\dbch\af31505\loch\f2 terminate); -\par {\*\bkmkstart _Toc347546225}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 4.1.10\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355633}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 4.1.10\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid3867041 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 -\af1 \ltrch\fcs0 \insrsid3867041 \hich\af1\dbch\af31505\loch\f1 Device Specific Help support{\*\bkmkend _Toc347546225} +\af1 \ltrch\fcs0 \insrsid3867041 \hich\af1\dbch\af31505\loch\f1 Device Specific Help support{\*\bkmkend _Toc356355633} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid7174065 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7174065 \par \hich\af1\dbch\af31505\loch\f1 A device declaration may specify a device type or class in the flags field by providing one of DEV_DISK, DEV_TAPE, DEV_MUX, DEV_ETHER or DEV_DISPLAY values when initializing the flags. The device type allows the scp HELP command routine to provide some d \hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 fault help information for devices which don\hich\f1 \rquote \loch\f1 t otherwise specify a device specific help routine or a attach_help routine. \par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid7174065\charrsid7174065 -\par {\*\bkmkstart _Toc347546226}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 4.1.11\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355634}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 4.1.11\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid3867041 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 -\af1 \ltrch\fcs0 \insrsid3867041 \hich\af1\dbch\af31505\loch\f1 Help Routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid14776269 {\*\bkmkend _Toc347546226} +\af1 \ltrch\fcs0 \insrsid3867041 \hich\af1\dbch\af31505\loch\f1 Help Routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid14776269 {\*\bkmkend _Toc356355634} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \par \hich\af1\dbch\af31505\loch\f1 A device declaration may provide a routine which will display help about that device w\hich\af1\dbch\af31505\loch\f1 \hich\f1 hen a user enters a \'93\loch\f1 \hich\f1 HELP dev\'94\loch\f1 command.}{\rtlch\fcs1 \af1 @@ -1548,9 +1792,9 @@ A device declaration may specify a device type or class in the flags field by pr \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 arguments are included for compatibility with the }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 HELP }{ \rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 comma\hich\af1\dbch\af31505\loch\f1 nd\hich\f1 \rquote \loch\f1 s validation routine calling sequence. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 -\par {\*\bkmkstart _Toc347546227}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 4.1.12\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355635}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 4.1.12\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid14776269 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 -\af1 \ltrch\fcs0 \insrsid14776269 \hich\af1\dbch\af31505\loch\f1 Attach Help Routine{\*\bkmkend _Toc347546227} +\af1 \ltrch\fcs0 \insrsid14776269 \hich\af1\dbch\af31505\loch\f1 Attach Help Routine{\*\bkmkend _Toc356355635} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3867041 \hich\af1\dbch\af31505\loch\f1 A device declaration may provide a routine which will display help about h}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \hich\af1\dbch\af31505\loch\f1 @@ -1562,9 +1806,9 @@ ORE to use if memory size must be changed: arguments are included for compatibility with the HELP command\hich\f1 \rquote \loch\f1 s validation routine calling sequence. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14776269 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14776269 \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8084824 -\par {\*\bkmkstart _Toc347546228}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355636}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit Structure{\*\bkmkend _Toc347546228} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit \hich\af1\dbch\af31505\loch\f1 Structure{\*\bkmkend _Toc356355636} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Units are allocated as contiguous array. Each unit is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_unit}{ @@ -1574,14 +1818,14 @@ ORE to use if memory size must be changed: \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct sim_unit \{ \par \tab \hich\af1\dbch\af31505\loch\f1 struct sim_unit\tab *next;\tab \tab \tab \tab /* next active */ \par \tab \hich\af1\dbch\af31505\loch\f1 t_stat\tab \tab (*action)();\tab \tab \tab /* action routine */ -\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab \hich\af1\dbch\af31505\loch\f1 *filename;\tab \tab \tab /* open file name */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *filename;\tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* open file name */ \par \tab \hich\af1\dbch\af31505\loch\f1 FILE\tab \tab *fileref;\tab \tab \tab \tab /* file reference */ \par \tab \hich\af1\dbch\af31505\loch\f1 void\tab \tab *filebuf;\tab \tab \tab \tab /* memory buffer */ \par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab hwmark;\tab \tab \tab /* high water mark */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab time;\tab \tab \tab \tab /* time out */ \par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */ \par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab capac;\tab \tab \tab \tab /* capacity */ -\par \tab \hich\af1\dbch\af31505\loch\f1 t_\hich\af1\dbch\af31505\loch\f1 addr\tab \tab pos;\tab \tab \tab \tab /* file position */ +\par \tab \hich\af1\dbch\af31505\loch\f1 t_addr\tab \tab pos;\tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* file position */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab buf;\tab \tab \tab \tab /* buffer */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab wait;\tab \tab \tab \tab /* wait */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u3;\tab \tab \tab \tab /* device specific */ @@ -1590,14 +1834,15 @@ ORE to use if memory size must be changed: \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab u6;\tab \tab \tab \tab /* device specific */ \par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ; \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 The fields ar\hich\af1\dbch\af31505\loch\f1 e the following: +\par \hich\af1\dbch\af31505\loch\f1 The fields are the follo\hich\af1\dbch\af31505\loch\f1 wing: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 next}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to next unit in active queue, NULL if none. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 action}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 address of unit time-out service routine. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 filename}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to name of attached file, NULL if none. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fileref}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to FILE structure of attached file, NULL if none. -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 hwmark}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 buffered devices only; highest modified address, + 1. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 hwmark}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 buffered d\hich\af1\dbch\af31505\loch\f1 +evices only; highest modified address, + 1. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 time}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 increment until time-out beyond previous unit in active queue. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 unit flags. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 unit capacity, 0 if variable. @@ -1610,13 +1855,13 @@ ORE to use if memory size must be changed: \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u5\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 user-defined. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 u6\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 user-defined. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 buf, wait, u3, u4, u5, u6, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and parts\hich\af1\dbch\af31505\loch\f1 of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 buf, wait, u3, u4, u5, u6, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and parts o\hich\af1\dbch\af31505\loch\f1 f }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 are all saved and restored by the SAVE and RESTORE commands and thus can be used for unit state which must be preserved. \par \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Macro }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UDATA}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is available to fill in the common fields of a UNIT. It is invoked by \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \tab \hich\af1\dbch\af31505\loch\f1 UDATA\tab \tab (action_routine, flags, capacity\hich\af1\dbch\af31505\loch\f1 ) +\par \tab \hich\af1\dbch\af31505\loch\f1 UDATA\tab \tab (action_routine, flags, capacity) \par \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Fields after }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 can be filled in manually, e.g, @@ -1625,13 +1870,13 @@ ORE to use if memory size must be changed: \par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2 UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE, 0), 500 \}; \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 defines the line printer as a sequential unit with a wait time of 500. -\par {\*\bkmkstart _Toc347546229}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355637}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Unit Flags{\*\bkmkend _Toc347546229} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Unit Flags{\*\bkmkend _Toc356355637} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field \hich\af1\dbch\af31505\loch\f1 -contains indicators of current unit status. SIMH defines 12 flags: +\par \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field co\hich\af1\dbch\af31505\loch\f1 +ntains indicators of current unit status. SIMH defines 12 flags: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag name\tab \tab meaning if set \par @@ -1652,9 +1897,9 @@ contains indicators of current unit status. SIMH defines 12 flags: \par \hich\af1\dbch\af31505\loch\f1 Star\hich\af1\dbch\af31505\loch\f1 ting at bit position UNIT_V_UF, the remaining flags are unit-specific. Unit-specific flags are set and cleared with the SET and CLEAR commands, which reference the MTAB array (see below). Unit-specific flags and UNIT_DIS are automatically saved and rest \hich\af1\dbch\af31505\loch\f1 o\hich\af1\dbch\af31505\loch\f1 red; the device need not supply a register for these bits. -\par {\*\bkmkstart _Toc347546230}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355638}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.2.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Service Routine{\*\bkmkend _Toc347546230} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Service Routine{\*\bkmkend _Toc356355638} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 This routine is called by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 @@ -1665,9 +1910,9 @@ ting at bit position UNIT_V_UF, the remaining flags are unit-specific. Unit-spe \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The status return\hich\af1\dbch\af31505\loch\f1 ed by the service routine is passed by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_process_event}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 back to the CPU. -\par {\*\bkmkstart _Toc347546231}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355639}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg Structure{\*\bkmkend _Toc347546231} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_reg Structure{\*\bkmkend _Toc356355639} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Registers are allocated as contiguous array, with a NULL register at the end. Each register is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 @@ -1682,7 +1927,7 @@ ed by the service routine is passed by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\i \par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab offset;\tab \tab \tab \tab /* starting bit */ \par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab depth;\tab \tab \tab \tab /* save depth */ \par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab flags;\tab \tab \tab \tab /* flags */ -\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab qptr;\tab \tab \tab \tab /* current queue pointer */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uin\hich\af1\dbch\af31505\loch\f1 t32\tab \tab qptr;\tab \tab \tab \tab /* current queue pointer */ \par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \}\hich\af1\dbch\af31505\loch\f1 ; \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 The fields are the following: @@ -1691,7 +1936,8 @@ ed by the service routine is passed by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\i \hich\af1\dbch\af31505\loch\f1 device name, string of all capital alphanumeric characters. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 loc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to location of the register value. \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 radix}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 radix for input and display of data, 2 to 16 inclusive. -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 width}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of data, 1 to 32 inclusive. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 wi\hich\af1\dbch\af31505\loch\f1 dth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 width in bits of data, 1 to 32 inclusive. + \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 width\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 bit offset (from right end of data). \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 depth\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 size of data array (normally 1). \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 flags and formatting information. @@ -1754,9 +2000,9 @@ d in automatically. For example, the following declares an arrayed regist\hich\ \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 position fields in a device with 4 units: \par \par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \{\hich\af2\dbch\af31505\loch\f2 URDATA\tab (POS, dev_unit[0].pos, 8, T_ADDR_W, 0, 4, 0) \} -\par {\*\bkmkstart _Toc347546232}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.3.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355640}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.3.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Register Flags{\*\bkmkend _Toc347546232} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Register Flags{\*\bkmkend _Toc356355640} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\outlinelevel0\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 The }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 @@ -1777,9 +2023,9 @@ d in automatically. For example, the following declares an arrayed regist\hich\ \par \hich\af1\dbch\af31505\loch\f1 REG_VMIO\tab \tab register is displayed and parsed usi\hich\af1\dbch\af31505\loch\f1 ng VM data routines. \par \hich\af1\dbch\af31505\loch\f1 REG_VMAD\tab \tab register is displayed and parsed using VM address routines. \par \hich\af1\dbch\af31505\loch\f1 REG_FIT\tab \tab register container uses arrayed rather than scalar size rules. -\par {\*\bkmkstart _Toc347546233}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355641}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab Structure{\*\bkmkend _Toc347546233} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_mtab Structure{\*\bkmkend _Toc356355641} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Device-specific SHOW and SET commands are p\hich\af1\dbch\af31505\loch\f1 @@ -1805,14 +2051,15 @@ rocessed using the modifications array, which is allocated as contiguous array, \par \hich\af1\dbch\af31505\loch\f1 MTAB supports two different structure interpretations: regular and extended. A regular MTAB entry modifies flags in the UNIT flags word; the descriptor entry is not used. The fields are the following: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab -\hich\af1\dbch\af31505\loch\f1 bit mask for testing the unit.}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field -\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 matc\hich\af1\dbch\af31505\loch\f1 h}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 value to be stored (SET) or compared (SHOW) +\hich\af1\dbch\af31505\loch\f1 bit mask for\hich\af1\dbch\af31505\loch\f1 testing the unit.}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 field +\par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab +\hich\af1\dbch\af31505\loch\f1 value to be stored (SET) or compared (SHOW) \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string printed on a match (SHOW), or NULL \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string to be matched (SET), or NULL -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 valid}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of validation routine (SET), or NULL -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 disp\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 address of display\hich\af1\dbch\af31505\loch\f1 routine (SHOW), or NULL +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 valid}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of validation routine (SET\hich\af1\dbch\af31505\loch\f1 ), or NULL +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 disp\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 address of display routine (SHOW), or NULL \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 For SET, a regular MTAB entry is interpreted as follows: \par @@ -1848,28 +2095,27 @@ match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\lo \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mask}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 entry flags -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 MTAB_XTD\tab extended entry +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 MTAB_XTD\tab extende\hich\af1\dbch\af31505\loch\f1 d entry \par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VDV\tab valid for devices \par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VUN\tab valid for units -\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11095770 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VAL\hich\af1\dbch\af31505\loch\f1 R\tab -\hich\af1\dbch\af31505\loch\f1 requires \hich\af1\dbch\af31505\loch\f1 a value +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid11095770 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VALR\tab requires a value \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_VAL}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 -\hich\af1\dbch\af31505\loch\f1 O}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 \hich\af1\dbch\af31505\loch\f1 optionally \hich\af1\dbch\af31505\loch\f1 requires }{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 a value +\hich\af1\dbch\af31505\loch\f1 O}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid11095770 \hich\af1\dbch\af31505\loch\f1 optionally requires }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 a value \par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_NMO\tab valid only in named SHOW \par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_NC\tab do not convert option value to upper case -\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_SHP\tab SHOW parameter takes optional value +\par \tab \tab \hich\af1\dbch\af31505\loch\f1 MTAB_SHP\tab SHOW parameter takes opt\hich\af1\dbch\af31505\loch\f1 ional value \par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 value to be stored (SET) \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string printed on a match (SHOW), or NULL -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 po\hich\af1\dbch\af31505\loch\f1 -inter to character string to be matched (SET), or NULL +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to character string to be matched (SET), or NULL \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 valid}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 address of validation routine (SET), or NULL -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 disp\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 address of display routine (SHOW), or NULL +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 disp\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 address of display ro\hich\af1\dbch\af31505\loch\f1 utine (SHOW), or NULL + \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc\tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pointer to a REG structure (MTAB_VAL set) or \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 a validation-specific structure (MTAB_VAL clear) \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 F\hich\af1\dbch\af31505\loch\f1 or SET, an extended MTAB entry is interpreted as follows: +\par \hich\af1\dbch\af31505\loch\f1 For SET, an extended MTAB entry is interpreted as follows: \par \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 1.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 \pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 @@ -1882,13 +2128,13 @@ inter to character string to be matched (SET), or NULL Test to see if the entry is valid for the type of SET being done (SET device or SET unit). \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 \pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -If a validation routine exists, call it and return its status. The validation routine is responsible for storing the result. +If a validation routine exists, call it and return its status. The validation routine is responsible f\hich\af1\dbch\af31505\loch\f1 or storing the result. \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 \pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is NULL, exit. \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 \pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 If MTAB_VAL is set, parse the SET option for \'93\loch\f1 \hich\f1 -option=n\'94\loch\f1 , and store the value n in the registe\hich\af1\dbch\af31505\loch\f1 r described by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +option=n\'94\loch\f1 , and store the value n in the register described by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 7.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls22\pnrnot0 \pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls22\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Otherwise, store the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 match}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value in the int32 pointed to by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 @@ -1900,153 +2146,147 @@ option=n\'94\loch\f1 , and store the value n in the registe\hich\af1\dbch\af3150 \pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 entry exists. \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 2.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0 -\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Test to see if the entry is valid for th\hich\af1\dbch\af31505\loch\f1 -e type of SHOW being done (device or unit). +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +Test to see if the entry is valid for the type of SHOW being done (device or unit). \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 3.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0 \pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If a display routine exists, call it, otherwise, \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0 -\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 If MTAB_VAL is set, print \'93\loch\f1 \hich\f1 pstring=n\'94 -\loch\f1 , where the value, radix, and width are taken from the register described by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 , otherwise, +\pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 If MT\hich\af1\dbch\af31505\loch\f1 \hich\f1 AB_VAL is set, print \'93 +\loch\f1 \hich\f1 pstring=n\'94\loch\f1 , where the value, radix, and width are taken from the register described by }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , otherwise, \par {\pntext\pard\plain\ltrpar \rtlch\fcs1 \af0\afs20 \ltrch\fcs0 \f1\fs20\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard \ltrpar\ql \fi-360\li1080\ri0\widctlpar\jclisttab\tx1080\wrapdefault{\*\pn \pnlvlbody\ilvl0\ls23\pnrnot0 \pndec\pnstart1\pnindent360\pnsp120\pnhang {\pntxta .}}\faauto\ls23\adjustright\rin0\lin1080\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Print the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 SHOW [dev|unit] \{=\} is a special case. Only two kinds of modifiers can be displayed individually: an extended MTAB entry that takes a value; and any MTAB entry with both a display routine and a }{ -\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Recall that if a display routine e\hich\af1\dbch\af31505\loch\f1 -xists, SHOW does not use the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 entry. For displaying a named modifier, }{ -\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - is used as the string match. This allows implementation of complex display routines that are only invoked by name, e.g., +\par \hich\af1\dbch\af31505\loch\f1 SHOW [dev|unit] \{=\} is a special case. Only two kinds of modifiers can be displayed indi\hich\af1\dbch\af31505\loch\f1 +vidually: an extended MTAB entry that takes a value; and any MTAB entry with both a display routine and a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 . Recall that if a display routine exists, SHOW does not use the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 entry. For displaying a named modifier, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is used as the strin\hich\af1\dbch\af31505\loch\f1 g match. This allows implementation of complex display routines that are only invoked by name, e.g., \par \par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 MTAB cpu_tab[] = \{ -\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 mask, value, \'93\loch\f2 \hich\f2 normal\'94\loch\f2 , \loch\af2\dbch\af31505\hich\f2 \'93\loch\f2 \hich\f2 NORMAL\'94\loch\f2 , NULL, NULL, NULL \}, +\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 mask, value, \'93\loch\f2 \hich\f2 normal\'94\loch\f2 \hich\f2 , \'93\loch\f2 \hich\f2 NORMAL\'94\loch\f2 , NULL, NULL, NULL \}, \par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, \'93\loch\f2 \hich\f2 SPECIAL\'94, \par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 NULL, NULL, NULL, &spec_disp \}, \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \tab \{\hich\af2\dbch\af31505\loch\f2 0 \} \par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \}\hich\af2\dbch\af31505\loch\f2 ; \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 A SHOW CPU command will display only the modifier named NORMAL; but SHOW CPU SPECIAL will invoke the special display routine. -\par {\*\bkmkstart _Toc347546234}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355642}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Validation Routine{\*\bkmkend _Toc347546234} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Validation Routine{\*\bkmkend _Toc356355642} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 The validation routine can be used to validate input during SET processing. It can make other state changes required by the modification or initiate additional dialogs needed by the modifier. Its calling sequence -\hich\af1\dbch\af31505\loch\f1 is: +\par \hich\af1\dbch\af31505\loch\f1 The validation routine can be used to validate input during SET processing. It can make other state changes required by the modification or initiate additional dialogs needed by the modifier. Its calling sequence is: + \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 validation_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 value, char *cptr, void *desc) \hich\f1 \endash \loch\f1 test that }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 -\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 can be set to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 -\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the value portion of the parameter string (any characters after the = sign); if }{\rtlch\fcs1 \ai\af1 -\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is NULL, no value was given. \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 -\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 REG}{\rtlch\fcs1 -\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 or int32 used to store the parameter. -\par {\*\bkmkstart _Toc347546235}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\hich\af1\dbch\af31505\loch\f1 validation_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *upt\hich\af1\dbch\af31505\loch\f1 r, int32 value, char *cptr, void *desc) \hich\f1 \endash \loch\f1 test that }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 .}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flags}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 can be set to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + points to the value portion of the parameter string (any characters after the = sign); if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 is NULL, no value was given. }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the }{ +\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 REG}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 or int32 used to s\hich\af1\dbch\af31505\loch\f1 tore the parameter. +\par {\*\bkmkstart _Toc356355643}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.4.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Display Routine{\*\bkmkend _Toc347546235} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Display Routine{\*\bkmkend _Toc356355643} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 The display routine is called during SHOW processing to display device- or unit-specific state. Its calling sequence is: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 display_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *st, UNIT *uptr, int value, void *desc) \hich\f1 \endash \loch\f1 output device- or unit-specific state for }{ -\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If the modifier is regular MTAB entry, or an extended entry without MTAB_SHP set, }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the structure in the MTAB entry. If the modifie\hich\af1\dbch\af31505\loch\f1 r is an extended MTAB entry with MTAB_SHP set, }{ -\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the optional value string or is NULL if no value was supplied. }{ -\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is the value field of the matched MTAB entry. +\hich\af1\dbch\af31505\loch\f1 display_routine}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *st, UNIT *uptr, int value, void *d\hich\af1\dbch\af31505\loch\f1 esc) \hich\f1 \endash \loch\f1 + output device- or unit-specific state for }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to stream }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If the modifier is regular MTAB entry, or an extended entry without MTAB_SHP set, }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the structure in the MTAB entry. If the modifier is an extended MTAB entry with MTAB_SHP +\hich\af1\dbch\af31505\loch\f1 set, }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + points to the optional value string or is NULL if no value was supplied. }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is the value field of the matched MTAB entry. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 When the display routine is called for a regular MTAB entry, SHOW has output \hich\af1\dbch\af31505\loch\f1 the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 -\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 argument but has not appended a newline. When it is called for an extended MTAB entry, SHOW hasn\hich\f1 \rquote \loch\f1 +\par \hich\af1\dbch\af31505\loch\f1 When the display routine is called for a regular MTAB entry, SHOW has output the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 argument but has not appended a newline. When it is called for an extended MTAB entry, SHOW hasn\hich\f1 \rquote \loch\f1 t output anything. SHOW will append a newline after the display routine returns, except for entries with the MTAB_NMO flag set. -\par {\*\bkmkstart _Toc347546236}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid14383756 \hich\af1\dbch\af31505\loch\f1 4.4.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355644}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid14383756 \hich\af1\dbch\af31505\loch\f1 4.4.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid14383756 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 -\af1 \ltrch\fcs0 \insrsid14383756 \hich\af1\dbch\af31505\loch\f1 Help Flags{\*\bkmkend _Toc347546236} +\af1 \ltrch\fcs0 \insrsid14383756 \hich\af1\dbch\af31505\loch\f1 Help Flag\hich\af1\dbch\af31505\loch\f1 s{\*\bkmkend _Toc356355644} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9796111 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14383756 -\par \hich\af0\dbch\af31505\loch\f0 The flags MTAB_VALR and MTAB_VALO are used to construct command syntax examples when displaying help for SET and SHOW commands.\hich\af0\dbch\af31505\loch\f0 The\hich\af0\dbch\af31505\loch\f0 se flags -\hich\af0\dbch\af31505\loch\f0 do\hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 n\hich\af0\dbch\af31505\loch\f0 o\hich\af0\dbch\af31505\loch\f0 t otherwise influence \hich\af0\dbch\af31505\loch\f0 the actions taken during -\hich\af0\dbch\af31505\loch\f0 processing\hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 of SET or SHOW commands. -\par {\*\bkmkstart _Toc347546237}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid14383756 \hich\af1\dbch\af31505\loch\f1 4.4.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par \hich\af0\dbch\af31505\loch\f0 +The flags MTAB_VALR and MTAB_VALO are used to construct command syntax examples when displaying help for SET and SHOW commands. These flags do not otherwise influence the actions taken during processing of SET or SHOW commands. +\par {\*\bkmkstart _Toc356355645}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid14383756 \hich\af1\dbch\af31505\loch\f1 4.4.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid14383756 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid14383756 \hich\af1\dbch\af31505\loch\f1 Example arguments in the }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid14383756\charrsid9796111 \hich\af1\dbch\af31505\loch\f1 mstring}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid14383756 -{\*\bkmkend _Toc347546237} +{\*\bkmkend _Toc356355645} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9796111 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14383756 -\par \hich\af0\dbch\af31505\loch\f0 The value of the }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\insrsid14383756\charrsid9796111 \hich\af0\dbch\af31505\loch\f0 mstring}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14383756 \hich\af0\dbch\af31505\loch\f0 field -\hich\af0\dbch\af31505\loch\f0 may contain \hich\af0\dbch\af31505\loch\f0 examples of valid additional parameters which may be specified as values. \hich\af0\dbch\af31505\loch\f0 For example: +\par \hich\af0\dbch\af31505\loch\f0 The value of the }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\insrsid14383756\charrsid9796111 \hich\af0\dbch\af31505\loch\f0 mstring}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14383756 \hich\af0\dbch\af31505\loch\f0 + field may contain examples of valid additional parameters which may be specified as values. For example: \par -\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14383756 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid14383756 \tab \hich\af2\dbch\af31505\loch\f2 MTAB \hich\af2\dbch\af31505\loch\f2 cr_mod -\hich\af2\dbch\af31505\loch\f2 [] = \{ -\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 mask, value, \'93\loch\f2 \hich\f2 normal\'94\loch\f2 , \loch\af2\dbch\af31505\hich\f2 \'93\loch\f2 \hich\f2 NORMAL\'94\loch\f2 , NULL, NULL, NULL \}, -\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 MTAB_XTD|MTAB_VDV\hich\af2\dbch\af31505\loch\f2 \hich\f2 , 0, \'93\hich\af2\dbch\af31505\loch\f2 TRANSLATION\loch\af2\dbch\af31505\hich\f2 \'94, -\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0\pararsid14383756 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid873649 \loch\af2\dbch\af31505\hich\f2 \'93\hich\af2\dbch\af31505\loch\f2 TRANSLATION=\{ -\hich\af2\dbch\af31505\loch\f2 DEFAULT|026|\hich\af2\dbch\af31505\loch\f2 026FTN|\hich\af2\dbch\af31505\loch\f2 029|\hich\af2\dbch\af31505\loch\f2 EBCDIC\}\loch\af2\dbch\af31505\hich\f2 \'94}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid14383756 , -\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0\pararsid873649 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid873649 \hich\af2\dbch\af31505\loch\f2 NULL, \hich\af2\dbch\af31505\loch\f2 &cr_set_trans -\hich\af2\dbch\af31505\loch\f2 , &\hich\af2\dbch\af31505\loch\f2 cr_show_trans\hich\af2\dbch\af31505\loch\f2 \}, +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14383756 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid14383756 \tab \hich\af2\dbch\af31505\loch\f2 MTAB cr_mod[] = \{ +\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 mask, value, \'93\loch\f2 \hich\f2 normal\'94\loch\f2 \hich\f2 , \'93\loch\f2 \hich\f2 NORMAL\'94\hich\af2\dbch\af31505\loch\f2 , NULL, NULL, NULL \}, +\par \tab \tab \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 MTAB_XTD|MTAB_VDV, 0, \'93\loch\f2 \hich\f2 TRANSLATION\'94, +\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0\pararsid14383756 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid873649 \loch\af2\dbch\af31505\hich\f2 \'93\loch\f2 TRANSLATION=\{DEFAULT|026|026FTN|029|EBCDIC\} +\hich\f2 \'94}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid14383756 , +\par }\pard \ltrpar\ql \fi720\li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0\pararsid873649 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid873649 \hich\af2\dbch\af31505\loch\f2 NULL, &cr_set_trans, &cr_show_trans \}, \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid14383756 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid14383756 \tab \tab \{\hich\af2\dbch\af31505\loch\f2 0 \} \par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid14383756 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid14383756 \}\hich\af2\dbch\af31505\loch\f2 ; \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9796111 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14383756 \par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649 \hich\af0\dbch\af31505\loch\f0 This entry has an }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\insrsid873649\charrsid9796111 \hich\af0\dbch\af31505\loch\f0 mstring}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649 -\hich\af0\dbch\af31505\loch\f0 value of\hich\af0\dbch\af31505\loch\f0 \hich\af0\dbch\af31505\loch\f0 \loch\af0\dbch\af31505\hich\f0 \'93}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid873649 \hich\af2\dbch\af31505\loch\f2 TRANSLATION=\{ -\hich\af2\dbch\af31505\loch\f2 DEFAULT|026|\hich\af2\dbch\af31505\loch\f2 026FTN|\hich\af2\dbch\af31505\loch\f2 029|\hich\af2\dbch\af31505\loch\f2 EBCDIC\}}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649 \loch\af0\dbch\af31505\hich\f0 \'94 -\hich\af0\dbch\af31505\loch\f0 . When comparisons are made against this string, everything starting at the equal sign and beyond is irrelevant to \hich\af0\dbch\af31505\loch\f0 -the match activity since the input being compared has already been parsed with a delimiter of \loch\af0\dbch\af31505\hich\f0 \lquote \hich\af0\dbch\af31505\loch\f0 =\loch\af0\dbch\af31505\hich\f0 \rquote \hich\af0\dbch\af31505\loch\f0 -. The remaining parts of the }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\insrsid873649\charrsid9796111 \hich\af0\dbch\af31505\loch\f0 mstring}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649 \hich\af0\dbch\af31505\loch\f0 - value are ignored, but are available when constructing \hich\af0\dbch\af31505\loch\f0 HELP \hich\af0\dbch\af31505\loch\f0 dev \hich\af0\dbch\af31505\loch\f0 SET output.}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649\charrsid9796111 +\hich\af0\dbch\af31505\loch\f0 \hich\f0 value of \'93}{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid873649 \hich\af2\dbch\af31505\loch\f2 TRANSLATION=\{DEFAULT|026|026FTN|029|EBCDIC\}}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649 +\loch\af0\dbch\af31505\hich\f0 \'94\loch\f0 . When compar\hich\af0\dbch\af31505\loch\f0 +isons are made against this string, everything starting at the equal sign and beyond is irrelevant to the match activity since the input being compared has already been parsed with a delimiter of \hich\f0 \lquote \loch\f0 =\hich\f0 \rquote \loch\f0 +. The remaining parts of the }{\rtlch\fcs1 \af0 \ltrch\fcs0 \b\insrsid873649\charrsid9796111 \hich\af0\dbch\af31505\loch\f0 mstring}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649 \hich\af0\dbch\af31505\loch\f0 value are ignored, +\hich\af0\dbch\af31505\loch\f0 but are available when constructing HELP dev SET output.}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649\charrsid9796111 \par }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14383756\charrsid9796111 -\par {\*\bkmkstart _Toc347546238}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid873649 \hich\af1\dbch\af31505\loch\f1 4.4.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355646}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid873649 \hich\af1\dbch\af31505\loch\f1 4.4.5\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0\pararsid873649 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid873649 \hich\af1\dbch\af31505\loch\f1 H\hich\af1\dbch\af31505\loch\f1 elp \hich\af1\dbch\af31505\loch\f1 field{\*\bkmkend _Toc347546238} +\ltrch\fcs0 \insrsid873649 \hich\af1\dbch\af31505\loch\f1 Help field{\*\bkmkend _Toc356355646} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9796111 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649 -\par \hich\af0\dbch\af31505\loch\f0 The MTAB entry\loch\af0\dbch\af31505\hich\f0 \rquote \hich\af0\dbch\af31505\loch\f0 s help field \hich\af0\dbch\af31505\loch\f0 is used when constructing HELP \hich\af0\dbch\af31505\loch\f0 dev -\hich\af0\dbch\af31505\loch\f0 SHOW or \hich\af0\dbch\af31505\loch\f0 HELP dev \hich\af0\dbch\af31505\loch\f0 SH\hich\af0\dbch\af31505\loch\f0 OW output. It ser\hich\af0\dbch\af31505\loch\f0 ves to describe the purpose or e\hich\af0\dbch\af31505\loch\f0 -ffect of the \hich\af0\dbch\af31505\loch\f0 particular SET dev or SHOW dev command. \hich\af0\dbch\af31505\loch\f0 T\hich\af0\dbch\af31505\loch\f0 he help field is ignored when constructing \hich\af0\dbch\af31505\loch\f0 HELP dev -\hich\af0\dbch\af31505\loch\f0 SET \hich\af0\dbch\af31505\loch\f0 output for MTAB entries which have an equal sign\hich\af0\dbch\af31505\loch\f0 in the mstring field.\hich\af0\dbch\af31505\loch\f0 }{\rtlch\fcs1 \af0 \ltrch\fcs0 -\insrsid873649\charrsid9796111 +\par \hich\af0\dbch\af31505\loch\f0 The MTAB entry\hich\f0 \rquote \loch\f0 s help field is used when constructing HELP dev SHOW or HELP dev SHOW output. It serves to describe the purpose or effect of the particula\hich\af0\dbch\af31505\loch\f0 +r SET dev or SHOW dev command. The help field is ignored when constructing HELP dev SET output for MTAB entries which have an equal sign in the mstring field. }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid873649\charrsid9796111 \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid14383756 -\par {\*\bkmkstart _Toc347546239}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.5\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355647}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 4.5\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other Data Structures{\*\bkmkend _Toc347546239} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other Data Structures{\*\bkmkend _Toc356355647} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_name[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - is a character array containing the VM name. +\par \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_name[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is a character array cont +\hich\af1\dbch\af31505\loch\f1 aining the VM name. \par \par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - contains the maximum number of words needed to hold the largest instruction or data item in the VM. Examine and deposit will process up to }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim -\hich\af1\dbch\af31505\loch\f1 _emax}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 words. + contains the maximum number of words needed to hold the largest instruction or data item in the VM. Examine and deposit will process up to }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_emax}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 words. \par \par \hich\af1\dbch\af31505\loch\f1 DEVICE *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_devices[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - is an array of pointers to all the devices in the VM. It is terminated by a NULL. By convention, the CPU is always the first device in the array. + is an array of pointers to all the device\hich\af1\dbch\af31505\loch\f1 s in the VM. It is terminated by a NULL. By convention, the CPU is always the first device in the array. \par \par \hich\af1\dbch\af31505\loch\f1 REG *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_PC}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure for the program counter. By convention, the PC is always the first register in the CPU\hich\f1 \rquote \loch\f1 s register array. \par \par \hich\af1\dbch\af31505\loch\f1 char *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_messages[]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - is an array of pointers to character strings, corresponding to error status returns greater than zero. If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_i\hich\af1\dbch\af31505\loch\f1 nstr}{\rtlch\fcs1 \af1 -\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 returns status code n > 0, then }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_message[n]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 is printed by SCP. + is an array of pointers to character strings, corresponding to error status returns greater than zero. If }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 returns status code n > 0, then }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_stop_message[n]}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + is printed by SCP. \par -\par {\*\bkmkstart _Toc347546240}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355648}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM Provided Routines{\*\bkmkend _Toc347546240} -\par {\*\bkmkstart _Toc347546241}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM Provided Routines{\*\bkmkend _Toc356355648} +\par {\*\bkmkstart _Toc356355649}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction Execution{\*\bkmkend _Toc347546241} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Instruction Execution{\*\bkmkend _Toc356355649} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 Instruction execution is performed by routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -. Its calling sequen\hich\af1\dbch\af31505\loch\f1 ce is: +. Its calling sequence is: \par \par }\pard \ltrpar\ql \fi720\li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_instr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (void) \hich\f1 \endash \loch\f1 execute from current PC until error or halt. -\par {\*\bkmkstart _Toc347546242}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355650}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Binary Load and Dump{\*\bkmkend _Toc347546242} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Binary Load and D\hich\af1\dbch\af31505\loch\f1 ump{\*\bkmkend _Toc356355650} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 If the VM responds to the LOAD (or DUMP) command, the load routine (dump routine) is implemented by routine }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 @@ -2054,41 +2294,43 @@ ffect of the \hich\af0\dbch\af31505\loch\f0 particular SET dev or SHOW dev comma \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *fptr, char *buf, char *fnam, t_bool flag) - If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 = 0, load data from binary file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fptr}{\rtlch\fcs1 -\af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - = 1, dump data to binary file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . For either command, }{\rtlch\fcs1 \ai\af1 -\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 contains any VM-specific arguments, and }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 fnam}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 contains the file name. +\hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 = 0, load data fro\hich\af1\dbch\af31505\loch\f1 m binary file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 fptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 flag}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 = 1, dump data to binary file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +. For either command, }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 contains any VM-specific arguments, and }{\rtlch\fcs1 +\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fnam}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 contains the file name. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 If LOAD or DUMP is not implemented, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - should simply return SCPE_ARG. The LOAD and DUMP commands open and close the specified file for }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . -\par {\*\bkmkstart _Toc347546243}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar + should simply return SCPE_ARG. The LOAD and DUMP\hich\af1\dbch\af31505\loch\f1 commands open and close the specified file for }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_load}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 . +\par {\*\bkmkstart _Toc356355651}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Symbolic Examination and Deposit{\*\bkmkend _Toc347546243} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Symbolic Examination and Deposit{\*\bkmkend _Toc356355651} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 If the VM pr\hich\af1\dbch\af31505\loch\f1 ovides symbolic examination and deposit of data, it must provide two routines, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fprint_sym}{ -\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for output and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 for input. Their calling sequences are: +\par \hich\af1\dbch\af31505\loch\f1 If the VM provides symbolic examination and deposit of data, it must provide two routines, }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for output and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for inp +\hich\af1\dbch\af31505\loch\f1 ut. Their calling sequences are: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 switch) \hich\f1 \endash \loch\f1 Based on the -\hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 variable, symbolically output to stream }{ -\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ofile}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 the data in array }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 at the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 in unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 switch) \hich\f1 \endash \loch\f1 Based on the }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 variable, symbolically output to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 ofile}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 the data in array }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 at the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + in unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pa\hich\af1\dbch\af31505\loch\f1 rse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 switch) \hich\f1 \endash \loch\f1 Based on the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 switch}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 variable, parse character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -\hich\af1\dbch\af31505\loch\f1 for a symbolic value }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 at the specified }{\rtlch\fcs1 -\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 in unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\hich\af1\dbch\af31505\loch\f1 variable, parse character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + for a symbolic value }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 at the specified }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 in unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 . \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 If symbolic processing is not implemented, or the output value or input string cannot be parsed, these routines should return SCPE_ARG. If the processing was successful and consumed more than a -\hich\af1\dbch\af31505\loch\f1 single word, then these routines should return extra number of addressing units consumed as a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 negative}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 number. If the processing was successful and consumed a single addressing unit, then these routines should return SCPE_OK. For example, PDP-11 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 parse_s\hich\af1\dbch\af31505\loch\f1 ym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 would respond as follows to various inputs: +\par \hich\af1\dbch\af31505\loch\f1 If symbolic processing is not implemented, or the output val\hich\af1\dbch\af31505\loch\f1 +ue or input string cannot be parsed, these routines should return SCPE_ARG. If the processing was successful and consumed more than a single word, then these routines should return extra number of addressing units consumed as a }{\rtlch\fcs1 \ab\af1 +\ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 negative}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 number. If the pr\hich\af1\dbch\af31505\loch\f1 +ocessing was successful and consumed a single addressing unit, then these routines should return SCPE_OK. For example, PDP-11 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 parse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 would respond as follows to various inputs: \par \par \tab \hich\af1\dbch\af31505\loch\f1 input\tab \tab \tab \tab return value \par @@ -2114,15 +2356,15 @@ uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow1\irowband1\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr \brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow -}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[2]\cell \hich\af1\dbch\af31505\loch\f1 addr + (2 * aincr)\cell }\pard \ltrpar -\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow2\irowband2\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl -\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 -\clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil -\cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[3]\cell \hich\af1\dbch\af31505\loch\f1 addr + (3 * aincr)\cell -}\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow3\irowband3\ltrrow\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 -\trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl -\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 -\cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :\cell +}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[2]\cell \hich\af1\dbch\af31505\loch\f1 addr\hich\af1\dbch\af31505\loch\f1 + + (2 * aincr)\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow2\irowband2\ltrrow\ts11\trgaph108\trleft1350\trbrdrt +\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 +\clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 +\cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val[3]\cell +\hich\af1\dbch\af31505\loch\f1 addr + (3 * aincr)\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow3\irowband3\ltrrow +\ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 +\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr +\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx7290\row \ltrrow}\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 :\cell \hich\af1\dbch\af31505\loch\f1 :\cell }\pard \ltrpar\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \trowd \irow4\irowband4\lastrow \ltrrow \ts11\trgaph108\trleft1350\trbrdrt\brdrs\brdrw10 \trbrdrl\brdrs\brdrw10 \trbrdrb\brdrs\brdrw10 \trbrdrr\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \trbrdrv\brdrs\brdrw10 \trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind1458\tblindtype3 \clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr\brdrs\brdrw10 \cltxlrtb\clftsWidth3\clwWidth2970\clshdrawnil \cellx4320\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrl\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \clbrdrr @@ -2131,12 +2373,12 @@ uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . is typically filled in and stored by calls on the device\hich\f1 \rquote \loch\f1 s examine and deposit routines, respectively, the examine and deposit routines and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fparse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 must agree on the expected width of items in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -, and on the alignment of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Further,\hich\af1\dbch\af31505\loch\f1 if }{ -\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fparse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 wants to modify a storage unit narrower than }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 -\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , it must insert the new data into the appropriate entry in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 without destroying surrounding fields. +, and on the alignment of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Further, if }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 fparse_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 wants to modify a storage unit narrower than }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 awidth}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , it must insert the new data into the appropriate entry in }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 val}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 without destroying surrounding field\hich\af1\dbch\af31505\loch\f1 s. \par -\par \hich\af1\dbch\af31505\loch\f1 The interpretation of switch values is arbitrary, but the following are used by existi\hich\af1\dbch\af31505\loch\f1 ng VM\hich\f1 \rquote \loch\f1 s: +\par \hich\af1\dbch\af31505\loch\f1 The interpretation of switch values is arbitrary, but the following are used by existing VM\hich\f1 \rquote \loch\f1 s: \par \par \tab \hich\af1\dbch\af31505\loch\f1 switch\tab \tab \tab \tab interpretation \par @@ -2144,87 +2386,90 @@ fprint_sym}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af315 \par \tab \hich\af1\dbch\af31505\loch\f1 -c\tab \tab \tab \tab character string \par \tab \hich\af1\dbch\af31505\loch\f1 -m\tab \tab \tab \tab instruction mnemonic \par -\par \hich\af1\dbch\af31505\loch\f1 In addition, on input, a leading \hich\f1 \lquote \loch\f1 \hich\f1 (apostrophe) is interpreted to mean a single character, and a leading \'93\hich\af1\dbch\af31505\loch\f1 +\par \hich\af1\dbch\af31505\loch\f1 In addition, on input, a leading \hich\f1 \lquote \loch\f1 (apostrophe) is i\hich\af1\dbch\af31505\loch\f1 \hich\f1 nterpreted to mean a single character, and a leading \'93\loch\f1 (double quote) is interpreted to mean a character string. -\par {\*\bkmkstart _Toc347546244}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355652}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Optional Interfaces{\*\bkmkend _Toc347546244} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Optional Interfaces{\*\bkmkend _Toc356355652} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 For greater flexibility, SCP provides some optional interfaces that can be used to extend its command input, command processing, and command post-\hich\af1\dbch\af31505\loch\f1 -processing capabilities. These interfaces are strictly optional and are off by default. Using them requires intimate knowledge of how SCP functions internally and is not recommended to the novice VM writer. -\par {\*\bkmkstart _Toc347546245}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par \hich\af1\dbch\af31505\loch\f1 For greater flexibility, SCP provides some optional interfaces that can be used to extend it\hich\af1\dbch\af31505\loch\f1 +s command input, command processing, and command post-processing capabilities. These interfaces are strictly optional and are off by default. Using them requires intimate knowledge of how SCP functions internally and is not recommended to the novice VM +\hich\af1\dbch\af31505\loch\f1 w\hich\af1\dbch\af31505\loch\f1 riter. +\par {\*\bkmkstart _Toc356355653}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.1\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Once Only Initialization Rou\hich\af1\dbch\af31505\loch\f1 tine{\*\bkmkend _Toc347546245} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Once Only Initialization Routine{\*\bkmkend _Toc356355653} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer (*}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_init}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 -)(void). This is a \'93\loch\f1 \hich\f1 weak global\'94\loch\f1 ; if no other module defines this value, it will default to NULL. A VM requiring special initialization should fill in this pointer with the address of its special init -\hich\af1\dbch\af31505\loch\f1 ialization routine: +)(void). This is a \'93\loch\f1 \hich\f1 weak global\'94\loch\f1 ; if no other module defines this value, it will default to NULL. A VM requiring special initialization should fil\hich\af1\dbch\af31505\loch\f1 +l in this pointer with the address of its special initialization routine: \par \par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 void sim_special_init (void); \par \tab \hich\af2\dbch\af31505\loch\f2 void (*sim_vm_init)(void) = &sim_special_init; \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 The special initialization routine can perform any actions required by the VM. If the other optional interfaces are to be used, the initialization routine\hich\af1\dbch\af31505\loch\f1 - can fill in the appropriate pointers; however, this can just as easily be done in the CPU reset routine. -\par {\*\bkmkstart _Toc347546246}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par \hich\af1\dbch\af31505\loch\f1 +The special initialization routine can perform any actions required by the VM. If the other optional interfaces are to be used, the initialization routine can fill in the appropriate pointers; however, this can just as easily be done in the CPU reset rou +\hich\af1\dbch\af31505\loch\f1 t\hich\af1\dbch\af31505\loch\f1 ine. +\par {\*\bkmkstart _Toc356355654}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.2\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Address Input and Display{\*\bkmkend _Toc347546246} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Address Input and Display{\*\bkmkend _Toc356355654} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer t_addr *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -)(DEVICE *, char *, char **). This is init\hich\af1\dbch\af31505\loch\f1 -ialized to NULL. If it is filled in by the VM, SCP will use the specified routine to parse addresses in place of its standard numerical input routine. The calling sequence for the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 routine is: +)(DEVICE *, char *, char **). This is initialized to NULL. If it is filled in by the VM, SCP will use the specified routine to parse addresses\hich\af1\dbch\af31505\loch\f1 + in place of its standard numerical input routine. The calling sequence for the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 routine is: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_addr }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (DEVICE *dptr, cha\hich\af1\dbch\af31505\loch\f1 r *cptr, char **optr) \hich\f1 \endash \loch\f1 - parse the string pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 as an address for the device pointed to by }{ -\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . o}{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 ptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the first character not successfully parsed. If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 == }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 optr}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , parsing failed. +\hich\af1\dbch\af31505\loch\f1 sim_vm_parse_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (DEVICE *dptr, char *cptr, char **optr) \hich\f1 \endash \loch\f1 parse the string pointed to by }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 as an address for the device pointed to b\hich\af1\dbch\af31505\loch\f1 y }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . o}{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ptr}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 points to the first character not successfully parsed. If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 == }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 optr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , parsing failed. + \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer void *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 )(FI -\hich\af1\dbch\af31505\loch\f1 LE *, DEVICE *, t_addr). This is initialized to NULL. If it is filled in by the VM, SCP will use the specified routine to print addresses in place of its standard numerical output routine. The calling sequence for the }{ -\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 routine is: +\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer void *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +)(FILE *, DEVICE *, t_addr). This is initialized to NULL. If it is filled in by the VM, SCP will use th\hich\af1\dbch\af31505\loch\f1 +e specified routine to print addresses in place of its standard numerical output routine. The calling sequence for the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 routine is: \par -\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_a\hich\af1\dbch\af31505\loch\f1 ddr }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 -\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *stream, DEVICE *dptr, t_addr addr) \hich\f1 \endash \loch\f1 output address }{\rtlch\fcs1 -\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 stream}{ -\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 in the format required by the device pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 . -\par {\*\bkmkstart _Toc347546247}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_addr }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_vm_fprint_addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *stream, DEVICE *dptr, t_addr addr) \hich\f1 \endash \loch\f1 output address }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 addr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 stream}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 in t\hich\af1\dbch\af31505\loch\f1 he format required by the device pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 . +\par {\*\bkmkstart _Toc356355655}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.3\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Command Input and Post-Processing{\*\bkmkend _Toc347546247} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Command Input and Post-Processing{\*\bkmkend _Toc356355655} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer char* (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm\hich\af1\dbch\af31505\loch\f1 _read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 )(char *, int32 *, FILE *). This is initialized to NULL. If it is filled in by the VM, SCP will use the specified routine to obtain command input in place of its standard routine, read_line. The calling sequence for the } +\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer char* (}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +)(char *, int32 *, FILE *). This is initialized to NULL. If it is filled in by the VM, SCP wil\hich\af1\dbch\af31505\loch\f1 l use the specified routine to obtain command input in place of its standard routine, read_line. The calling sequence for the } {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_read}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 routine is: \par -\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cha\hich\af1\dbch\af31505\loch\f1 r }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 -\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_input}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (char *buf, int32 *max, FILE *stream) \hich\f1 \endash \loch\f1 read the next command line from }{ -\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 stream}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and store it in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 sim_vm_input}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (char *buf, int32 *max, FILE *stream) \hich\f1 \endash \loch\f1 read the next command line from }{\rtlch\fcs1 \ai\af1 +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 stream}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and sto\hich\af1\dbch\af31505\loch\f1 re it in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , up to a maximum of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 max}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 characters \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 The routine is expected to strip off leading whitespace characters and to return NULL on end of file. \par -\par \hich\af1\dbch\af31505\loch\f1 SCP\hich\af1\dbch\af31505\loch\f1 defines a pointer void *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_post}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 )(t_bool from_scp). This is initialized to NULL. If filled in by the VM, SCP will call the specified routine at the end of every command. This allows the VM to update any local state, such as a GUI console display -\hich\af1\dbch\af31505\loch\f1 . The calling sequence for the vm_post routine is: +\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer void *(}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_post}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +)(t_bool from_scp). This is initialized to NULL. If filled in \hich\af1\dbch\af31505\loch\f1 +by the VM, SCP will call the specified routine at the end of every command. This allows the VM to update any local state, such as a GUI console display. The calling sequence for the vm_post routine is: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 sim_vm_postupdate}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (t_bool from_scp) \hich\f1 \endash \loch\f1 if called from SCP, the argument }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 -\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 from_scp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is TRUE; otherwise, it is FALSE. -\par {\*\bkmkstart _Toc347546248}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar +\hich\af1\dbch\af31505\loch\f1 sim_vm_postupdate}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (t_bool from_scp) \hich\f1 \endash \loch\f1 if calle\hich\af1\dbch\af31505\loch\f1 d from SCP, the argument }{\rtlch\fcs1 +\ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 from_scp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is TRUE; otherwise, it is FALSE. +\par {\*\bkmkstart _Toc356355656}{\listtext\pard\plain\ltrpar \s3 \rtlch\fcs1 \af0 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 5.4.4\tab}}\pard\plain \ltrpar\s3\ql \fi-720\li720\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx720\wrapdefault\faauto\ls1\ilvl2\outlinelevel2\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs24\alang1025 \ltrch\fcs0 \fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM-Specific Commands{\*\bkmkend _Toc347546248} +\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 VM-Specific Commands{\*\bkmkend _Toc356355656} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer CTAB *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim\hich\af1\dbch\af31505\loch\f1 _vm_cmd}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 . This is initialized to NULL. If filled in by the VM, SCP interprets it as a pointer to SCP command table. This command table is checked before user input is looked up in the standard command table. +\par \hich\af1\dbch\af31505\loch\f1 SCP defines a pointer CTAB *}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_vm_cmd}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . T +\hich\af1\dbch\af31505\loch\f1 his is initialized to NULL. If filled in by the VM, SCP interprets it as a pointer to SCP command table. This command table is checked before user input is looked up in the standard command table. \par \par \hich\af1\dbch\af31505\loch\f1 A command table is allocated as a contiguous \hich\af1\dbch\af31505\loch\f1 array. Each entry is defined with a }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_ctab}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 CTAB}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 @@ -2245,117 +2490,120 @@ ialized to NULL. If it is filled in by the VM, SCP will use the specified routi \ltrch\fcs0 \f1\insrsid4550150 \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 The string passed to the action routine starts at the \hich\af1\dbch\af31505\loch\f1 first non-blank character past the command name. -\par {\*\bkmkstart _Toc347546249}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355657}{\listtext\pard\plain\ltrpar \s1 \rtlch\fcs1 \ab\af0\afs28 \ltrch\fcs0 \b\f1\fs28\kerning28\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.\tab}}\pard\plain \ltrpar\s1\ql \fi-360\li360\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx360\wrapdefault\faauto\ls1\outlinelevel0\adjustright\rin0\lin360\itap0 \rtlch\fcs1 \ab\af1\afs28\alang1025 \ltrch\fcs0 \b\fs28\lang1033\langfe1033\kerning28\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other SCP Facilities{\*\bkmkend _Toc347546249} -\par {\*\bkmkstart _Toc347546250}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Other SCP Facilities{\*\bkmkend _Toc356355657} +\par {\*\bkmkstart _Toc356355658}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.1\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Input/Output Formatting Library{\*\bkmkend _Toc347546250} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Input/Output Formatting Library{\*\bkmkend _Toc356355658} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 SIMH provides routines to convert ASCII input characters to the format expected VM, and to convert VM-supplied ASCII characters to C-standard format. The routines are +\par \hich\af1\dbch\af31505\loch\f1 SIMH provides routines to convert ASCII input characters to the format expected VM, a\hich\af1\dbch\af31505\loch\f1 nd to convert VM-supplied ASCII characters to C-standard format. The routines are \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_inpcvt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 c, uint32 mode) \hich\f1 \endash \loch\f1 convert input character }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 c}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 according to the\hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mode }{ -\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 specification and return the converted result (-1 if the character is not valid in the specified mode). +\hich\af1\dbch\af31505\loch\f1 c}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 according to the }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mode }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 specification and return the converted result (-1 if the character is not valid\hich\af1\dbch\af31505\loch\f1 in the specified mode). \par \par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_outcvt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 c, uint32 mode) \hich\f1 \endash \loch\f1 convert output character }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 c}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 according to the }{\rtlch\fcs1 \ai\af1 -\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 specification and return the converted result (-1 i\hich\af1\dbch\af31505\loch\f1 -f the character is not valid in the specified mode). +\ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mode}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 specification and return the converted result (-1 if the character is not valid in the specified mode). + \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 The supported modes are: \par -\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_8B\tab 8b mode; no conversion +\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF\hich\af1\dbch\af31505\loch\f1 _MODE_8B\tab 8b mode; no conversion \par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_7B\tab 7b mode; the high-order bit is masked off \par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_7P\tab 7b printable mode; the high-order bit is masked off -\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 In addition, \hich\af1\dbch\af31505\loch\f1 on output, if the character is not printable, +\par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 In addition, on output, if the character is not printable, \par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 -1 is returned -\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_UC\tab 7b upper case mode; the high-order bit is masked off +\par \tab \hich\af1\dbch\af31505\loch\f1 TTUF_MODE_UC\tab 7\hich\af1\dbch\af31505\loch\f1 b upper case mode; the high-order bit is masked off \par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 In addition, lower case is converted to upper case \par \tab \tab \tab \tab \hich\af1\dbch\af31505\loch\f1 If the character is not printable, -1 is returned \par -\par \hich\af1\dbch\af31505\loch\f1 On input, TTUF\hich\af1\dbch\af31505\loch\f1 _MODE_UC has an additional modifier, TTUF_MODE_KSR, which forces the high order bit to be set rather than cleared. +\par \hich\af1\dbch\af31505\loch\f1 On input, TTUF_MODE_UC has an additional modifier, TTUF_MODE_KSR, which forces the high order \hich\af1\dbch\af31505\loch\f1 bit to be set rather than cleared. \par \par \hich\af1\dbch\af31505\loch\f1 The set of printable control characters is contained in the global bit-vector variable }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Each bit represents the character corr\hich\af1\dbch\af31505\loch\f1 -esponding to the bit number (e.g., bit 0 represents NUL, bit 1 represents SOH, etc.). If a bit is set, the corresponding control character is considered printable. It initially contains the following characters: BEL, BS, HT, LF, and CR. The set may be -\hich\af1\dbch\af31505\loch\f1 m\hich\af1\dbch\af31505\loch\f1 anipulated with these routines: +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Each bit represents the character corresponding to the bit number (e.g., bit 0 represents NUL, bit 1 represents SOH, e\hich\af1\dbch\af31505\loch\f1 +tc.). If a bit is set, the corresponding control character is considered printable. It initially contains the following characters: BEL, BS, HT, LF, and CR. The set may be manipulated with these routines: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 sim_set_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 flag, char *cptr) \hich\f1 \endash \loch\f1 set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the value pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{ -\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ; return SCPE_2FARG if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 is null or points to a null string, or SCPE_ARG if the value cannot be converted or does not contai\hich\af1\dbch\af31505\loch\f1 n at least CR and LF. +\hich\af1\dbch\af31505\loch\f1 sim_set_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (int32 flag, char *cptr) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the value pointed to by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ; return SCPE_2FARG if }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is null or points to a null string, or SCPE_ARG if the value cannot be converted or does not contain at least CR and LF. \par -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_show_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr) \hich\f1 \endash \loch\f1 output the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_show_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *st, DEVICE *dptr, UNIT *uptr +\hich\af1\dbch\af31505\loch\f1 , int32 flag, char *cptr) \hich\f1 \endash \loch\f1 output the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tt_pchar}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 value to the stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 Note that the DEL character is always considered non-printable and will be suppressed in the UC and\hich\af1\dbch\af31505\loch\f1 7P modes. +\par \hich\af1\dbch\af31505\loch\f1 Note that the DEL character is always considered non-printable and will be suppressed in the UC and 7P modes. \par -\par {\*\bkmkstart _Toc347546251}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355659}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.2\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Multiplexer Emulation Library{\*\bkmkend _Toc347546251} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Terminal Multiplexer Emulation Library{\*\bkmkend _Toc356355659} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 SIMH supports the use of multiple terminals. All terminals except the console are accessed via Telnet}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 or serial ports on the host machine}{ \rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . SIMH provides }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 three }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 supporting li\hich\af1\dbch\af31505\loch\f1 braries for implementing multiple terminals: sim_tmxr.c (and its header file, sim_tmxr.h), which provide OS-independent support routines for terminal multiplexers; }{\rtlch\fcs1 -\af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 sim_serial.c (and its header file sim_serial.h), which provide OS-dependent serial I/O routi\hich\af1\dbch\af31505\loch\f1 nes; }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 and sim_sock.c (and its header file, sim_sock.h), which provide OS-dependent socket routines. Sim_sock.c }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 and sim_serial.c are}{\rtlch\fcs1 +\hich\af1\dbch\af31505\loch\f1 supporting libraries for implementing multiple terminals: sim_tmxr.c (and its header file, si\hich\af1\dbch\af31505\loch\f1 m_tmxr.h), which provide OS-independent support routines for terminal multiplexers; }{\rtlch\fcs1 +\af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 sim_serial.c (and its header file sim_serial.h), which provide OS-dependent serial I/O routines; }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +and sim_sock.c (and its header file, sim_sock.h), which provide OS-dependen\hich\af1\dbch\af31505\loch\f1 t socket routines. Sim_sock.c }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 and sim_serial.c are}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 implemented under Windows, VMS, UNIX, and MacOS. \par -\par \hich\af1\dbch\af31505\loch\f1 Two basic data structures define the multiple terminals. Individual lines\hich\af1\dbch\af31505\loch\f1 are defined by an array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmln -}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TMLN}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 ): +\par \hich\af1\dbch\af31505\loch\f1 Two basic data structures define the multiple terminals. Individual lines are defined by an array of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmln}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structures (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TMLN}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ): \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct tmln \{ -\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int\tab \tab conn;\tab \tab \tab \tab /* line connected flag */ - +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int\tab \tab \hich\af1\dbch\af31505\loch\f1 conn;\tab \tab \tab +\tab /* line connected flag */ \par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1 SOCKET\tab sock;\tab \tab \tab \tab /* connection socket */ \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1 char }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ipad;\tab \tab \tab \tab /* IP address */ \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 SOCKET\tab master;\tab \tab \tab \tab /* line specific master socket */ -\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab \hich\af1\dbch\af31505\loch\f1 *port;\tab \tab \tab \tab /* line specific listening port */ -\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab sessions;\tab \tab \tab /* count of tcp connections received */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *port;\tab \tab \tab \tab /* line specific listening port */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab sessions;\tab \tab \tab \hich\af1\dbch\af31505\loch\f1 /* count of tcp connections received */ \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab cnms;\tab \tab \tab \tab /* connect time ms */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab tsta;\tab \tab \tab \tab /* Telnet state */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rcve;\tab \tab \tab \tab /* rcv enable */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab xmte;\tab \tab \tab \tab /* xmt enable */ -\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab \hich\af1\dbch\af31505\loch\f1 dstb;\tab \tab \tab \tab /* disable Tlnt bin */ -\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab notelnet;\tab \tab \tab -/* raw binary data (no telnet interpret) */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab dstb;\tab \tab \tab \tab /* disable Tlnt bin */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab notelnet;\tab \tab \tab /* raw bina +\hich\af1\dbch\af31505\loch\f1 ry data (no telnet interpret) */ \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxbpr;\tab \tab \tab \tab /* rcv buf remove */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxbpi;\tab \tab \tab \tab /* rcv buf insert */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab rxcnt;\tab \tab \tab \tab /* rcv count */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txbpr;\tab \tab \tab \tab /* xmt buf remove */ -\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab \hich\af1\dbch\af31505\loch\f1 txbpi;\tab \tab \tab \tab /* xmt buf insert */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txbpi;\tab \tab \tab \tab /* xmt buf insert */ \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txcnt;\tab \tab \tab \tab /* xmt count */ \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txdrp;\tab \tab \tab \tab /* xmt drop count */ \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid4462419 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4462419 \hich\af1\dbch\af31505\loch\f1 \tab int32\tab \tab txbsz;\tab \tab \tab \tab /* xmt buffer size */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab txbfd;\tab \tab \tab \tab /* xmt buffered flag */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid2634434 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 t_bool}{ +\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 modem_control}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab +\hich\af1\dbch\af31505\loch\f1 /* }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 line modem control support}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 */ +\par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 modembits}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 ;\tab \tab \tab +\hich\af1\dbch\af31505\loch\f1 /* }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 modem bits which are set}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 */ \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 FILE\tab \tab *txlog;\tab \tab \tab \tab /* xmt log file */ -\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid3891160 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 FILEREF\tab *txlogref;\tab \tab \tab -\hich\af1\dbch\af31505\loch\f1 /* xmt log file reference */ +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid3891160 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 FILEREF\tab *txlogref;\tab \tab \tab /* xmt log file reference */ + \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *txlogname;\tab \tab \tab /* xmt log file name */ \par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab rxb[TMXR_MAXBUF];\tab \tab /* rcv buffer */ \par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab rbr[TMXR_MAXBUF];\tab \tab /* rcv break */ \par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txb;}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 /* xmt buffer */ \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 TMXR\tab \tab *mp;\tab \tab \tab \tab /* back pointer to mux */ -\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *serconfig;\tab \tab \tab /*\hich\af1\dbch\af31505\loch\f1 line config */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *serconfig;\tab \tab \tab /* line config */ \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid3891160 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 SERHANDLE\tab serport;\tab \tab \tab \tab /* serial port handle */ -\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab ser_connect_pending;\tab \tab +\par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab \hich\af1\dbch\af31505\loch\f1 ser_connect_pending;\tab \tab /* serial connection notice pending */ \par \tab \hich\af1\dbch\af31505\loch\f1 SOCKET\tab connecting;\tab \tab \tab /* Outgoing socket while connecting */ -\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *destination;\tab \tab \tab /* Outgoing destination address:port *\hich\af1\dbch\af31505\loch\f1 / +\par \tab \hich\af1\dbch\af31505\loch\f1 char\tab \tab *destination;\tab \tab \tab /* Outgoing destination address:port */ \par \tab \hich\af1\dbch\af31505\loch\f1 UNIT\tab \tab *uptr;\tab \tab \tab \tab /* input polling unit -default to mp->uptr */ -\par \tab \hich\af1\dbch\af31505\loch\f1 UNIT\tab \tab *o_uptr;\tab \tab \tab \tab /* output polling unit \hich\f1 \endash \loch\f1 default to lp->uptr */ +\par \tab \hich\af1\dbch\af31505\loch\f1 UNIT\tab \tab *\hich\af1\dbch\af31505\loch\f1 o_uptr;\tab \tab \tab \tab /* output polling unit \hich\f1 \endash \loch\f1 default to lp->uptr */ \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \}\hich\af1\dbch\af31505\loch\f1 ; \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 The fields are the following: @@ -2364,8 +2612,7 @@ esponding to the bit number (e.g., bit 0 represents NUL, bit 1 represents SOH, e \hich\af1\dbch\af31505\loch\f1 flag }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (0 = disconnected) \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid3891160 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3891160\charrsid3891160 \hich\af1\dbch\af31505\loch\f1 sock}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \tab \hich\af1\dbch\af31505\loch\f1 connection socket -\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid3806017 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \hich\af1\dbch\af31505\loch\f1 ipad\tab \tab IP address of r\hich\af1\dbch\af31505\loch\f1 -emote end of connection +\par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid3806017 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \hich\af1\dbch\af31505\loch\f1 ipad\tab \tab IP address of remote end of connection \par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3806017\charrsid3806017 \hich\af1\dbch\af31505\loch\f1 master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \tab \hich\af1\dbch\af31505\loch\f1 optional line specific listening socket \par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3806017\charrsid3806017 \hich\af1\dbch\af31505\loch\f1 port}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \tab \hich\af1\dbch\af31505\loch\f1 optional line specific listening port \par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid3806017 \hich\af1\dbch\af31505\loch\f1 sessions}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3806017 \tab \hich\af1\dbch\af31505\loch\f1 count of tcp connections received @@ -2374,12 +2621,12 @@ emote end of connection \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 Telnet state \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rcve}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive enable flag (0 = disabled) \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 xmte}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit flow control flag (0 = transmit disabled) -\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dstb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 Telnet bin mode disabled +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dstb}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 Telnet bin mode disa\hich\af1\dbch\af31505\loch\f1 bled \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxbp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 r\tab \tab receive buffer remove pointer \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxbpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive buffer insert pointer \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 rxcnt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 receive count \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txbpr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer remove pointer -\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txbpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer insert point\hich\af1\dbch\af31505\loch\f1 er +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txbpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer insert pointer \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txcnt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit count \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txlog}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 pointer to log file descriptor \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 txlogname}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to log file name @@ -2390,21 +2637,21 @@ emote end of connection \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 transmit buffer \par \par \hich\af1\dbch\af31505\loch\f1 The overall set of extra terminals is defined by the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TMX\hich\af1\dbch\af31505\loch\f1 R}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ): + structure (typedef }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 TMXR}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ): \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 struct tmxr \{ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab lines;\tab \tab \tab \tab /* # lines */ \par \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \hich\af1\dbch\af31505\loch\f1 char}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \hich\af1\dbch\af31505\loch\f1 *}{\rtlch\fcs1 \af1 -\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 port;\tab \tab \tab \tab /* listening port */ +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 port;\tab \tab \tab \tab /* liste\hich\af1\dbch\af31505\loch\f1 ning port */ \par \tab \hich\af1\dbch\af31505\loch\f1 SOCKET\tab master;\tab \tab \tab \tab /* master socket */ \par \tab \hich\af1\dbch\af31505\loch\f1 TMLN\tab \tab *ldsc;\tab \tab \tab \tab /* pointer to line descriptors */ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab *lnorder;\tab \tab \tab /* line connection order */ -\par \tab \hich\af1\dbch\af31505\loch\f1 DEVICE\tab *dptr;\tab \tab \tab \tab /* multiple\hich\af1\dbch\af31505\loch\f1 xer device */ +\par \tab \hich\af1\dbch\af31505\loch\f1 DEVICE\tab *dptr;\tab \tab \tab \tab /* multiplexer device */ \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \tab \hich\af1\dbch\af31505\loch\f1 UNIT\tab \tab *uptr;\tab \tab \tab \tab /* polling unit (connection) */ -\par \tab \hich\af1\dbch\af31505\loch\f1 char \tab \tab logfiletmpl[FILENAMEMAX];\tab /* template logfile name */ +\par \tab \hich\af1\dbch\af31505\loch\f1 char \tab \tab logfi\hich\af1\dbch\af31505\loch\f1 letmpl[FILENAMEMAX];\tab /* template logfile name */ \par \tab \hich\af1\dbch\af31505\loch\f1 int23\tab \tab buffered;\tab \tab \tab /* Buffered line behavior and buffer size*/ \par \tab \hich\af1\dbch\af31505\loch\f1 int32\tab \tab sessions;\tab \tab \tab /* count of tcp connections received */ -\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab \hich\af1\dbch\af31505\loch\f1 last_poll_time;\tab \tab \tab /* time of last connection poll */ +\par \tab \hich\af1\dbch\af31505\loch\f1 uint32\tab \tab last_poll_time;\tab \tab \tab /* time of last connection poll */ \par \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab notelnet;\tab \tab \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 /* default telnet capability for incoming connections */}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid3891160 \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \tab \hich\af1\dbch\af31505\loch\f1 t_bool\tab \tab modem_control;\tab \tab \tab /* multiplexer supports modem control behaviors */ @@ -2412,18 +2659,18 @@ emote end of connection \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 The fields are the following: \par -\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lines}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 nu\hich\af1\dbch\af31505\loch\f1 mber of lines (constant) +\par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lines}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 number of lines (constant) \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 port}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 master listening port (specified by ATTACH command) \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 master listening socket (filled in by ATTACH command) \par \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ldsc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \tab \hich\af1\dbch\af31505\loch\f1 array of line descriptors \par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab -\hich\af1\dbch\af31505\loch\f1 array of line numbers in order of connection sequence, or NULL if us\hich\af1\dbch\af31505\loch\f1 er-defined connection order is not required +\hich\af1\dbch\af31505\loch\f1 array of line numbers in order of connection sequence, or NULL if user-defined connection order is n\hich\af1\dbch\af31505\loch\f1 ot required \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab \hich\af1\dbch\af31505\loch\f1 pointer to the multiplexer\hich\f1 \rquote \loch\f1 s DEVICE structure, or NULL if the device is to be derived from the UNIT passed to the attach call. \par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid1264706 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid1264706 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 \tab \hich\af1\dbch\af31505\loch\f1 the UNIT passed to the attach call. \par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid7674256 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 logfiletmpl}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid1264706 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 template logfile name used \hich\af1\dbch\af31505\loch\f1 to create names for per line log filesl.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 +\f1\insrsid1264706 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 template logfile name used to create names for per line log\hich\af1\dbch\af31505\loch\f1 filesl.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 buffered}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 Buffered line behaviors enabled flag and the size of the line buffer.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 @@ -2431,9 +2678,8 @@ Buffered line behaviors enabled flag and the size of the line buffer.}{\rtlch\fc \f1\insrsid1264706 \tab }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 count of tcp connections received on the master socket}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 . \par }\pard \ltrpar\ql \fi-1440\li2160\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin2160\itap0\pararsid7674256 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 last_poll_time}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \tab \hich\af1\dbch\af31505\loch\f1 time of last connection poll. -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 notelnet}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \tab \hich\af1\dbch\af31505\loch\f1 default telnet \hich\af1\dbch\af31505\loch\f1 -capability for tcp connections. -\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 modem_control}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \tab \hich\af1\dbch\af31505\loch\f1 +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 notelnet}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \tab \hich\af1\dbch\af31505\loch\f1 default telnet capability for tcp connections. +\par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 mo\hich\af1\dbch\af31505\loch\f1 dem_control}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid7674256 \tab \hich\af1\dbch\af31505\loch\f1 flag indicating that multiplexer supports full modem control behaviors. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid1264706 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid1264706 \par @@ -2442,12 +2688,12 @@ flag indicating that multiplexer supports full modem control behaviors. \par \hich\af1\dbch\af31505\loch\f1 The number of elements in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ldsc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 arrays must equal the value of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lines}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field. Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to NULL if the connection \hich\af1\dbch\af31505\loch\f1 order feature is not needed. If the first element of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to NULL if the connection order feature is not needed. If t\hich\af1\dbch\af31505\loch\f1 he first element of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 array is \hich\f1 \endash \loch\f1 1, then the default ascending sequential connection order is used. Set }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 dptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to NULL if the device should be derived from the unit passed to the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 call. \par -\par \hich\af1\dbch\af31505\loch\f1 Library sim_tmxr\hich\af1\dbch\af31505\loch\f1 .c provides the following routines to support Telnet}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 and Serial port}{\rtlch\fcs1 \af1 +\par \hich\af1\dbch\af31505\loch\f1 Library sim_tmxr.c provides the following routines\hich\af1\dbch\af31505\loch\f1 to support Telnet}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid8129972 \hich\af1\dbch\af31505\loch\f1 and Serial port}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -based terminals: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 @@ -2462,12 +2708,14 @@ lnorder}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\ \par \par \hich\af1\dbch\af31505\loch\f1 int32 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_getc_ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMLN *lp) \hich\f1 \endash \loch\f1 return the next available character from the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -. If a character is available, the return variable is: +. If a character is available, the return }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is: \par \par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 (1 << TMXR_V_VA\hich\af2\dbch\af31505\loch\f2 LID) | character \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 If a BREAK occurred on the line, SCPE_BREAK will be ORed into the return variable. }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -If no character is available, the return variable is 0. +If no character is available, the return }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 value}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is 0. \par \par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_poll_rx}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 \endash \loch\f1 poll for input available on the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . @@ -2491,8 +2739,8 @@ to the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hi return the number of characters in the transmit queue of the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9308345 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9308345 -\hich\af1\dbch\af31505\loch\f1 tmxr_send_buffered_data}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 (TMLN *lp) \hich\f1 \endash \loch\f1 flush any buffered data for the line described by }{\rtlch\fcs1 \ai\af1 -\ltrch\fcs0 \i\f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 . +\hich\af1\dbch\af31505\loch\f1 tmxr_send_buff\hich\af1\dbch\af31505\loch\f1 ered_data}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 (TMLN *lp) \hich\f1 \endash \loch\f1 flush any buffered data for the line described by +}{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 . \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp, UNIT *uptr, char *cptr) \hich\f1 \endash \loch\f1 attach the port contained in character string }{\rtlch\fcs1 \ai\af1 @@ -2500,26 +2748,26 @@ to the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hi \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t\hich\af1\dbch\af31505\loch\f1 mxr_open_master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_open_maste\hich\af1\dbch\af31505\loch\f1 r}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp, char *cptr) \hich\f1 \endash \loch\f1 associate the port contained in character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . This routine is a subset of }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par \par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (TMXR *mp, UNIT *uptr) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 detach all connections for the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 . + (TMXR *mp, UNIT *uptr) \hich\f1 \endash \loch\f1 detach all connections for the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 and unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 . \par \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_close_master}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 \endash \loch\f1 close the master port for the terminals described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 mp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . This routine is a subset of}{ \rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 . \par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_ex}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (t_value *vptr, t_addr addr, -\hich\af1\dbch\af31505\loch\f1 UNIT *uptr, int32 sw) \hich\f1 \endash \loch\f1 stub examine routine, needed because the extra terminals are marked as attached; always returns an error. +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_ex}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 + (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 stub examine routine, needed because the extra terminals are marked as attached; always returns an error. \par \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_dep}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (t_value val, t_addr addr, UNIT *uptr, int32 sw) \hich\f1 \endash \loch\f1 stub deposit routine, needed because the extra terminals a\hich\af1\dbch\af31505\loch\f1 re marked as detached; always returns an error. + (t_value val, t_addr addr, UNIT *uptr, int32 sw) \hich\f1 \endash \loch\f1 stub deposit routine, needed because the extra terminals are marked as detached; \hich\af1\dbch\af31505\loch\f1 always returns an error. \par }\pard \ltrpar\ql \li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par }\pard \ltrpar\ql \fi360\li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0\pararsid9308345 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 tmxr_msg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 (SOCKET sock, char *msg) \hich\f1 \endash \loch\f1 output character string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid9308345 @@ -2530,20 +2778,26 @@ to the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hi \hich\af1\dbch\af31505\loch\f1 msg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to line }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par +\par }\pard \ltrpar\ql \fi360\li360\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin360\itap0\pararsid2634434 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid2634434 +\hich\af1\dbch\af31505\loch\f1 tmxr_linemsg}{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 f}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 (TMLN *lp, }{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 const *fmt, ,,,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 ) \hich\f1 \endash \loch\f1 output }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 +\hich\af1\dbch\af31505\loch\f1 formatted }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 msg}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 to line }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 +\i\f1\insrsid2634434 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2634434 . +\par \par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_fconns}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (FILE *st, TMLN *lp, \hich\af1\dbch\af31505\loch\f1 int32 ln) \hich\f1 \endash \loch\f1 output connection status to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 + (FILE *st, TMLN *lp, int32 ln) \hich\f1 \endash \loch\f1 output conn\hich\af1\dbch\af31505\loch\f1 ection status to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for the line described by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If }{ \rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is >= 0, preface the output with the specified line number. \par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 void }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tmxr_fstats}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (FILE *st, TMLN *lp, int32 ln) \hich\f1 -\endash \loch\f1 output connection statistics to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for the line des -\hich\af1\dbch\af31505\loch\f1 cribed by }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 -\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is >= 0, preface the output with the specified line number. +\endash \loch\f1 output connection statistics to stream }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 for the line described by }{ +\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 lp}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . If }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 ln}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is\hich\af1\dbch\af31505\loch\f1 >= 0, preface the output with the specified line number. \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 \hich\af1\dbch\af31505\loch\f1 tstat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid9308345\charrsid2698330 \hich\af1\dbch\af31505\loch\f1 tmxr_set_log}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9308345 -\hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *mp) \hich\f1 \endash \loch\f1 enable logging of a line of the multipleser described by mp to the filename pointed to by cptr. If uptr is \hich\af1\dbch\af31505\loch\f1 -NULL, then val indicates the line number; otherwise, the unit number within the associated device implies the line number. This function may be used as an MTAB validation routine. +\hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *mp) \hich\f1 \endash \loch\f1 enable logging of a line of the multipleser described by mp to the filename pointed to by cptr. If uptr is NULL, then val indicate +\hich\af1\dbch\af31505\loch\f1 s the line number; otherwise, the unit number within the associated device implies the line number. This function may be used as an MTAB validation routine. \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid2698330 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1 tstat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid2698330\charrsid5979563 \hich\af1\dbch\af31505\loch\f1 tmxr_set_}{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid2698330 \hich\af1\dbch\af31505\loch\f1 no}{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\f1\insrsid2698330\charrsid5979563 @@ -2600,26 +2854,22 @@ desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1 outputs the number of lines in the terminal multiplexer (TMXR *) I to stream I. \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \par }\pard \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid7674256 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid7674256 -\hich\af1\dbch\af31505\loch\f1 tmxr_set_modem_control_passthru}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 - Enables modem control passthru behaviors, and disables internal manipulation of DTR (&RTS) by tmxr apis. Enables the tmxr_set_get_modem_bits and tmxr_set_config_line apis. -\par -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 tmxr_set_modem_control_passthru}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 -\endash \loch\f1 Enables modem control passthr\hich\af1\dbch\af31505\loch\f1 u behaviors, and disables internal manipulation of DTR (&RTS) by tmxr apis. Enables the tmxr_set_get_modem_bits and tmxr_set_config_line apis. +\hich\af1\dbch\af31505\loch\f1 tmxr_set_modem_control_passthru}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 \endash \loch\f1 Enables modem control passthru behaviors, and disables internal manipulat +\hich\af1\dbch\af31505\loch\f1 ion of DTR (&RTS) by tmxr apis. Enables the tmxr_set_get_modem_bits and tmxr_set_config_line apis. \par \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid7674256 \hich\af1\dbch\af31505\loch\f1 tmxr_clear_modem_control_passthru}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp) \hich\f1 -\endash \loch\f1 Disables modem control passthru behaviors, and enables in\hich\af1\dbch\af31505\loch\f1 ternal manipulation of DTR (&RTS) by tmxr apis. Disables the tmxr_set_get_modem_bits and tmxr_set_config_line apis. +\endash \loch\f1 Disables modem control passthru behaviors, and enables internal manipulation of DTR (&RTS) by tmxr apis. Disables the tmxr_set_get\hich\af1\dbch\af31505\loch\f1 _modem_bits and tmxr_set_config_line apis. \par \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid9462171\charrsid9462171 \hich\af1\dbch\af31505\loch\f1 tmxr_set_get_modem_bits}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 -\hich\af1\dbch\af31505\loch\f1 (TMLN *lp, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits) \hich\f1 \endash \loch\f1 For a line connected to a serial\hich\af1\dbch\af31505\loch\f1 - port on a TMXR device with modem_control_passthru enabled, then the bits_to_set and/or bits_to_clear (DTR and RTS) are changed and if incoming_bits is not NULL, then the current modem bits are returned (DCD,RNG,CTS, DSR).}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\insrsid7674256 +\hich\af1\dbch\af31505\loch\f1 (TMLN *lp, int32 bits_to_set, int32 bits_to_clear, int32 *incoming_bits) \hich\f1 \endash \loch\f1 For a line connected to a serial port on a TMXR device with modem_control_passthru enabled, then the bits_ +\hich\af1\dbch\af31505\loch\f1 to_set and/or bits_to_clear (DTR and RTS) are changed and if incoming_bits is not NULL, then the current modem bits are returned (DCD,RNG,CTS, DSR).}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid7674256 \par }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid9462171\charrsid9462171 \hich\af1\dbch\af31505\loch\f1 tmxr_set_config_line}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 (TML -\hich\af1\dbch\af31505\loch\f1 N *lp, char *config) \hich\f1 \endash \loch\f1 sets the line configuration (speed, parity, character size, stopbits) on a serial port. Config is a string of the form: 9600-8N1. +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid9462171\charrsid9462171 \hich\af1\dbch\af31505\loch\f1 tmxr_set_config_line}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 + (TMLN *lp, char *config) \hich\f1 \endash \loch\f1 sets the line configuration (speed, parity, charact\hich\af1\dbch\af31505\loch\f1 er size, stopbits) on a serial port. Config is a string of the form: 9600-8N1. \par \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \af1 \ltrch\fcs0 \b\insrsid9462171\charrsid3806017 \hich\af1\dbch\af31505\loch\f1 tmxr_set_line_unit}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 (TMXR *mp, int line, UNIT *uptr) }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid3806017 \loch\af1\dbch\af31505\hich\f1 \endash }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid3806017 -\hich\af1\dbch\af31505\loch\f1 Declare which unit polls for input on a \hich\af1\dbch\af31505\loch\f1 given line (only needed if the input polling unit is different than the unit provided when the multiplexer was attached.}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\hich\af1\dbch\af31505\loch\f1 Declare which unit polls for input on a given line (only needed if the input polling unit is different than the un\hich\af1\dbch\af31505\loch\f1 it provided when the multiplexer was attached.}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9462171 \par }\pard \ltrpar\s21\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid3806017 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid2698330 \par }\pard \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid8129972 @@ -2627,50 +2877,49 @@ desc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f The OS dependent serial I/O and socket routines should not need to be accessed by the terminal simulators. \par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par {\*\bkmkstart _Toc347546252}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355660}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.3\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Magnetic\hich\af1\dbch\af31505\loch\f1 Tape Emulation Library{\*\bkmkend _Toc347546252} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Magnetic Tape Emulation Library{\*\bkmkend _Toc356355660} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 \hich\f1 SIMH supports the use of emulated magnetic tapes. Magnetic tapes are emulated as disk files containing both data records and metadata markers; the format is fully described in the paper \'93\loch\f1 -SIMH Magtape Representation an\hich\af1\dbch\af31505\loch\f1 \hich\f1 d Handling\'94\loch\f1 -. SIMH provides a supporting library, sim_tape.c (and its header file, sim_tape.h), that abstracts handling of magnetic tapes. This allows support for multiple tape formats, without change to magnetic device simulators. +\par \hich\af1\dbch\af31505\loch\f1 \hich\f1 SIMH supports the use of emulated magnetic tapes. Magnetic tapes are emulated as disk files containing both data records and metadata markers; the format is fully described in the paper \'93\loch\f1 \hich\f1 +SIMH Magtape Representation and Handling\'94\loch\f1 . SIMH provides a support\hich\af1\dbch\af31505\loch\f1 i\hich\af1\dbch\af31505\loch\f1 +ng library, sim_tape.c (and its header file, sim_tape.h), that abstracts handling of magnetic tapes. This allows support for multiple tape formats, without change to magnetic device simulators. \par -\par \hich\af1\dbch\af31505\loch\f1 The magtape library do\hich\af1\dbch\af31505\loch\f1 es not require any special data structures. However, it does define some additional unit flags: +\par \hich\af1\dbch\af31505\loch\f1 The magtape library does not require any special data struct\hich\af1\dbch\af31505\loch\f1 ures. However, it does define some additional unit flags: \par \par \tab \hich\af1\dbch\af31505\loch\f1 MTUF_WLK\tab \tab unit is write locked \par -\par \hich\af1\dbch\af31505\loch\f1 If magtape simulators need to define private unit flags, those flags should begin at bit number MTUF_V_UF instead of UNIT_V_U\hich\af1\dbch\af31505\loch\f1 -F. The magtape library maintains the current magtape position in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pos}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field of the } -{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure. +\par \hich\af1\dbch\af31505\loch\f1 If magtape simulators need to define private unit flags, those flags should begin at bit number MTUF_V_UF instead of UNIT_V_UF. The magtape library maintains the \hich\af1\dbch\af31505\loch\f1 +current magtape position in the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 pos}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 field of the }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 +\b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 UNIT}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 structure. \par \par \hich\af1\dbch\af31505\loch\f1 Library sim_tape.c provides the following routines to support emulated magnetic tapes: \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 sim_tape_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, char *cptr) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 Attach tape unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 -\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 -\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Tape -\par \hich\af1\dbch\af31505\loch\f1 Simulators should call this routine, rather than the standard attach_unit routine, to allow for future expansion of format support. +\hich\af1\dbch\af31505\loch\f1 sim_tape_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, char *cptr) \hich\f1 \endash \loch\f1 Attach tape unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 uptr }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to file }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Tape +\par \hich\af1\dbch\af31505\loch\f1 Simulator\hich\af1\dbch\af31505\loch\f1 s should call this routine, rather than the standard attach_unit routine, to allow for future expansion of format support. \par \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_detach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash -\loch\f1 Detach tape unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 from its current fi\hich\af1\dbch\af31505\loch\f1 le. - +\loch\f1 Detach tape unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 from its current file. \par -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_set_fmt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 Set the tape format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_set_fmt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, +\hich\af1\dbch\af31505\loch\f1 char *cptr, void *desc) \hich\f1 \endash \loch\f1 Set the tape format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the format specified by string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_fmt}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1 Write the tape format for uni\hich\af1\dbch\af31505\loch\f1 t }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 -\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . + (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1 Write the tape format for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +\par \hich\af1\dbch\af31505\loch\f1 t_sta\hich\af1\dbch\af31505\loch\f1 t }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, int32 val, char *cptr, void *desc) \hich\f1 \endash \loch\f1 Set the tape capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the capacity, in MB, specified by string }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 cptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \loch\f1 Write the capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\hich\af1\dbch\af31505\loch\f1 to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . + (FILE *st, UNIT *uptr, int32 val, void *desc) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 Write the capacity for unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 +\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 to the file specified by descriptor }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 st}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par }\pard\plain \ltrpar\s21\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af1\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_rdrecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 @@ -2684,31 +2933,31 @@ F. The magtape library maintains the current magtape position in the }{\rtlch\f (UNIT *uptr, uint8 *buf, t_mtrlnt *tbc, t_mtrlnt max) \hich\f1 \endash \loch\f1 Reverse read the next record on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 into buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 buf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 of size }{ \rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 max}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Return the actual record size in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 -\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Note that\hich\af1\dbch\af31505\loch\f1 - the record is returned in forward order, that is, byte 0 of the record is stored in buf[0], and so on. +\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . Note that the record is \hich\af1\dbch\af31505\loch\f1 +returned in forward order, that is, byte 0 of the record is stored in buf[0], and so on. \par \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrrecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, uint8 buf, t_mtrlnt tbc) \hich\f1 \endash \loch\f1 Write buffer }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 of size }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 as the next record on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape sprecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (\hich\af1\dbch\af31505\loch\f1 -UNIT *uptr, t_mtrlnt *tbc) \hich\f1 \endash \loch\f1 Space unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape sprecf}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, t_m +\hich\af1\dbch\af31505\loch\f1 trlnt *tbc) \hich\f1 \endash \loch\f1 Space unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 forward one record. The size of the record is returned in }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tbc}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_sprecr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr, t_mtrlnt *tbc) \hich\f1 \endash \loch\f1 Space unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 reverse one record. The size of the record is returned in tbc. \par -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_t\hich\af1\dbch\af31505\loch\f1 ape_wrtmk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (UNIT *uptr) \hich\f1 \endash \loch\f1 Write a tape mark on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrtmk}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT +\hich\af1\dbch\af31505\loch\f1 *uptr) \hich\f1 \endash \loch\f1 Write a tape mark on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 . \par \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wreom}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash \loch\f1 Write an end-of-medium marker on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (this effectively erases the rest of the tape). \par \par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_wrgap}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (UNIT *uptr, uint32 gaplen, uint32 bpi) \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 Write an erase gap on unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 + (UNIT *uptr, uint32 gaplen, uint32 bpi) \hich\f1 \endash \loch\f1 Write an erase gap o\hich\af1\dbch\af31505\loch\f1 n unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 gaplen}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 tenths of an inch in length at a tape density of }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 bpi}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 bits per inch. \par @@ -2716,8 +2965,8 @@ UNIT *uptr, t_mtrlnt *tbc) \hich\f1 \endash \loch\f1 Space unit }{\rtlch\fcs1 \ \loch\f1 Rewind unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . This operation succeeds whether or not the unit is attached to a file. \par -\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape\hich\af1\dbch\af31505\loch\f1 _reset}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - (UNIT *uptr) \hich\f1 \endash \loch\f1 Reset unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 +\par \hich\af1\dbch\af31505\loch\f1 t_stat }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_reset}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash +\hich\af1\dbch\af31505\loch\f1 Reset unit }{\rtlch\fcs1 \ai\af1 \ltrch\fcs0 \i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 uptr}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 . This routine should be called when a tape unit is reset. \par \par \hich\af1\dbch\af31505\loch\f1 t_bool }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_bot}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 (UNIT *uptr) \hich\f1 \endash @@ -2732,24 +2981,24 @@ UNIT *uptr, t_mtrlnt *tbc) \hich\f1 \endash \loch\f1 Space unit }{\rtlch\fcs1 \ \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Sim_tape_attach}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_detach, sim_tape_set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -sim_tape_show_fmt, sim_tape_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , and\hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -sim_tape_show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 - return standard SCP status codes; the other magtape library routines return return private codes for success and failure. The currently defined magtape status codes are: +sim_tape_show_fmt, sim_tape_set_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 , and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_capac}{\rtlch\fcs1 \af1 +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 return s\hich\af1\dbch\af31505\loch\f1 +tandard SCP status codes; the other magtape library routines return return private codes for success and failure. The currently defined magtape status codes are: \par \par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_OK\tab \tab operation successful -\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_UNATT\tab \tab unit is not attache\hich\af1\dbch\af31505\loch\f1 d to a file -\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_FMT\tab \tab unit specifies an unsupported tape file format +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_UNATT\tab \tab unit is not attached to a file +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_FMT\tab \tab \hich\af1\dbch\af31505\loch\f1 unit specifies an unsupported tape file format \par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_IOERR\tab \tab host operating system I/O error during operation \par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_INVRL\tab \tab invalid record length (exceeds maximum allowed) \par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_RECE\tab \tab record header contains error flag -\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_TMK\tab \tab tape m\hich\af1\dbch\af31505\loch\f1 ark encountered -\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_BOT\tab \tab beginning of tape encountered during reverse operation +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_TMK\tab \tab tape mark encountered +\par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_B\hich\af1\dbch\af31505\loch\f1 OT\tab \tab beginning of tape encountered during reverse operation \par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_EOM\tab \tab end of medium encountered \par \tab \hich\af1\dbch\af31505\loch\f1 MTSE_WRP\tab \tab write protected unit during write operation \par \par }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Sim_tape_set_fmt,}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_tape_show_fmt, sim_tape_set_capac, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 and }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 -sim_tape_show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\af1\dbch\af31505\loch\f1 should be referenced by an entry in the tape device\hich\f1 \rquote \loch\f1 s modifier list, as follows: +sim_tape_show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 should be referenced by\hich\af1\dbch\af31505\loch\f1 an entry in the tape device\hich\f1 \rquote \loch\f1 s modifier list, as follows: \par \par }{\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 MTAB tape_mod[] = \{ \par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 MTAB_XTD|MTAB_VDV, 0, \'93\loch\f2 \hich\f2 FORMAT\'94\loch\f2 @@ -2757,18 +3006,19 @@ sim_tape_show_capac}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\d \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \tab \hich\af2\dbch\af31505\loch\f2 \tab &sim_tape_set_fmt, &sim_tape_show_fmt, NULL \}, \par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \{\hich\af2\dbch\af31505\loch\f2 \hich\f2 MTAB_XTD|MTAB_VUN, 0, \'93\loch\f2 \hich\f2 CAPACITY\'94\loch\f2 \hich\f2 , \'93\loch\f2 \hich\f2 CAPACITY\'94, -\par }\pard \ltrpar\ql \li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 &sim_tape_set_capac, &sim_tape_show_capac, NULL \}\hich\f2 , \'85 +\par }\pard \ltrpar\ql \li1440\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin1440\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \hich\af2\dbch\af31505\loch\f2 &sim_tape_set_capac, &sim_tap\hich\af2\dbch\af31505\loch\f2 e_show_capac, NULL \} +\hich\f2 , \'85 \par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid4550150 \}\hich\af2\dbch\af31505\loch\f2 ; -\par {\*\bkmkstart _Toc347546253}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 6.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355661}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid9973523 \hich\af1\dbch\af31505\loch\f1 6.4\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0\pararsid9973523 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 { -\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9973523 \hich\af1\dbch\af31505\loch\f1 Disk Emulation Library{\*\bkmkend _Toc347546253} +\rtlch\fcs1 \af1 \ltrch\fcs0 \insrsid9973523 \hich\af1\dbch\af31505\loch\f1 Disk Emulation Library{\*\bkmkend _Toc356355661} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9973523 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 -\par \hich\af1\dbch\af31505\loch\f1 SIMH supports the use of disk drives. Disk drives as disk files containing both data records and metadata markers; the format is fully describe\hich\af1\dbch\af31505\loch\f1 \hich\f1 d in the paper \'93\loch\f1 \hich\f1 -SIMH Magtape Representation and Handling\'94\loch\f1 . SIMH provides a supporting library, sim_disk.c (and its header file, sim_disk.h), that abstracts handling of disk drives tapes. This allows support for disk formats, without change to magnetic d -\hich\af1\dbch\af31505\loch\f1 e\hich\af1\dbch\af31505\loch\f1 vice simulators. +\par \hich\af1\dbch\af31505\loch\f1 \hich\f1 SIMH supports the use of disk drives. Disk drives as disk files containing both data records and metadata markers; the format is fully described in the paper \'93\loch\f1 SIMH Magtape Re +\hich\af1\dbch\af31505\loch\f1 \hich\f1 presentation and Handling\'94\loch\f1 +. SIMH provides a supporting library, sim_disk.c (and its header file, sim_disk.h), that abstracts handling of disk drives tapes. This allows support for disk formats, without change to magnetic device simulators. \par -\par \hich\af1\dbch\af31505\loch\f1 The disk library does not require any special data structures. However, it does define some additional unit flags: +\par \hich\af1\dbch\af31505\loch\f1 The disk libr\hich\af1\dbch\af31505\loch\f1 ary does not require any special data structures. However, it does define some additional unit flags: \par \par \tab \hich\af1\dbch\af31505\loch\f1 DKUF_WLK\tab \tab unit is write locked \par @@ -2908,9 +3158,9 @@ _set_capac, }{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 \hich\af1\dbch\af3 \par }\pard \ltrpar\ql \fi720\li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0\pararsid9973523 {\rtlch\fcs1 \af2 \ltrch\fcs0 \f2\insrsid9973523 \}\hich\af2\dbch\af31505\loch\f2 ; \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0\pararsid9973523 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid9973523 -\par {\*\bkmkstart _Toc347546254}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.5\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar +\par {\*\bkmkstart _Toc356355662}{\listtext\pard\plain\ltrpar \s2 \rtlch\fcs1 \ab\ai\af0 \ltrch\fcs0 \b\i\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 6.5\tab}}\pard\plain \ltrpar\s2\ql \fi-390\li390\ri0\sb240\sa60\keepn\widctlpar \jclisttab\tx390\wrapdefault\faauto\ls1\ilvl1\outlinelevel1\adjustright\rin0\lin390\itap0 \rtlch\fcs1 \ab\ai\af1\afs24\alang1025 \ltrch\fcs0 \b\i\fs24\lang1033\langfe1033\loch\af1\hich\af1\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 -\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Breakpoint Support{\*\bkmkend _Toc347546254} +\ltrch\fcs0 \insrsid4550150 \hich\af1\dbch\af31505\loch\f1 Breakpoint Support{\*\bkmkend _Toc356355662} \par }\pard\plain \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par \hich\af1\dbch\af31505\loch\f1 SCP provides underlying mechanisms to track multiple brea\hich\af1\dbch\af31505\loch\f1 kpoints of different types. Most VM\hich\f1 \rquote \loch\f1 @@ -2925,13 +3175,13 @@ s implement at least instruction execution breakpoints (type E); but a VM might \par }\pard\plain \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 \rtlch\fcs1 \af0\afs20\alang1025 \ltrch\fcs0 \fs20\lang1033\langfe1033\loch\af0\hich\af0\dbch\af31505\cgrid\langnp1033\langfenp1033 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \tab }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_dflt}{\rtlch\fcs1 \af1 -\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 \endash \hich\af1\dbch\af31505\loch\f1 initialized by the VM to the mask for the default breakpoint type. +\ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 \endash \loch\f1 initialized by\hich\af1\dbch\af31505\loch\f1 the VM to the mask for the default breakpoint type. \par \par }\pard \ltrpar\ql \li720\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin720\itap0 {\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 \hich\f1 \endash \loch\f1 maintained by SCP, providing a bit mask summary of whether any breakpoints of a particular type have been defined. \par }\pard \ltrpar\ql \li0\ri0\widctlpar\wrapdefault\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 -\par \hich\af1\dbch\af31505\loch\f1 If the VM only implements one type of breakpoint, then }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 s\hich\af1\dbch\af31505\loch\f1 im_brk_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 -\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 is non-zero if any breakpoints are set. +\par \hich\af1\dbch\af31505\loch\f1 If the VM only implements one type of breakpoint, then }{\rtlch\fcs1 \ab\af1 \ltrch\fcs0 \b\f1\insrsid4550150 \hich\af1\dbch\af31505\loch\f1 sim_brk_summ}{\rtlch\fcs1 \af1 \ltrch\fcs0 \f1\insrsid4550150 +\hich\af1\dbch\af31505\loch\f1 is \hich\af1\dbch\af31505\loch\f1 non-zero if any breakpoints are set. \par \par \hich\af1\dbch\af31505\loch\f1 To test whether a breakpoint of particular type is set for an address, the VM calls \par @@ -3059,18 +3309,18 @@ fffffffffffffffffdffffff04000000feffffff05000000fefffffffeffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff -ffffffffffffffffffffffffffffffff52006f006f007400200045006e00740072007900000000000000000000000000000000000000000000000000000000000000000000000000000000000000000016000500ffffffffffffffff010000000c6ad98892f1d411a65f0040963251e50000000000000000000000006076 -291d4901ce010300000080020000000000004d0073006f004400610074006100530074006f0072006500000000000000000000000000000000000000000000000000000000000000000000000000000000001a000101ffffffffffffffff0200000000000000000000000000000000000000000000006076291d4901ce01 -6076291d4901ce01000000000000000000000000d4003500d200c1004100da00d80046003200d40053004600cb0050004f004b00560051004e004a00d700c0003d003d000000000000000000000000000000000032000101ffffffffffffffff0300000000000000000000000000000000000000000000006076291d4901 -ce016076291d4901ce010000000000000000000000004900740065006d0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a000201ffffffff04000000ffffffff000000000000000000000000000000000000000000000000 +ffffffffffffffffffffffffffffffff52006f006f007400200045006e00740072007900000000000000000000000000000000000000000000000000000000000000000000000000000000000000000016000500ffffffffffffffff010000000c6ad98892f1d411a65f0040963251e500000000000000000000000010e8 +14bd5f51ce010300000080020000000000004d0073006f004400610074006100530074006f0072006500000000000000000000000000000000000000000000000000000000000000000000000000000000001a000101ffffffffffffffff02000000000000000000000000000000000000000000000010e814bd5f51ce01 +10e814bd5f51ce01000000000000000000000000db005a00c3004d003100d300d500d500df00c400c200530046003100ca004d00cc0044004f0049004300c0003d003d000000000000000000000000000000000032000101ffffffffffffffff03000000000000000000000000000000000000000000000010e814bd5f51 +ce0110e814bd5f51ce010000000000000000000000004900740065006d0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000a000201ffffffff04000000ffffffff000000000000000000000000000000000000000000000000 00000000000000000000000000000000d800000000000000010000000200000003000000feffffff0500000006000000070000000800000009000000feffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff3c623a536f75726365732053656c65637465645374796c653d225c4150412e58534c22205374796c654e616d653d224150412220786d6c6e733a623d22687474703a2f2f736368656d61732e6f70656e786d6c666f726d6174732e6f7267 2f6f6666696365446f63756d656e742f323030362f6269626c696f6772617068792220786d6c6e733d22687474703a2f2f736368656d61732e6f70656e786d6c666f726d6174732e6f72672f6f6666696365446f63756d656e742f323030362f6269626c696f677261706879223e3c2f623a536f75726365733e00000000 -0000000000000000000000000000000000000000000000000000000000000000000000003c3f786d6c2076657273696f6e3d22312e302220656e636f64696e673d225554462d3822207374616e64616c6f6e653d226e6f223f3e0d0a3c64733a6461746173746f72654974656d2064733a6974656d49443d227b30334131 -464344312d303541452d343437332d383541432d4633384135353033343944457d2220786d6c6e733a64733d22687474703a2f2f736368656d61732e6f70656e786d6c666f726d6174732e6f72672f6f6666696365446f63756d656e742f323030362f637573746f6d586d6c223e3c64733a736368656d61526566733e3c +0000000000000000000000000000000000000000000000000000000000000000000000003c3f786d6c2076657273696f6e3d22312e302220656e636f64696e673d225554462d3822207374616e64616c6f6e653d226e6f223f3e0d0a3c64733a6461746173746f72654974656d2064733a6974656d49443d227b36464343 +393845442d373533442d343846452d393231352d4241384342303333383830417d2220786d6c6e733a64733d22687474703a2f2f736368656d61732e6f70656e786d6c666f726d6174732e6f72672f6f6666696365446f63756d656e742f323030362f637573746f6d586d6c223e3c64733a736368656d61526566733e3c 64733a736368656d615265662064733a7572693d22687474703a2f2f736368656d61732e6f70656e500072006f007000650072007400690065007300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000016000200ffffffffffffffffffffffff000000000000 0000000000000000000000000000000000000000000000000000000000000400000055010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffff00000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffff0000 diff --git a/sim_tmxr.c b/sim_tmxr.c index a368d87b..09995f40 100644 --- a/sim_tmxr.c +++ b/sim_tmxr.c @@ -437,9 +437,9 @@ lp->dstb = 0; /* default bin mode */ lp->rxbpr = lp->rxbpi = lp->rxcnt = 0; /* init receive indexes */ if (!lp->txbfd) /* if not buffered */ lp->txbpr = lp->txbpi = lp->txcnt = 0; /* init transmit indexes */ -memset (lp->rbr, 0, TMXR_MAXBUF); /* clear break status array */ +memset (lp->rbr, 0, sizeof(lp->rbr)); /* clear break status array */ lp->txdrp = 0; -if (lp->mp->modem_control) +if (lp->modem_control) lp->modembits = TMXR_MDM_CTS | TMXR_MDM_DSR; if (!lp->mp->buffered) { lp->txbfd = 0; @@ -721,6 +721,8 @@ for (i=0; ilines; ++i) { sprintf (growstring(&tptr, 32), "%sLine=%d", *tptr ? "," : "", i); else sprintf (growstring(&tptr, 32), "%s", *tptr ? "," : ""); + if (lp->modem_control != mp->modem_control) + sprintf (growstring(&tptr, 32), ",%s", mp->modem_control ? "Modem" : "NoModem"); if (lp->destination) { if (lp->serport) { char portname[CBUFSIZE]; @@ -913,17 +915,25 @@ for (i = 0; i < mp->lines; i++) { /* check each line in se } } if (lp->conn == 0) { /* is the line available? */ - tmxr_init_line (lp); /* init line */ - lp->conn = TRUE; /* record connection */ - lp->sock = newsock; /* save socket */ - lp->ipad = address; /* ip address */ - if (!lp->notelnet) { - sim_write_sock (newsock, (char *)mantra, sizeof(mantra)); - tmxr_debug (TMXR_DBG_XMT, lp, "Sending", (char *)mantra, sizeof(mantra)); + if ((!lp->modem_control) || (lp->modembits & TMXR_MDM_DTR)) { + tmxr_init_line (lp); /* init line */ + lp->conn = TRUE; /* record connection */ + lp->sock = newsock; /* save socket */ + lp->ipad = address; /* ip address */ + if (!lp->notelnet) { + sim_write_sock (newsock, (char *)mantra, sizeof(mantra)); + tmxr_debug (TMXR_DBG_XMT, lp, "Sending", (char *)mantra, sizeof(mantra)); + } + tmxr_report_connection (mp, lp); + lp->cnms = sim_os_msec (); /* time of connection */ + return i; + } + else { + tmxr_msg (newsock, "Line connection not available\r\n"); + tmxr_debug_connect_line (lp, "tmxr_poll_conn() - Line connection not available"); + sim_close_sock (newsock, 0); + free (address); } - tmxr_report_connection (mp, lp); - lp->cnms = sim_os_msec (); /* time of connection */ - return i; } else { tmxr_msg (newsock, "Line connection busy\r\n"); @@ -945,7 +955,7 @@ for (i = 0; i < mp->lines; i++) { /* check each line in se /* Check for needed outgoing connection initiation */ if (lp->destination && (!lp->sock) && (!lp->connecting) && (!lp->serport) && - (!mp->modem_control || (lp->modembits & TMXR_MDM_DTR))) { + (!lp->modem_control || (lp->modembits & TMXR_MDM_DTR))) { sprintf (msg, "tmxr_poll_conn() - establishing outgoing connection to: %s", lp->destination); tmxr_debug_connect_line (lp, msg); lp->connecting = sim_connect_sock (lp->destination, "localhost", NULL); @@ -969,7 +979,7 @@ static t_stat tmxr_reset_ln_ex (TMLN *lp, t_bool closeserial) { char msg[512]; -tmxr_debug_trace_line (lp, "tmxr_reset_ln_ex)"); +tmxr_debug_trace_line (lp, "tmxr_reset_ln_ex()"); if (lp->txlog) fflush (lp->txlog); /* flush log */ @@ -992,7 +1002,7 @@ if (lp->serport) { lp->xmte = 1; } else - if (!lp->mp->modem_control) { /* serial connection? */ + if (!lp->modem_control) { /* serial connection? */ sim_control_serial (lp->serport, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL);/* drop DTR and RTS */ sim_os_ms_sleep (TMXR_DTR_DROP_TIME); sim_control_serial (lp->serport, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL);/* raise DTR and RTS */ @@ -1013,7 +1023,7 @@ if ((lp->destination) && (!lp->serport)) { sim_close_sock (lp->connecting, 0); lp->connecting = 0; } - if ((!lp->mp->modem_control) || (lp->modembits & TMXR_MDM_DTR)) { + if ((!lp->modem_control) || (lp->modembits & TMXR_MDM_DTR)) { sprintf (msg, "tmxr_reset_ln_ex() - connecting to %s", lp->destination); tmxr_debug_connect_line (lp, msg); lp->connecting = sim_connect_sock (lp->destination, "localhost", NULL); @@ -1058,10 +1068,33 @@ return tmxr_reset_ln_ex (lp, FALSE); tmxr_set_config_line APIs. */ +static t_stat tmxr_clear_modem_control_passthru_state (TMXR *mp, t_bool state) +{ +int i; + +if (mp->modem_control == state) + return SCPE_OK; +if (mp->master) + return SCPE_ALATT; +for (i=0; ilines; ++i) { + TMLN *lp; + + lp = mp->ldsc + i; + if ((lp->master) || + (lp->sock) || + (lp->connecting) || + (lp->serport)) + return SCPE_ALATT; + } +mp->modem_control = state; +for (i=0; ilines; ++i) + mp->ldsc[i].modem_control = state; +return SCPE_OK; +} + t_stat tmxr_set_modem_control_passthru (TMXR *mp) { -mp->modem_control = TRUE; -return SCPE_OK; +return tmxr_clear_modem_control_passthru_state (mp, TRUE); } /* Disable modem control pass thru @@ -1087,24 +1120,7 @@ return SCPE_OK; */ t_stat tmxr_clear_modem_control_passthru (TMXR *mp) { -int i; - -if (!mp->modem_control) - return SCPE_OK; -if (mp->master) - return SCPE_ALATT; -for (i=0; ilines; ++i) { - TMLN *lp; - - lp = mp->ldsc + i; - if ((lp->master) || - (lp->sock) || - (lp->connecting) || - (lp->serport)) - return SCPE_ALATT; - } -mp->modem_control = FALSE; -return SCPE_OK; +return tmxr_clear_modem_control_passthru_state (mp, FALSE); } /* Manipulate the modem control bits of a specific line @@ -1153,7 +1169,7 @@ if (sim_deb && lp->mp && lp->mp->dptr) { } if (incoming_bits) *incoming_bits = incoming_state; -if (lp->mp && lp->mp->modem_control) { /* This API ONLY works on modem_control enabled multiplexers */ +if (lp->mp && lp->modem_control) { /* This API ONLY works on modem_control enabled multiplexer lines */ if (bits_to_set | bits_to_clear) { /* Anything to do? */ if (lp->serport) return sim_control_serial (lp->serport, bits_to_set, bits_to_clear, incoming_bits); @@ -1185,7 +1201,7 @@ t_stat tmxr_set_config_line (TMLN *lp, char *config) t_stat r; tmxr_debug_trace_line (lp, "tmxr_set_config_line()"); -if (!lp->mp->modem_control) /* This API ONLY works on modem_control enabled multiplexers */ +if (!lp->modem_control) /* This API ONLY works on modem_control enabled multiplexer lines */ return SCPE_IERR; if (lp->serport) r = sim_config_serial (lp->serport, config); @@ -1594,13 +1610,14 @@ char tbuf[CBUFSIZE], listen[CBUFSIZE], destination[CBUFSIZE], SOCKET sock; SERHANDLE serport; char *tptr = cptr; -t_bool nolog, notelnet, listennotelnet, unbuffered; +t_bool nolog, notelnet, listennotelnet, unbuffered, modem_control; TMLN *lp; t_stat r = SCPE_ARG; for (i = 0; i < mp->lines; i++) { /* initialize lines */ lp = mp->ldsc + i; lp->mp = mp; /* set the back pointer */ + lp->modem_control = mp->modem_control; } tmxr_debug_trace (mp, "tmxr_open_master()"); while (*tptr) { @@ -1612,6 +1629,7 @@ while (*tptr) { memset(port, '\0', sizeof(port)); memset(option, '\0', sizeof(option)); nolog = notelnet = listennotelnet = unbuffered = FALSE; + modem_control = mp->modem_control; while (*tptr) { tptr = get_glyph_nc (tptr, tbuf, ','); if (!tbuf[0]) @@ -1660,6 +1678,18 @@ while (*tptr) { nolog = TRUE; continue; } + if (0 == MATCH_CMD (gbuf, "NOMODEM")) { + if ((NULL != cptr) && ('\0' != *cptr)) + return SCPE_2MARG; + modem_control = FALSE; + continue; + } + if (0 == MATCH_CMD (gbuf, "MODEM")) { + if ((NULL != cptr) && ('\0' != *cptr)) + return SCPE_2MARG; + modem_control = TRUE; + continue; + } if (0 == MATCH_CMD (gbuf, "CONNECT")) { if ((NULL == cptr) || ('\0' == *cptr)) return SCPE_ARG; @@ -1710,6 +1740,8 @@ while (*tptr) { listennotelnet = TRUE; } if (line == -1) { + if (modem_control != mp->modem_control) + return SCPE_ARG; if (logfiletmpl[0]) { strncpy(mp->logfiletmpl, logfiletmpl, sizeof(mp->logfiletmpl)-1); for (i = 0; i < mp->lines; i++) { @@ -1935,6 +1967,7 @@ while (*tptr) { return SCPE_ARG; } } + lp->modem_control = modem_control; r = SCPE_OK; } } @@ -2731,10 +2764,12 @@ else { fprintf (st, " - %stelnet", lp->notelnet ? "no" : ""); if (lp->uptr && (lp->uptr != lp->mp->uptr)) fprintf (st, " - Unit: %s", sim_uname (lp->uptr)); + if (mp->modem_control != lp->modem_control) + fprintf(st, ", ModemControl=%s", lp->modem_control ? "enabled" : "disabled"); fprintf (st, "\n"); } if ((!lp->sock) && (!lp->connecting) && (!lp->serport) && (!lp->master)) { - if (mp->modem_control) + if (lp->modem_control) tmxr_fconns (st, lp, -1); continue; } @@ -2790,6 +2825,8 @@ for (i = 0; i < mp->lines; i++) { /* loop thru conn */ free (lp->port); lp->port = NULL; } + free (lp->txb); + lp->txb = NULL; lp->modembits = 0; } @@ -2888,6 +2925,10 @@ if (single_line) { /* Single Line Multiplexer */ fprintf (st, "The %s multiplexer may be connected to terminal emulators supporting the\n", dptr->name); fprintf (st, "Telnet protocol via sockets, or to hardware terminals via host serial\n"); fprintf (st, "ports.\n\n"); + if (mux->modem_control) { + fprintf (st, "The %s device is a full modem control device and therefore is capable of\n", dptr->name); + fprintf (st, "passing port configuration information and modem signals.\n"); + } fprintf (st, "A Telnet listening port can be configured with:\n\n"); fprintf (st, " sim> ATTACH %s {interface:}port\n\n", dptr->name); fprintf (st, "Line buffering can be enabled for the %s device with:\n\n", dptr->name); @@ -2906,6 +2947,14 @@ else { fprintf (st, "Telnet protocol via sockets, or to hardware terminals via host serial\n"); fprintf (st, "ports. Concurrent Telnet and serial connections may be mixed on a given\n"); fprintf (st, "multiplexer.\n\n"); + if (mux && mux->modem_control) { + fprintf (st, "The %s device is a full modem control device and therefore is capable of\n", dptr->name); + fprintf (st, "passing port configuration information and modem signals on all lines.\n"); + } + fprintf (st, "Modem Control signalling behaviors can be enabled/disabled on a specific\n"); + fprintf (st, "multiplexer line with:\n\n"); + fprintf (st, " sim> ATTACH %s Line=n,Modem\n", dptr->name); + fprintf (st, " sim> ATTACH %s Line=n,NoModem\n\n", dptr->name); fprintf (st, "A Telnet listening port can be configured with:\n\n"); fprintf (st, " sim> ATTACH %s {interface:}port\n\n", dptr->name); if (mux) @@ -2961,7 +3010,12 @@ fprintf (st, "As an example:\n\n"); fprintf (st, " 9600-8n1\n\n"); fprintf (st, "The supported rates, sizes, and parity options are host-specific. If\n"); fprintf (st, "a configuration string is not supplied, then the default of 9600-8N1\n"); -fprintf (st, "is used.\n\n"); +fprintf (st, "is used.\n"); +fprintf (st, "Note: The serial port configuration option is only available on multiplexer\n"); +fprintf (st, " lines which are not operating with full modem control behaviors enabled.\n"); +fprintf (st, " Lines with full modem control behaviors enabled have all of their\n"); +fprintf (st, " configuration managed by the Operating System running within the\n"); +fprintf (st, " simulator.\n\n"); fprintf (st, "An attachment to a serial port with the '-V' switch will cause a\n"); fprintf (st, "connection message to be output to the connected serial port.\n"); fprintf (st, "This will help to confirm the correct port has been connected and\n"); @@ -3152,7 +3206,7 @@ if (lp->cnms) { else fprintf (st, " Line disconnected\n"); -if (lp->mp->modem_control) { +if (lp->modem_control) { fprintf (st, " Modem Bits: %s%s%s%s%s%s\n", (lp->modembits & TMXR_MDM_DTR) ? "DTR " : "", (lp->modembits & TMXR_MDM_RTS) ? "RTS " : "", (lp->modembits & TMXR_MDM_DCD) ? "DCD " : "", @@ -3525,7 +3579,7 @@ if (mp == NULL) return SCPE_IERR; for (i = any = 0; i < mp->lines; i++) { if ((mp->ldsc[i].sock != 0) || - (mp->ldsc[i].serport != 0) || mp->modem_control) { + (mp->ldsc[i].serport != 0) || mp->ldsc[i].modem_control) { if ((mp->ldsc[i].sock != 0) || (mp->ldsc[i].serport != 0)) any++; if (val) diff --git a/sim_tmxr.h b/sim_tmxr.h index 306304dd..4ed65f9f 100644 --- a/sim_tmxr.h +++ b/sim_tmxr.h @@ -117,6 +117,7 @@ struct tmln { int32 txdrp; /* xmt drop count */ int32 txbsz; /* xmt buffer size */ int32 txbfd; /* xmt buffered flag */ + t_bool modem_control; /* line supports modem control behaviors */ int32 modembits; /* modem bits which are currently set */ FILE *txlog; /* xmt log file */ FILEREF *txlogref; /* xmt log file reference */