diff --git a/AltairZ80/altairz80_sys.c b/AltairZ80/altairz80_sys.c index 6e526027..1158b344 100644 --- a/AltairZ80/altairz80_sys.c +++ b/AltairZ80/altairz80_sys.c @@ -60,6 +60,11 @@ extern DEVICE selchan_dev; extern DEVICE ss1_dev; extern DEVICE if3_dev; extern DEVICE i8272_dev; +extern DEVICE ibc_dev; +extern DEVICE ibc_hdc_dev; +extern DEVICE ibc_smd_dev; +extern DEVICE ibctimer_device; +extern DEVICE ibcrtctimer_device; extern DEVICE mdriveh_dev; extern DEVICE switchcpu_dev; @@ -127,6 +132,12 @@ DEVICE *sim_devices[] = { &disk1a_dev, &disk2_dev, &disk3_dev, &ss1_dev, &mdriveh_dev, &selchan_dev, &if3_dev, /* Cromemco Devices */ &cromfdc_dev, + /* Integrated Business Computers (IBC) Devices */ + &ibc_dev, + &ibctimer_device, + &ibcrtctimer_device, + &ibc_hdc_dev, + &ibc_smd_dev, /* IMSAI Devices */ &fif_dev, /* Micropolis Devices */ diff --git a/AltairZ80/ibc.c b/AltairZ80/ibc.c new file mode 100644 index 00000000..538ae0eb --- /dev/null +++ b/AltairZ80/ibc.c @@ -0,0 +1,2236 @@ +/************************************************************************* + * * + * Copyright (c) 2021-2023 Howard M. Harte. * + * https://github.com/hharte * + * * + * Permission is hereby granted, free of charge, to any person obtaining * + * a copy of this software and associated documentation files (the * + * "Software"), to deal in the Software without restriction, including * + * without limitation the rights to use, copy, modify, merge, publish, * + * distribute, sublicense, and/or sell copies of the Software, and to * + * permit persons to whom the Software is furnished to do so, subject to * + * the following conditions: * + * * + * The above copyright notice and this permission notice shall be * + * included in all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON- * + * INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE * + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * + * SOFTWARE. * + * * + * Except as contained in this notice, the names of The Authors shall * + * not be used in advertising or otherwise to promote the sale, use or * + * other dealings in this Software without prior written authorization * + * from the Authors. * + * * + * Module Description: * + * Integrated Business Computers (IBC) Middi Cadet HP and Megastar * + * module for SIMH. * + * * + * This module is a wrapper around the wd179x FDC module, and adds the * + * IBC-specific registers as well as the Boot ROM. * + * * + *************************************************************************/ + +#include "altairz80_defs.h" +#include "sim_defs.h" /* simulator definitions */ +#include "wd179x.h" + +#define DEV_NAME "IBC" + +/* Debug flags */ +#define ERROR_MSG (1 << 0) +#define DRIVE_MSG (1 << 1) +#define PIO_MSG (1 << 2) +#define SBD_MSG (1 << 3) +#define RTC_MSG (1 << 4) +#define BANK_MSG (1 << 5) +#define UART_MSG (1 << 6) +#define CACHE_MSG (1 << 7) +#define UNHANDLED_IO_MSG (1 << 8) +#define FIFO_MSG (1 << 9) +#define DIPSW_MSG (1 << 10) +#define VERBOSE_MSG (1 << 11) + +#define IBC_MAX_UNITS (4) +#define IBC_NUM_SIO 16 /* Number of serial ports. */ +#define IBC_ROM_SIZE (8 * 1024) +#define IBC_ROM_ADDR_MASK (IBC_ROM_SIZE - 1) +#define FDC_FIFO_LEN (1024) +#define FDC_FIFO_MASK (FDC_FIFO_LEN - 1) + +#define IBC_SW_E_DEFAULT_VALUE 0xFF + +typedef enum ibc_model { + ibc_mcc = 0, + ibc_scc +} ibc_model_t; + +typedef struct { + PNP_INFO pnp; /* Plug and Play */ + uint8 rom_disabled; /* TRUE if ROM has been disabled */ + ibc_model_t model; + uint8 dipsw_E; /* 8-position DIP switch at location E. */ + uint8* cache; /* IBC CACHE storage */ + uint8 param; + uint8 head_sel; + uint8 autowait; + uint8 rtc; + uint8 imask; /* Interrupt Mask Register */ + uint8 ipend; /* Interrupt Pending Register */ + uint32 cache_wbase; + uint32 cache_rbase; + uint8 cache_index; + uint8 fdc_fifo[FDC_FIFO_LEN]; + uint16 fdc_fifo_rd_index; +} IBC_INFO; + +extern WD179X_INFO_PUB *wd179x_infop; + +extern t_stat set_membase(UNIT *uptr, int32 val, CONST char *cptr, void *desc); +extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc); +extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc); +extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc); +extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type, + int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap); +extern void setBankSelect(const int32 b); +extern uint8 GetBYTEWrapper(const uint32 Addr); + +extern int32 sio0d(const int32 port, const int32 io, const int32 data); +extern int32 sio0s(const int32 port, const int32 io, const int32 data); + +void wd179x_connect_external_fifo(uint16 fifo_len, uint8* storage); +void wd179x_reset_external_fifo(void); + +extern uint32 PCX; /* external view of PC */ +extern int32 IR_S; /* Z80 Interrupt/Refresh register */ +extern uint32 vectorInterrupt; /* Interrupt pending */ +extern uint8 dataBus[MAX_INT_VECTORS]; /* IBC interrupt data bus values */ + +#define IBC_CAPACITY (77*1*26*128) /* Default SSSD Disk Capacity */ + +#define MOTOR_TO_LIMIT 128 + +static t_stat ibc_reset(DEVICE *ibc_dev); +static t_stat ibc_boot(int32 unitno, DEVICE *dptr); +static t_stat ibc_attach(UNIT *uptr, CONST char *cptr); +static t_stat ibc_detach(UNIT *uptr); +static t_stat ibc_set_model(UNIT* uptr, int32 value, CONST char* cptr, void* desc); + +static int32 ibc_sio(const int32 port, const int32 io, const int32 data); +static int32 ibc_pio(const int32 port, const int32 io, const int32 data); +static int32 ibc_param_reg(const int32 port, const int32 io, const int32 data); +static int32 ibc_banksel(const int32 port, const int32 io, const int32 data); +static int32 ibc_rtc(const int32 port, const int32 io, const int32 data); +static int32 ibc_cart(const int32 port, const int32 io, const int32 data); +static int32 ibc_reel(const int32 port, const int32 io, const int32 data); +static int32 ibc_dev31(const int32 port, const int32 io, const int32 data); +static int32 ibc_rom(const int32 port, const int32 io, const int32 data); +static int32 ibc_fdc_data(const int32 port, const int32 io, const int32 data); +static int32 ibc_sc_cache(const int32 port, const int32 io, const int32 data); +static int32 ibc_sc_baud(const int32 port, const int32 io, const int32 data); +static int32 ibc_sc_dtr(const int32 port, const int32 io, const int32 data); +static int32 ibc_unhandled(const int32 port, const int32 io, const int32 data); +static const char* ibc_description(DEVICE *dptr); + +/* Disk Control/Flags Register, 0x2a (OUT) */ +#define IBC_PARAM_DDENS (1 << 3) /* FDC Parameter Register */ + +/* IBC Middi Cadet I/O Ports */ +#define IBC_SIO 0x04 /* 0x04-0x13: UARTs (using AltairZ80 SIO.) UARTS 0x00-0x03 are using 2sio. */ +#define IBC_FDC_DATA 0x28 /* FDC Data Regster */ +#define IBC_PARAM 0x2a /* FDC PARAM register */ +#define IBC_DIPSWE 0x3c /* CPU Board DIP Switch E */ +#define IBC_BANKSEL 0x38 /* Bank Select register */ +#define IBC_FIFO_CTRL 0x3e /* FDC FIFO Control */ +#define IBC_ROM_CTRL 0x3f /* ROM Control Register */ +#define IBC_SCC_BANKSEL 0x58 /* Bank Select register */ +#define IBC_SCC_FIFO_CTRL 0x5e /* FDC FIFO Control */ +#define IBC_SCC_ROM_CTRL 0x5f /* ROM Control Register */ +#define IBC_HDC 0x40 /* 0x40-0x4F: Hard Disk Controller */ +#define IBC_CART 0x60 /* 0x60-0x63: Cartridge Tape Controller */ +#define IBC_REEL 0x64 /* 0x64-0x67: Reel to Reel Tape Controller */ +#define IBC_RTC 0x70 /* 0x70-0x7F: RTC */ +#define IBC_DEV31 0x80 /* 0x80-0x83: SYSTEM.DEV31 ? */ +#define IBC_PIO 0xec /* 0xEC-0xEF: Centronics Parallel Port */ + +#define IBC_CACHE_BASE_H 0x00 +#define IBC_CACHE_BASE_L_WR 0x01 +#define IBC_CACHE_BASE_L_RD 0x02 +#define IBC_CACHE_DATA 0x03 + +/* Z80 Mode 2 Interrupt Requests */ +#define IRQ_VI0 (1 << 0) +#define IRQ_VI1 (1 << 1) +#define IRQ_VI10 (1 << 10) +#define IRQ_VI15 (1 << 15) + +#define IBC_CACHE_SIZE (256 * 1024) /* CACHE is 256K */ +#define IBC_CACHE_MASK (IBC_CACHE_SIZE - 1) + +#define RST_OPCODE_TO_VECTOR(x) (x & 0x38) + +#define DEFAULT_TIMER_DELTA 100 /* default value for timer delta in ms */ + +static IBC_INFO ibc_info_data = { { 0x0000, IBC_ROM_SIZE, 0x3, 2 }, 0, ibc_mcc, IBC_SW_E_DEFAULT_VALUE, NULL }; +static IBC_INFO* ibc_info = &ibc_info_data; + +static uint8 current_baud[IBC_NUM_SIO] = { 0 }; +static uint8 baud_unlock[IBC_NUM_SIO] = { 0 }; + +/* The IBC does not really have RAM associated with it, but for ease of integration with the + * SIMH/AltairZ80 Resource Mapping Scheme, rather than Map and Unmap the ROM, simply implement our + * own RAM that can be swapped in when the IBC Boot ROM is disabled. + */ +static uint8 ibc_ram[IBC_ROM_SIZE]; + +#define IBC_WAIT 16 +#define IBC_UDATA(act,fl,wait,u4,name) NULL,act,NULL,NULL,NULL,0,0,(fl),0,(0),0,NULL,0,0,wait,0,u4,0,0,NULL,NULL,0,0,0,NULL,0,0,NULL,0,name + +static UNIT ibc_unit[] = { + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_CAPACITY), 1024 }, + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_CAPACITY) }, + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_CAPACITY) }, + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_CAPACITY) }, +}; + +static REG ibc_reg[] = { + { HRDATAD (PARAM, ibc_info_data.param, 8, "FDC PARAM Register"), }, + { HRDATAD (DIPSWE, ibc_info_data.dipsw_E, 8, "DIP Switch at location E on the MCC CPU board"), }, + { FLDATAD (PROMDIS, ibc_info_data.rom_disabled, 1, "PROM Disable"), }, + { HRDATAD (MODEL, ibc_info_data.model, 8, "Model (0=MultiStar, 1=MegaStar)"), }, + { HRDATAD (CACHWRBASE, ibc_info_data.cache_wbase, 32, "CACHE Write Base"), }, + { HRDATAD (CACHERBASE, ibc_info_data.cache_rbase, 32, "CACHE Read Base"), }, + { HRDATAD (CACHINDEX, ibc_info_data.cache_index, 8, "CACHE Index"), }, + { NULL } +}; + +#define IBC_NAME "IBC Middi Cadet HP (IBC MCC CPU)" + +static const char* ibc_description(DEVICE *dptr) { + if (dptr == NULL) { + return NULL; + } + + return IBC_NAME; +} + +static t_stat ibc_show_vectable(FILE* st, UNIT* uptr, int32 val, CONST void* desc); + +#define UNIT_IBC_V_MCC (UNIT_V_UF+1) /* Set model to MCC */ +#define UNIT_IBC_MCC (1 << UNIT_IBC_V_MCC) +#define UNIT_IBC_V_SCC (UNIT_V_UF+2) /* Set model to SCC */ +#define UNIT_IBC_SCC (1 << UNIT_IBC_V_SCC) + + +static MTAB ibc_mod[] = { + { MTAB_XTD|MTAB_VDV, 0, "MEMBASE", "MEMBASE", + &set_membase, &show_membase, NULL, "Sets disk controller memory base address" }, + { MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", + &set_iobase, &show_iobase, NULL, "Sets disk controller I/O base address" }, + { MTAB_XTD | MTAB_VDV, 0, NULL, "VECTABLE", + NULL, &ibc_show_vectable, NULL, "Show Z80 Mode 2 Interrupt Vector Table" }, + { MTAB_XTD | MTAB_VDV, ibc_mcc, NULL, "MCC", &ibc_set_model, + NULL, NULL, "Set IBC Model to MCC (MultiStar)" }, + { MTAB_XTD | MTAB_VDV, ibc_scc, NULL, "SCC", &ibc_set_model, + NULL, NULL, "Set IBC Model to SCC (MegaStar)" }, + { 0 } +}; + +/* Debug Flags */ +static DEBTAB ibc_dt[] = { + { "ERROR", ERROR_MSG, "Error messages" }, + { "BANK", BANK_MSG, "Memory Control messages" }, + { "DRIVE", DRIVE_MSG, "Drive messages" }, + { "VERBOSE", VERBOSE_MSG, "Verbose messages" }, + { "PIO", PIO_MSG, "PIO messages" }, + { "RTC", RTC_MSG, "RTC messages" }, + { "SBD", SBD_MSG, "System Board messages" }, + { "UART", UART_MSG, "UART messages" }, + { "CACHE", CACHE_MSG, "CACHE messages" }, + { "UIO", UNHANDLED_IO_MSG, "Unsuported I/O Ports" }, + { "FIFO", FIFO_MSG, "FDC FIFO messages" }, + { "DIPSW", DIPSW_MSG, "DIP Switch messages" }, + { NULL, 0, NULL } +}; + +DEVICE ibc_dev = { + "IBC", ibc_unit, ibc_reg, ibc_mod, + IBC_MAX_UNITS, /* # units */ + 10, /* address radix */ + 31, /* address width */ + 1, /* address increment */ + 8, /* data radix */ + 8, /* data width */ + NULL, /* examine routine */ + NULL, /* deposit routine */ + &ibc_reset, /* Reset routine */ + &ibc_boot, /* boot routine */ + &ibc_attach, /* attach routine */ + &ibc_detach, /* detach routine */ + &ibc_info_data, /* context */ + (DEV_DISABLE | DEV_DIS | DEV_DEBUG), ERROR_MSG, + ibc_dt, NULL, NULL, NULL, NULL, NULL, + &ibc_description +}; + +/* Synthetic device SIMH for communication + between Altair and SIMH environment using port 0xfe */ +static t_stat ibctimer_svc(UNIT* uptr); +static t_stat ibctimer_reset(DEVICE* dptr); + +static UNIT ibctimer_unit = { + UDATA(&ibctimer_svc, 0, 0), KBD_POLL_WAIT +}; + +static REG ibctimer_reg[] = { + { NULL } +}; + +static MTAB ibctimer_mod[] = { + /* timer generated interrupts are off */ + { 0 } +}; + +const char* ibctimer_description(DEVICE* dptr) { + if (dptr == NULL) { + return NULL; + } + + return "IBC Timer"; +} + +#define TIMER_MSG (1 << 1) +#define IN_MSG (1 << 2) +#define OUT_MSG (1 << 3) + +/* Debug Flags */ +static DEBTAB ibctimer_dt[] = { + { "ERROR", ERROR_MSG, "Error messages" }, + { "TIMER", TIMER_MSG, "Timer messages" }, + { "IN_MSG", IN_MSG, "Input messages" }, + { "OUT_MSG", OUT_MSG, "Output messages" }, + { NULL, 0 } +}; + +DEVICE ibctimer_device = { + "IBCTIMER", &ibctimer_unit, ibctimer_reg, ibctimer_mod, + 1, 10, 31, 1, 16, 4, + NULL, NULL, &ibctimer_reset, + NULL, NULL, NULL, + NULL, (DEV_DISABLE | DEV_DEBUG), 0, + ibctimer_dt, NULL, NULL, NULL, NULL, NULL, &ibctimer_description +}; + +/* Port 0x14 IBC Periodic Timer */ +int32 ibctimer_dev(const int32 port, const int32 io, const int32 data) { + int32 result = 0xFF; + if (io == 0) { + sim_debug(IN_MSG, &ibctimer_device, ": " ADDRESS_FORMAT + " IN(0x%02x)=0x%02x: Clear Status / Reset timer.\n", PCX, port, result); + sim_cancel(&ibctimer_unit); /* cancel unit */ + } + else { + sim_debug(OUT_MSG, &ibctimer_device, ": " ADDRESS_FORMAT + "OUT(0x%02x)=0x%02x: Set timer, count=%d.\n", PCX, port, data, data); + sim_activate_after(&ibctimer_unit, 250); + } + return result; +} + +static t_stat ibctimer_reset(DEVICE* dptr) { + if (dptr == NULL) { + return SCPE_IERR; + } + + sim_cancel(&ibctimer_unit); /* cancel unit */ + sim_debug(TIMER_MSG, &ibctimer_device, ": " ADDRESS_FORMAT + " Reset timer.\n", PCX); + return SCPE_OK; +} + +/* Unit service routine */ +static t_stat ibctimer_svc(UNIT* uptr) +{ + if (uptr == NULL) { + return (SCPE_IERR); + } + + if (ibc_info->model == ibc_mcc) { + /* MultiStar */ + vectorInterrupt |= IRQ_VI0; + dataBus[0] = 0; + } else { + /* Megastar */ + if ((IR_S & 0xFF00) == 0x0900) { +//#define THEOS8M +#ifdef THEOS8M + // THEOS8-M + vectorInterrupt |= IRQ_VI10; + dataBus[10] = 20; +#else + // THEOS8-S + vectorInterrupt |= IRQ_VI15; + dataBus[15] = 30; +#endif + } + else { + sim_printf("IBCTIMER - MegaStar - Unhandled!\n"); + } + } + + return SCPE_OK; +} + +/* Port 0x20: MegaStar RTC Timer */ +static t_stat ibcrtctimer_svc(UNIT* uptr); +static t_stat ibcrtctimer_reset(DEVICE* dptr); + +static UNIT ibcrtctimer_unit = { + UDATA(&ibcrtctimer_svc, 0, 0), KBD_POLL_WAIT +}; + +static REG ibcrtctimer_reg[] = { + { NULL } +}; + +static MTAB ibcrtctimer_mod[] = { + /* timer generated interrupts are off */ + { 0 } +}; + +const char* ibcrtctimer_description(DEVICE* dptr) { + if (dptr == NULL) { + return NULL; + } + + return "IBC RTC Timer"; +} + +DEVICE ibcrtctimer_device = { + "IBCRTCTIMER", &ibcrtctimer_unit, ibcrtctimer_reg, ibcrtctimer_mod, + 1, 10, 31, 1, 16, 4, + NULL, NULL, &ibcrtctimer_reset, + NULL, NULL, NULL, + NULL, (DEV_DISABLE | DEV_DEBUG), 0, + ibctimer_dt, NULL, NULL, NULL, NULL, NULL, &ibcrtctimer_description +}; + +/* port 0x20 IBC Super Cadet RTC Timer */ +int32 ibcrtctimer_dev(const int32 port, const int32 io, const int32 data) { + int32 result = 0xFF; + if (io == 0) { + sim_debug(IN_MSG, &ibcrtctimer_device, ": " ADDRESS_FORMAT + " IN(0x%02x)=0x%02x: Clear Status / Reset timer.\n", PCX, port, result); + sim_cancel(&ibcrtctimer_unit); /* cancel unit */ + } + else { + sim_debug(OUT_MSG, &ibcrtctimer_device, ": " ADDRESS_FORMAT + "OUT(0x%02x)=0x%02x: Set timer, count=%d.\n", PCX, port, data, data); + if (!sim_is_active(&ibcrtctimer_unit)) { + sim_activate(&ibcrtctimer_unit, sim_rtcn_init_unit_ticks(&ibcrtctimer_unit, 20, 0, 1)); + } + } + return result; +} + +static t_stat ibcrtctimer_reset(DEVICE* dptr) { + if (dptr == NULL) { + return SCPE_IERR; + } + + sim_cancel(&ibcrtctimer_unit); /* cancel unit */ + sim_debug(TIMER_MSG, &ibcrtctimer_device, ": " ADDRESS_FORMAT + " Reset timer.\n", PCX); + return SCPE_OK; +} + +/* Unit service routine */ +static t_stat ibcrtctimer_svc(UNIT* uptr) +{ + if (uptr == NULL) { + return SCPE_IERR; + } + + vectorInterrupt |= IRQ_VI1; + dataBus[1] = 2; + sim_rtcn_calb_tick(0); + sim_activate_after(&ibcrtctimer_unit, 1000000); + return SCPE_OK; +} + + +t_stat ibc_show_vectable(FILE* st, UNIT* uptr, int32 val, CONST void* desc) +{ + uint8 i; + int32 vectable = (IR_S & 0xFF00); + int32 vector; + + if (uptr == NULL) { + return SCPE_IERR; + } + + fprintf(st, "Vector table @0x%04x\n--------------------\n", vectable); + + for (i = 0; i < 64; i++) { + vector = (GetBYTEWrapper(vectable + (i * 2) + 1) << 8) | GetBYTEWrapper(vectable + (i * 2)); + if (vector != 0) fprintf(st, "%02d @0x%04x=0x%04x\n", i, vectable + (i * 2), vector); + } + return SCPE_OK; +} + + +/* IBC MultiStar Boot ROM DMP011 REV L. SEEQ 2764 */ +static uint8 ibc_rom_data[2][IBC_ROM_SIZE] = { + { + 0xF3, 0xDB, 0x14, 0xDB, 0x24, 0xDB, 0x80, 0xAF, 0xD3, 0x62, 0xD3, 0x40, 0xD3, 0x44, 0xD3, 0x47, + 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x77, 0x23, 0x0D, 0x20, 0xFB, 0x10, 0xF9, 0x3E, 0x03, 0x01, + 0x00, 0x0A, 0xED, 0x79, 0x0C, 0xED, 0x50, 0x0C, 0x10, 0xF8, 0x31, 0xFE, 0xFF, 0x3E, 0xE1, 0xED, + 0x47, 0x11, 0x8A, 0x01, 0x21, 0xF7, 0x02, 0xDB, 0x3C, 0xCB, 0x77, 0x20, 0x26, 0xAF, 0xD3, 0x3E, + 0xD3, 0x28, 0x3C, 0xD3, 0x28, 0x3C, 0xD3, 0x28, 0xD3, 0x3E, 0xDB, 0x28, 0xB7, 0x20, 0x0E, 0xDB, + 0x28, 0xFE, 0x01, 0x20, 0x08, 0xDB, 0x28, 0xFE, 0x02, 0x20, 0x02, 0x18, 0x06, 0x11, 0x40, 0x04, + 0x21, 0xA1, 0x05, 0x18, 0x07, 0x00, 0x00, 0x00, 0xC3, 0xAE, 0x0E, 0x00, 0xD5, 0xAF, 0xD3, 0x1C, + 0xED, 0x52, 0xE5, 0xC1, 0x11, 0x00, 0xE1, 0xE1, 0xED, 0xB0, 0xDB, 0x24, 0x11, 0x00, 0xE1, 0x2A, + 0x04, 0xE1, 0x19, 0x22, 0x04, 0xE1, 0xED, 0x5E, 0xFB, 0x01, 0x11, 0x00, 0x11, 0x22, 0xE4, 0x21, + 0x4D, 0x01, 0xED, 0xB0, 0x3E, 0x11, 0x01, 0x00, 0x0A, 0xED, 0x79, 0x0C, 0x0C, 0x10, 0xFA, 0xDB, + 0x3C, 0xCB, 0x57, 0xCA, 0x65, 0x0A, 0xCB, 0x7F, 0x20, 0x04, 0x3E, 0x01, 0xD3, 0x20, 0xDB, 0x3C, + 0xCB, 0x47, 0x28, 0x13, 0xCB, 0x4F, 0xCA, 0xF7, 0x02, 0x3E, 0x30, 0xD3, 0x2A, 0x32, 0x00, 0xE4, + 0xDB, 0x24, 0xCB, 0x7F, 0xCA, 0x5E, 0x01, 0xAF, 0x32, 0x1A, 0xE4, 0xCD, 0x83, 0x0E, 0x3A, 0x1A, + 0xE4, 0x3C, 0x3C, 0xFE, 0x14, 0x30, 0xC8, 0x18, 0xEF, 0x21, 0x1D, 0x01, 0xCD, 0xD1, 0x0E, 0xCD, + 0xCE, 0x0E, 0xCD, 0x83, 0x0E, 0x28, 0xFB, 0x11, 0xDF, 0x00, 0xD5, 0x67, 0xCD, 0x6F, 0x0E, 0x6F, + 0xE5, 0x06, 0x19, 0x21, 0x6E, 0x08, 0xDB, 0x3C, 0xCB, 0x77, 0x20, 0x03, 0x21, 0xBE, 0x09, 0x56, + 0x23, 0x5E, 0x23, 0xE3, 0xE5, 0xAF, 0xED, 0x52, 0xE1, 0x20, 0x06, 0xE1, 0x5E, 0x23, 0x56, 0xD5, + 0xC9, 0xE3, 0x23, 0x23, 0x10, 0xE9, 0xE1, 0x21, 0xD2, 0x08, 0xC3, 0xA5, 0x0E, 0x2F, 0x0D, 0x0A, + 0x49, 0x42, 0x43, 0x20, 0x4D, 0x75, 0x6C, 0x74, 0x69, 0x53, 0x74, 0x61, 0x72, 0x2A, 0x20, 0x53, + 0x45, 0x52, 0x49, 0x45, 0x53, 0x20, 0x20, 0x20, 0x4C, 0x6F, 0x61, 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TMS2764 */ + { + 0xF3, 0xAF, 0xD3, 0x62, 0xDB, 0x14, 0xDB, 0x24, 0xDB, 0x80, 0xAF, 0xD3, 0x40, 0xD3, 0x41, 0x3E, + 0x10, 0xD3, 0x42, 0xD3, 0x47, 0x18, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xC3, 0x00, 0x00, 0xC3, 0xF5, 0x0F, 0x16, 0x10, 0xAF, 0x5F, 0x0E, 0x08, 0x7A, + 0x3D, 0x0F, 0x0F, 0x0F, 0xE6, 0x60, 0x6F, 0x7A, 0x3D, 0x0F, 0xE6, 0x06, 0xB5, 0x6F, 0x7B, 0x45, + 0xB7, 0x28, 0x13, 0xFE, 0x04, 0x38, 0x08, 0xCB, 0xC5, 0xD6, 0x04, 0x5F, 0x45, 0x28, 0x07, 0x47, + 0x7D, 0xC6, 0x08, 0x10, 0xFC, 0x47, 0x78, 0xD3, 0x3D, 0x1C, 0x0D, 0x20, 0xE1, 0x15, 0x20, 0xCB, + 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } +}; + +typedef struct io_resource_list { + int32(*routine)(const int32, const int32, const int32); + uint32 baseaddr; + uint32 size; + uint32 resource_type; + char* name; +} IO_RESOURCE_LIST; + +IO_RESOURCE_LIST IBC_MCC_RESOURCES[] = { + { &ibc_sio, IBC_SIO, 16, RESOURCE_TYPE_IO, "ibc_sio"}, + { &ibctimer_dev, 0x14, 1, RESOURCE_TYPE_IO, "ibctimer_dev"}, + { &ibc_fdc_data, IBC_FDC_DATA, 1, RESOURCE_TYPE_IO, "ibc_sbd" }, + { &ibc_param_reg, IBC_PARAM, 1, RESOURCE_TYPE_IO, "ibc_param_reg" }, + { &ibc_banksel, IBC_BANKSEL, 1, RESOURCE_TYPE_IO, "ibc_banksel" }, + { &ibc_banksel, IBC_DIPSWE, 4, RESOURCE_TYPE_IO, "ibc_banksel" }, + { &ibc_cart, IBC_CART, 4, RESOURCE_TYPE_IO, "ibc_cart" }, + { &ibc_reel, IBC_REEL, 4, RESOURCE_TYPE_IO, "ibc_reel" }, + { &ibc_dev31, IBC_DEV31, 4, RESOURCE_TYPE_IO, "ibc_dev31" }, + { &ibc_rtc, IBC_RTC, 16, RESOURCE_TYPE_IO, "ibc_rtc" }, + { &ibc_pio, IBC_PIO, 4, RESOURCE_TYPE_IO, "ibc_pio" }, + { NULL } +}; + +IO_RESOURCE_LIST IBC_SCC_RESOURCES[] = { + { &ibc_sio, IBC_SIO, 16, RESOURCE_TYPE_IO, "ibc_sio"}, + { &ibctimer_dev, 0x14, 1, RESOURCE_TYPE_IO, "ibctimer_dev"}, + { &ibc_fdc_data, IBC_FDC_DATA, 1, RESOURCE_TYPE_IO, "ibc_sbd" }, + { &ibc_param_reg, IBC_PARAM, 1, RESOURCE_TYPE_IO, "ibc_param_reg" }, + { &ibc_banksel, IBC_BANKSEL, 1, RESOURCE_TYPE_IO, "ibc_banksel" }, + { &ibc_banksel, IBC_DIPSWE, 4, RESOURCE_TYPE_IO, "ibc_banksel" }, + { &ibc_cart, IBC_CART, 4, RESOURCE_TYPE_IO, "ibc_cart" }, + { &ibc_reel, IBC_REEL, 4, RESOURCE_TYPE_IO, "ibc_reel" }, + { &ibc_dev31, IBC_DEV31, 4, RESOURCE_TYPE_IO, "ibc_dev31" }, + { &ibc_rtc, IBC_RTC, 16, RESOURCE_TYPE_IO, "ibc_rtc" }, + { &ibc_pio, IBC_PIO, 4, RESOURCE_TYPE_IO, "ibc_pio" }, + { &ibc_sc_dtr, 0x1c, 4, RESOURCE_TYPE_IO, "ibc_sc_1C-1F" }, + { &ibcrtctimer_dev, 0x20, 1, RESOURCE_TYPE_IO, "ibcrtctimer_dev"}, + { &ibc_sio, 0x2c, 12, RESOURCE_TYPE_IO, "ibc_sc_sio" }, /* UARTS 11-16 */ + { &ibc_sc_baud, 0x3d, 1, RESOURCE_TYPE_IO, "ibc_sc_3D" }, + { &ibc_pio, 0x4c, 4, RESOURCE_TYPE_IO, "ibc_sc_pio" }, + { &ibc_unhandled, 0x50, 12, RESOURCE_TYPE_IO, "ibc_sc_50-5B" }, + { &ibc_banksel, 0x5c, 4, RESOURCE_TYPE_IO, "ibc_sc_banksel" }, + { &ibc_unhandled, 0x70, 1, RESOURCE_TYPE_IO, "ibc_sc_70" }, + { &ibc_unhandled, 0xC0, 16, RESOURCE_TYPE_IO, "ibc_sc_C0-CF" }, + { &ibc_sc_cache, 0xE0, 4, RESOURCE_TYPE_IO, "ibc_sc_cache" }, + { &ibc_unhandled, 0xE4, 12, RESOURCE_TYPE_IO, "ibc_sc_E4-EF" }, + { &ibc_unhandled, 0xF0, 16, RESOURCE_TYPE_IO, "ibc_sc_F0-FF" }, /* Take over the SIMH Pseudo device ports as the boot ROM accesses them. */ + { NULL } +}; + +static t_stat ibc_set_model(UNIT* uptr, int32 value, CONST char* cptr, void* desc) { + IO_RESOURCE_LIST* resources; + + if (value == ibc_info->model) { + sim_printf("IBC model unchanged\n"); + return SCPE_OK; + } + + if (value > ibc_scc) { + return SCPE_ARG; + } + + /* Unmap current model I/O ports */ + resources = (ibc_info->model == ibc_mcc) ? IBC_MCC_RESOURCES : IBC_SCC_RESOURCES; + while (resources->routine != NULL) { + sim_debug(VERBOSE_MSG, &ibc_dev, "Unmapping I/O at 0x%02x-0x%02x: %s\n", + resources->baseaddr, resources->baseaddr + resources->size - 1, resources->name); + sim_map_resource(resources->baseaddr, resources->size, resources->resource_type, resources->routine, resources->name, TRUE); + resources++; + } + + ibc_info->model = value; + + /* Map new model I/O ports */ + resources = (ibc_info->model == ibc_mcc) ? IBC_MCC_RESOURCES : IBC_SCC_RESOURCES; + while (resources->routine != NULL) { + sim_debug(VERBOSE_MSG, &ibc_dev, "Mapping I/O at 0x%02x-0x%02x: %s\n", + resources->baseaddr, resources->baseaddr + resources->size - 1, resources->name); + sim_map_resource(resources->baseaddr, resources->size, resources->resource_type, resources->routine, resources->name, FALSE); + resources++; + } + + return SCPE_OK; +} + +/* Reset routine */ +static t_stat ibc_reset(DEVICE* dptr) +{ + PNP_INFO* pnp = (PNP_INFO*)dptr->ctxt; + int i; + uint8 unmap = dptr->flags & DEV_DIS; + IO_RESOURCE_LIST* resources = (ibc_info->model == ibc_mcc) ? IBC_MCC_RESOURCES : IBC_SCC_RESOURCES; + + /* Connect IBC ROM at base address */ + sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &ibc_rom, "ibc_rom", unmap); + + while (resources->routine != NULL) { + sim_debug(VERBOSE_MSG, &ibc_dev, "%s I/O at 0x%02x-0x%02x: %s\n", + unmap ? "Unmapping" : "Mapping", resources->baseaddr, resources->baseaddr + resources->size - 1, resources->name); + sim_map_resource(resources->baseaddr, resources->size, resources->resource_type, resources->routine, resources->name, unmap); + resources++; + } + + for (i = 0; i < IBC_MAX_UNITS; i++) { + ibc_unit[i].u4 = i; + } + + /* Reset FDC PARAM register */ + ibc_info->param = 0; + ibc_info->rom_disabled = FALSE; + ibc_info->cache_wbase = 0; + ibc_info->cache_rbase = 0; + ibc_info->cache_index = 0; + + if (unmap) { + wd179x_infop->intenable = 0; + wd179x_connect_external_fifo(0, NULL); + } + else { + wd179x_connect_external_fifo(FDC_FIFO_LEN, ibc_info->fdc_fifo); + ibc_info->fdc_fifo_rd_index = 0; + wd179x_infop->intenable = 1; + wd179x_infop->intvector = 2; + } + + /* If memory was allocated for the CACHE, free it. */ + if (ibc_info->cache != NULL) { + sim_debug(CACHE_MSG, &ibc_dev, "Freeing CACHE.\n"); + free(ibc_info->cache); + ibc_info->cache = NULL; + } + + return SCPE_OK; +} + +static t_stat ibc_boot(int32 unitno, DEVICE *dptr) +{ + if ((dptr == NULL) || (unitno > 0)) { + return SCPE_IERR; + } + + sim_debug(VERBOSE_MSG, &ibc_dev, "Booting IBC Controller\n"); + + /* Set the PC to 0000H, and go. */ + *((int32 *) sim_PC->loc) = 0000; + return SCPE_OK; +} + +/* Attach routine */ +static t_stat ibc_attach(UNIT *uptr, CONST char *cptr) +{ + t_stat r = SCPE_IERR; + + if (uptr->u4 < 4) { + r = wd179x_attach(uptr, cptr); + } + + return r; +} + +/* Detach routine */ +static t_stat ibc_detach(UNIT *uptr) +{ + t_stat r = SCPE_IERR; + + if (uptr->u4 < 4) { + r = wd179x_detach(uptr); + } + + return r; +} + +static int32 ibc_rom(const int32 Addr, const int32 write, const int32 data) +{ + if(write) { + ibc_ram[Addr & IBC_ROM_ADDR_MASK] = (uint8)data; + return 0; + } else { + if(ibc_info->rom_disabled == FALSE) { + return(ibc_rom_data[ibc_info->model][Addr & IBC_ROM_ADDR_MASK]); + } else { + return(ibc_ram[Addr & IBC_ROM_ADDR_MASK]); + } + } +} + +/* IBC Cadet SIO ports */ +static int32 ibc_sio(const int32 port, const int32 io, const int32 data) +{ + int32 result = 0xFF; + int32 uart = port >> 1; + + if (port >=0x2c && port <= 0x37) { + uart -= 12; + } + + if (io) { /* Write */ + if (port & 1) { /* Data port */ + result = sio0d(port, 1, data); + sim_debug(UART_MSG, &ibc_dev, ADDRESS_FORMAT " WR UART[%d] DATA=0x%02x\n", PCX, uart, data); + } + else { /* Status port */ + result = sio0s(port, 1, data); + sim_debug(UART_MSG, &ibc_dev, ADDRESS_FORMAT " WR UART[%d] STAT=0x%02x\n", PCX, uart, data); + } + } + else { /* Read */ + if (port & 1) { /* Data port */ + result = sio0d(port, 0, 0); + sim_debug(UART_MSG, &ibc_dev, ADDRESS_FORMAT " RD UART[%d] DATA=0x%02x\n", PCX, uart, result); + } + else { /* Status port */ + result = sio0s(port, 0, 0); + sim_debug(UART_MSG, &ibc_dev, ADDRESS_FORMAT " RD UART[%d] STAT=0x%02x\n", PCX, uart, result); + } + } + return result; +} + +/* Disk Control/Flags Register, 0x2a */ +static int32 ibc_param_reg(const int32 port, const int32 io, const int32 data) +{ + int32 result = 0; + if(io) { /* I/O Write */ + + ibc_info->param = (uint8)data; + /* Disk drive select bits 1:0 */ + wd179x_infop->sel_drive = data & 0x03; + + if (data & IBC_PARAM_DDENS) { + wd179x_infop->ddens = 1; + } + else { + wd179x_infop->ddens = 0; + } + + sim_debug(DRIVE_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR CTRL 0x%02x: sel_drive=%d, drivetype=%d, head_sel=%d, dens=%d, aw=%d\n", + PCX, port, wd179x_infop->sel_drive, + wd179x_infop->drivetype, ibc_info->head_sel, + wd179x_infop->ddens, ibc_info->autowait); + } else { /* I/O Read */ + result = wd179x_infop->drq ? 0xFF : 0; + if (wd179x_infop->intrq) + result &= 0x7F; + + sim_debug(DRIVE_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD DISK STATUS: sel_drive=%d: Status=0x%02x\n", PCX, wd179x_infop->sel_drive, result); + } + + return result; +} + +/* DIP Switch E (0x3c) / ROM Control (0x3f) */ +static int32 ibc_banksel(const int32 port, const int32 io, const int32 data) +{ + int32 result = 0xFF; + + if (io) { /* Write */ + switch(port) { + case IBC_BANKSEL: + case IBC_SCC_BANKSEL: + if (data < 16) { + setBankSelect(data); + sim_debug(BANK_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR Bank Select Port: 0x%02x=0x%02x\n", PCX, port, data); + } + else { + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " Invalid RAM bank 0x%02x\n", PCX, data); + } + break; + case IBC_ROM_CTRL: + case IBC_SCC_ROM_CTRL: + sim_debug(BANK_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR ROM Ctrl Port: 0x%02x=0x%02x (Disable ROM.)\n", PCX, port, data); + ibc_info->rom_disabled = TRUE; + break; + case IBC_FIFO_CTRL: + case IBC_SCC_FIFO_CTRL: + sim_debug(DRIVE_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR FDC FIFO Ctrl Port: 0x%02x=0x%02x\n", PCX, port, data); + if (data & 0x10) { /* FIFO Reset */ + wd179x_reset_external_fifo(); + ibc_info->fdc_fifo_rd_index = 0; + } + break; + default: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR Unhandled Port: 0x%02x=0x%02x\n", PCX, port, data); + break; + } + } else { /* Read */ + switch(port) { + case IBC_DIPSWE: + /* These are 8-position DIP switch at location E on the IBC CPU board. + * + * 0xff: Boot from floppy (All off.) + * Switch 1 - 0xfe: Boot into ROM monitor (Switch 1 on.) + * Switch 2 - 0xfd: Boot from hard disk (Switch 2 on.) + * Switch 7 - 0xbe: OFF = Use FDC Interupts, ON = Poll FDC instead. + */ + result = ibc_info->dipsw_E; + + if (ibc_info->model == ibc_mcc) { + sim_debug(DIPSW_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD DIPSW E=0x%02x\n", PCX, result); + } + else { + sim_debug(DIPSW_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " Boot mode: %d, baud=%d, Bank %s, %s Floppy\n", PCX, (result & 0x07), (result & 0x38) >> 3, (result & 0x40) ? "Base 16K / Bank 48K" : "Base 40K / Bank 24K", (result & 0x80) ? "1.6MB" : "1MB"); + } + break; + case IBC_ROM_CTRL: + case 0x5F: + sim_debug(BANK_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD ROM Ctrl Port: 0x%02x=0x%02x (Enable ROM.)\n", PCX, port, result); + ibc_info->rom_disabled = FALSE; + break; + default: + sim_debug(SBD_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD attempt from write-only 0x%02x=0x%02x\n", PCX, port, result); + break; + } + } + return result; +} + +/* IBC FDC Data Port (0x28) */ +static int32 ibc_fdc_data(const int32 port, const int32 io, const int32 data) +{ + uint8 fifodata = 0xFF; + + if (io) { /* Write */ + ibc_info->fdc_fifo[ibc_info->fdc_fifo_rd_index] = (uint8)data; + ibc_info->fdc_fifo_rd_index++; + ibc_info->fdc_fifo_rd_index &= FDC_FIFO_MASK; + } else { /* Read */ + fifodata = ibc_info->fdc_fifo[ibc_info->fdc_fifo_rd_index]; + ibc_info->fdc_fifo_rd_index++; + ibc_info->fdc_fifo_rd_index &= FDC_FIFO_MASK; + } + + sim_debug(FIFO_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " %s FIFO: 0x%02x=%02x\n", PCX, io ? "WR" : "RD", port, fifodata); + + return (fifodata); +} + +static struct tm currentTime; + +/* IBC MCC RTC (0x70-0x7F) + * + * Uses the National Semiconductor MM58174A + * Microprocessor-Compatible Real-Time Clock + */ +static int32 ibc_rtc(const int32 port, const int32 io, const int32 data) +{ + int32 result; + time_t now; + + if (io) { /* Write */ + switch (port) { + default: + sim_debug(RTC_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR Unhandled RTC Port: 0x%02x=0x%02x\n", PCX, port, data); + break; + } + result = 0; + } + else { /* Read */ + sim_get_time(&now); + now += 0; // ss1_rtc[0].clockDelta; + currentTime = *localtime(&now); + + switch (port & 0x0F) { + case 1: + result = 0; + break; + case 2: + result = currentTime.tm_sec % 10; + break; + case 3: + result = currentTime.tm_sec / 10; + break; + case 4: + result = currentTime.tm_min % 10; + break; + case 5: + result = currentTime.tm_min / 10; + break; + case 6: + result = currentTime.tm_hour % 10; + break; + case 7: + result = currentTime.tm_hour / 10; + break; + case 8: + result = currentTime.tm_mday % 10; + break; + case 9: + result = currentTime.tm_mday / 10; + break; + case 10: + result = currentTime.tm_wday; + break; + case 11: + result = (currentTime.tm_mon + 1) % 10; + break; + case 12: + result = (currentTime.tm_mon + 1) / 10; + break; + default: + result = 0xFF; + break; + } + } + return result; +} + +/* IBC Cartridge Tape Controller (0x60-0x63) */ +static int32 ibc_cart(const int32 port, const int32 io, const int32 data) +{ + int32 result; + if (io) { /* Write */ + switch (port) { + case IBC_CART: + case IBC_CART + 1: + case IBC_CART + 2: + case IBC_CART + 3: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR CART Port: 0x%02x=0x%02x\n", PCX, port, data); + break; + default: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR Unhandled CART Port: 0x%02x=0x%02x\n", PCX, port, data); + break; + } + result = 0; + } + else { /* Read */ + result = 0xFF; + switch (port) { + case IBC_CART: + case IBC_CART + 1: + case IBC_CART + 2: + case IBC_CART + 3: + sim_debug(DRIVE_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD CART Port: 0x%02x=0x%02x\n", PCX, port, result); + break; + default: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD Unhandled SBD CART: 0x%02x=0x%02x\n", PCX, port, result); + break; + } + } + return result; +} + +/* IBC Reel to Reel Tape Controller (0x64-0x67) */ +static int32 ibc_reel(const int32 port, const int32 io, const int32 data) +{ + int32 result; + if (io) { /* Write */ + switch (port) { + case IBC_REEL: + case IBC_REEL + 1: + case IBC_REEL + 2: + case IBC_REEL + 3: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR REEL Port: 0x%02x=0x%02x\n", PCX, port, data); + break; + default: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR Unhandled REEL Port: 0x%02x=0x%02x\n", PCX, port, data); + break; + } + result = 0; + } + else { /* Read */ + result = 0xFF; + switch (port) { + case IBC_REEL: + case IBC_REEL + 1: + case IBC_REEL + 2: + case IBC_REEL + 3: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD REEL Port: 0x%02x=0x%02x\n", PCX, port, result); + break; + default: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD Unhandled SBD CART: 0x%02x=0x%02x\n", PCX, port, result); + break; + } + } + return result; +} + +/* IBC DEV31 (Unknown) (0x80-0x83) */ +static int32 ibc_dev31(const int32 port, const int32 io, const int32 data) +{ + int32 result; + if (io) { /* Write */ + switch (port) { + case IBC_DEV31: + case IBC_DEV31 + 1: + case IBC_DEV31 + 2: + case IBC_DEV31 + 3: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR DEV31 Port: 0x%02x=0x%02x\n", PCX, port, data); + break; + default: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR Unhandled DEV31 Port: 0x%02x=0x%02x\n", PCX, port, data); + break; + } + result = 0; + } + else { /* Read */ + result = 0xFF; + switch (port) { + case IBC_DEV31: + case IBC_DEV31 + 1: + case IBC_DEV31 + 2: + case IBC_DEV31 + 3: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD DEV31 Port: 0x%02x=0x%02x\n", PCX, port, result); + break; + default: + sim_debug(ERROR_MSG, &ibc_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD Unhandled SBD CART: 0x%02x=0x%02x\n", PCX, port, result); + break; + } + } + return result; +} + +/* IBC Cadet PIO port */ +static int32 ibc_pio(const int32 port, const int32 io, const int32 data) +{ + static int32 result = 0xFF; + if (io) { /* Write */ + switch (port & 0x03) { + case 0x00: + sim_debug(PIO_MSG, &ibc_dev, ADDRESS_FORMAT + " WR 0x%02x PIOA DATA=0x%02x\n", PCX, port, data); + break; + case 0x01: + sim_debug(PIO_MSG, &ibc_dev, ADDRESS_FORMAT + " WR 0x%02x PIOB DATA=0x%02x\n", PCX, port, data); + break; + case 0x02: + sim_debug(PIO_MSG, &ibc_dev, ADDRESS_FORMAT + " WR 0x%02x PIOC CTRL=0x%02x\n", PCX, port, data); + break; + default: + sim_debug(ERROR_MSG, &ibc_dev, ADDRESS_FORMAT + " WR Unhandled Port: 0x%02x=0x%02x\n", PCX, port, data); + break; + } + } + else { /* Read */ + result = 0x00; + switch (port & 0x03) { + case 0x00: + sim_debug(PIO_MSG, &ibc_dev, ADDRESS_FORMAT + " RD %02x PIOA DATA=0x%02x\n", PCX, port, result); + break; + default: + sim_debug(ERROR_MSG, &ibc_dev, ADDRESS_FORMAT + " RD Unhandled Port: 0x%02x=0x%02x\n", PCX, port, result); + break; + } + } + return result; +} + +/* IBC Cadet CACHE */ +static int32 ibc_sc_cache(const int32 port, const int32 io, const int32 data) +{ + static int32 result = 0xFF; + + /* The first time the CACHE is accessed, allocate memory for the CACHE */ + if (ibc_info->cache == NULL) { + ibc_info->cache = calloc(IBC_CACHE_SIZE, 1); + if (ibc_info->cache != NULL) { + sim_debug(CACHE_MSG, &ibc_dev, ADDRESS_FORMAT + " Allocated %d bytes for CACHE\n", PCX, IBC_CACHE_SIZE); + } + else { + return sim_messagef(SCPE_MEM, "Cannot allocate %d bytes for CACHE.\n", IBC_CACHE_SIZE); + } + } + + if (io) { /* Write */ + switch (port & 0x03) { + case IBC_CACHE_BASE_H: + /* Set CACHE Write Base */ + ibc_info->cache_wbase = ((ibc_info->cache_wbase) & 0xFF00) | (data << 16); + ibc_info->cache_wbase &= IBC_CACHE_MASK; + + /* Set CACHE Read Base */ + ibc_info->cache_rbase = ibc_info->cache_wbase; + + /* Reset CACHE Index */ + ibc_info->cache_index = 0; + sim_debug(CACHE_MSG, &ibc_dev, ADDRESS_FORMAT + " WR CACHE Port: 0x%02x=0x%02x, wbase=0x%06x, rbase=0x%06x\n", PCX, port, data, ibc_info->cache_wbase, ibc_info->cache_rbase); + break; + case IBC_CACHE_BASE_L_WR: + ibc_info->cache_wbase = ((ibc_info->cache_wbase) & 0xFF0000) | (data << 8); + ibc_info->cache_wbase &= IBC_CACHE_MASK; + + ibc_info->cache_index = 0; + sim_debug(CACHE_MSG, &ibc_dev, ADDRESS_FORMAT + " WR CACHE Port: 0x%02x=0x%02x, wbase=0x%06x\n", PCX, port, data, ibc_info->cache_wbase); + break; + case IBC_CACHE_BASE_L_RD: + ibc_info->cache_rbase = ((ibc_info->cache_rbase) & 0xFF0000) | (data << 8); + ibc_info->cache_rbase &= IBC_CACHE_MASK; + ibc_info->cache_index = 0; + sim_debug(CACHE_MSG, &ibc_dev, ADDRESS_FORMAT + " WR CACHE Port: 0x%02x=0x%02x, wbase=0x%06x\n", PCX, port, data, ibc_info->cache_rbase); + break; + case IBC_CACHE_DATA: + sim_debug(CACHE_MSG, &ibc_dev, ADDRESS_FORMAT + " WR CACHE Data: 0x%02x=0x%02x, wbase=0x%06x\n", PCX, port, data, ibc_info->cache_rbase); + ibc_info->cache[ibc_info->cache_wbase + ibc_info->cache_index] = (uint8)data; + ibc_info->cache_index++; + break; + } + } + else { /* Read */ + switch (port & 0x03) { + case IBC_CACHE_DATA: + result = ibc_info->cache[ibc_info->cache_rbase + ibc_info->cache_index]; + sim_debug(CACHE_MSG, &ibc_dev, ADDRESS_FORMAT + " RD CACHE Data: 0x%02x=0x%02x, rbase=0x%06x, index=0x%02x\n", PCX, port, result, ibc_info->cache_rbase, ibc_info->cache_index); + ibc_info->cache_index++; + break; + default: + sim_debug(CACHE_MSG, &ibc_dev, ADDRESS_FORMAT + " RD CACHE Port: 0x%02x=0x%02x, rbase=0x%06x, index=0x%02x\n", PCX, port, result, ibc_info->cache_rbase, ibc_info->cache_index); + break; + } + } + return result; +} + +/* IBC Super Cadet Baud Rate Control port */ +static int32 ibc_sc_baud(const int32 port, const int32 io, const int32 data) +{ + uint8 sioport = ((data & 0x60) >> 5) | ((data & 0x06) << 1); + uint8 baudrate = ((data & 0x18) >> 3) | ((data & 0x1) << 2); + uint8 baudset = ((data & 0x80) >> 7); + static int32 result = 0xFF; + + if (io) { /* Write */ + sim_debug(UART_MSG, &ibc_dev, ADDRESS_FORMAT + " WR Baud Rate Port 0x%02x=0x%02x: SIO: %d, baud: 0x%x, set=%d, current_baud=%d, unlock=%d\n", PCX, port, data, sioport, baudrate, baudset, current_baud[sioport], baud_unlock[sioport]); + + if (baudset == 0) { + if (baudrate == current_baud[sioport]) { + baud_unlock[sioport] = 1; + } + } + else { + if (baud_unlock[sioport] == 1) { + sim_debug(UART_MSG, &ibc_dev, ADDRESS_FORMAT " Setting SIO %d baud: %d\n", PCX, sioport, baudrate); + current_baud[sioport] = baudrate; + baud_unlock[sioport] = 0; + } + else { + sim_debug(ERROR_MSG, &ibc_dev, ADDRESS_FORMAT " Error Setting SIO %d baud: %d (locked.)\n", PCX, sioport, baudrate); + } + } + } + else { /* Read */ + sim_debug(UART_MSG, &ibc_dev, ADDRESS_FORMAT + " RD Baud Port: 0x%02x=0x%02x\n", PCX, port, result); + } + return result; +} + +/* IBC Super Cadet DTR Control ports */ +static int32 ibc_sc_dtr(const int32 port, const int32 io, const int32 data) +{ + uint8 sioport = (data & 0x07) | ((port & 1) << 3); + uint8 deasserted = (port & 0x02) >> 1; + static int32 result = 0xFF; + + if (io) { /* Write */ + sim_debug(UART_MSG, &ibc_dev, ADDRESS_FORMAT + " WR DTR Port 0x%02x=0x%02x: SIO: %d: %s DTR\n", PCX, port, data, sioport, deasserted == 1 ? "De-assert" : "Assert"); + } + else { /* Read */ + sim_debug(UART_MSG, &ibc_dev, ADDRESS_FORMAT + " RD DTR Port: 0x%02x=0x%02x\n", PCX, port, result); + } + return result; +} + +/* IBC Cadet Unhandled ports */ +static int32 ibc_unhandled(const int32 port, const int32 io, const int32 data) +{ + static int32 result = 0xFF; + if (io) { /* Write */ + sim_debug(UNHANDLED_IO_MSG, &ibc_dev, ADDRESS_FORMAT + " WR Unhandled Port: 0x%02x=0x%02x\n", PCX, port, data); + } + else { /* Read */ + sim_debug(UNHANDLED_IO_MSG, &ibc_dev, ADDRESS_FORMAT + " RD Unhandled Port: 0x%02x=0x%02x\n", PCX, port, result); + } + return result; +} diff --git a/AltairZ80/ibc_mcc_hdc.c b/AltairZ80/ibc_mcc_hdc.c new file mode 100644 index 00000000..7ded1947 --- /dev/null +++ b/AltairZ80/ibc_mcc_hdc.c @@ -0,0 +1,679 @@ +/************************************************************************* + * * + * Copyright (c) 2021-2023 Howard M. Harte. * + * https://github.com/hharte * + * * + * Permission is hereby granted, free of charge, to any person obtaining * + * a copy of this software and associated documentation files (the * + * "Software"), to deal in the Software without restriction, including * + * without limitation the rights to use, copy, modify, merge, publish, * + * distribute, sublicense, and/or sell copies of the Software, and to * + * permit persons to whom the Software is furnished to do so, subject to * + * the following conditions: * + * * + * The above copyright notice and this permission notice shall be * + * included in all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON- * + * INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE * + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * + * SOFTWARE. * + * * + * Except as contained in this notice, the names of The Authors shall * + * not be used in advertising or otherwise to promote the sale, use or * + * other dealings in this Software without prior written authorization * + * from the Authors. * + * * + * Module Description: * + * IBC/Integrated Business Computers MCC ST-506 Hard Disk Controller * + * module for SIMH. * + * * + *************************************************************************/ + +#include "altairz80_defs.h" +#include "sim_imd.h" + +/* Debug flags */ +#define ERROR_MSG (1 << 0) +#define CMD_MSG (1 << 1) +#define RD_DATA_MSG (1 << 2) +#define WR_DATA_MSG (1 << 3) +#define FIFO_MSG (1 << 4) +#define TF_MSG (1 << 5) +#define VERBOSE_MSG (1 << 6) + +#define IBC_HDC_MAX_DRIVES 4 /* Maximum number of drives supported */ +#define IBC_HDC_MAX_SECLEN 256 /* Maximum of 256 bytes per sector */ +#define IBC_HDC_FORMAT_FILL_BYTE 0xe5 /* Real controller uses 0, but we + choose 0xe5 so the disk shows up as blank under CP/M. */ +#define IBC_HDC_MAX_CYLS 1024 +#define IBC_HDC_MAX_HEADS 16 +#define IBC_HDC_MAX_SPT 256 + +#define DEV_NAME "IBCHDC" + +/* Task File Register Offsets */ +#define TF_CSEC 0 +#define TF_HEAD 1 +#define TF_NSEC 2 +#define TF_SA3 3 +#define TF_CMD 4 +#define TF_DRIVE 5 +#define TF_TRKL 6 +#define TF_TRKH 7 +#define TF_FIFO 8 + +#define IBC_HDC_STATUS_ERROR (1 << 0) + +#define IBC_HDC_ERROR_ID_NOT_FOUND (1 << 4) + +#define IBC_HDC_CMD_RESET 0x00 +#define IBC_HDC_CMD_READ_SECT 0x01 +#define IBC_HDC_CMD_WRITE_SECT 0x02 +#define IBC_HDC_CMD_FORMAT_TRK 0x08 +#define IBC_HDC_CMD_ACCESS_FIFO 0x0b +#define IBC_HDC_CMD_READ_PARAMETERS 0x10 + +#define IBC_HDC_REG_STATUS 0x40 +#define IBC_HDC_REG_FIFO_STATUS 0x44 +#define IBC_HDC_REG_FIFO 0x48 + +typedef struct { + UNIT *uptr; + uint8 readonly; /* Drive is read-only? */ + uint16 sectsize; /* sector size */ + uint16 nsectors; /* number of sectors/track */ + uint16 nheads; /* number of heads */ + uint16 ncyls; /* number of cylinders */ + uint16 cur_cyl; /* Current cylinder */ + uint8 cur_head; /* Current Head */ + uint8 cur_sect; /* current starting sector of transfer */ + uint16 cur_sectsize;/* Current sector size in SA6 register */ + uint16 xfr_nsects; /* Number of sectors to transfer */ + uint8 ready; /* Is drive ready? */ +} IBC_HDC_DRIVE_INFO; + +typedef struct { + PNP_INFO pnp; /* Plug and Play */ + uint8 sel_drive; /* Currently selected drive */ + uint8 reg_temp_holding[4]; + uint8 taskfile[9]; /* ATA Task File Registers */ + uint8 status_reg; /* IBC Disk Slave Status Register */ + uint8 error_reg; /* IBC Disk Slave Error Register */ + uint8 ndrives; /* Number of drives attached to the controller */ + uint8 sectbuf[IBC_HDC_MAX_SECLEN*10]; + uint16 secbuf_index; + IBC_HDC_DRIVE_INFO drive[IBC_HDC_MAX_DRIVES]; +} IBC_HDC_INFO; + +static IBC_HDC_INFO ibc_hdc_info_data = { { 0x0, 0, 0x40, 9 } }; +static IBC_HDC_INFO *ibc_hdc_info = &ibc_hdc_info_data; + +extern uint32 PCX; +extern int32 HL_S; /* HL register */ +extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc); +extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc); +extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type, + int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap); +extern int32 find_unit_index(UNIT *uptr); + +#define UNIT_V_IBC_HDC_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */ +#define UNIT_IBC_HDC_VERBOSE (1 << UNIT_V_IBC_HDC_VERBOSE) +#define IBC_HDC_CAPACITY (512*4*32*256) /* Default Disk Capacity Quantum 2020 */ + +static t_stat ibc_hdc_reset(DEVICE *ibc_hdc_dev); +static t_stat ibc_hdc_attach(UNIT *uptr, CONST char *cptr); +static t_stat ibc_hdc_detach(UNIT *uptr); +static t_stat ibc_hdc_unit_set_geometry(UNIT* uptr, int32 value, CONST char* cptr, void* desc); +static t_stat ibc_hdc_unit_show_geometry(FILE* st, UNIT* uptr, int32 value, CONST void* desc); +static int32 ibchdcdev(const int32 port, const int32 io, const int32 data); + +static uint8 IBC_HDC_Read(const uint32 Addr); +static uint8 IBC_HDC_Write(const uint32 Addr, uint8 cData); +static t_stat IBC_HDC_doCommand(void); +static const char* ibc_hdc_description(DEVICE *dptr); + +static UNIT ibc_hdc_unit[] = { + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_HDC_CAPACITY) }, + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_HDC_CAPACITY) }, + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_HDC_CAPACITY) }, + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_HDC_CAPACITY) } +}; + +static REG ibc_hdc_reg[] = { + { HRDATAD (TF_ERROR, ibc_hdc_info_data.error_reg, 8, "Taskfile Error Register"), }, + { HRDATAD (TF_STATUS, ibc_hdc_info_data.status_reg, 8, "Taskfile Status Register"), }, + { HRDATAD (TF_CSEC, ibc_hdc_info_data.taskfile[TF_CSEC], 8, "Taskfile Current Sector Register"), }, + { HRDATAD (TF_HEAD, ibc_hdc_info_data.taskfile[TF_HEAD], 8, "Taskfile Current Head Register"), }, + { HRDATAD (TF_NSEC, ibc_hdc_info_data.taskfile[TF_NSEC], 8, "Taskfile Sector Count Register"), }, + { HRDATAD (TF_SA3, ibc_hdc_info_data.taskfile[TF_SA3], 8, "Taskfile SA3 Register"), }, + { HRDATAD (TF_CMD, ibc_hdc_info_data.taskfile[TF_CMD], 8, "Taskfile Command Register"), }, + { HRDATAD (TF_DRIVE, ibc_hdc_info_data.taskfile[TF_DRIVE], 8, "Taskfile Drive Register"), }, + { HRDATAD (TF_TRKL, ibc_hdc_info_data.taskfile[TF_TRKL], 8, "Taskfile Track Low Register"), }, + { HRDATAD (TF_TRKH, ibc_hdc_info_data.taskfile[TF_TRKH], 8, "Taskfile Track High Register"), }, + { HRDATAD (TF_FIFO, ibc_hdc_info_data.taskfile[TF_FIFO], 8, "Data FIFO"), }, + { NULL } +}; + +#define IBC_HDC_NAME "IBC MCC ST-506 Hard Disk Controller" + +static const char* ibc_hdc_description(DEVICE *dptr) { + if (dptr == NULL) { + return NULL; + } + + return IBC_HDC_NAME; +} + +static MTAB ibc_hdc_mod[] = { + { MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", + &set_iobase, &show_iobase, NULL, "Sets disk controller I/O base address" }, + { MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "GEOMETRY", "GEOMETRY", + &ibc_hdc_unit_set_geometry, &ibc_hdc_unit_show_geometry, NULL, + "Set disk geometry C:nnnn/H:n/S:nnn/N:nnnn" }, + { 0 } +}; + +/* Debug Flags */ +static DEBTAB ibc_hdc_dt[] = { + { "ERROR", ERROR_MSG, "Error messages" }, + { "CMD", CMD_MSG, "Command messages" }, + { "READ", RD_DATA_MSG, "Read messages" }, + { "WRITE", WR_DATA_MSG, "Write messages" }, + { "FIFO", FIFO_MSG, "FIFO messages" }, + { "TF", TF_MSG, "Taskfile messages" }, + { "VERBOSE", VERBOSE_MSG, "Verbose messages" }, + { NULL, 0 } +}; + +DEVICE ibc_hdc_dev = { + DEV_NAME, ibc_hdc_unit, ibc_hdc_reg, ibc_hdc_mod, + IBC_HDC_MAX_DRIVES, 10, 31, 1, IBC_HDC_MAX_DRIVES, IBC_HDC_MAX_DRIVES, + NULL, NULL, &ibc_hdc_reset, + NULL, &ibc_hdc_attach, &ibc_hdc_detach, + &ibc_hdc_info_data, (DEV_DISABLE | DEV_DIS | DEV_DEBUG), ERROR_MSG, + ibc_hdc_dt, NULL, NULL, NULL, NULL, NULL, &ibc_hdc_description +}; + +/* Reset routine */ +static t_stat ibc_hdc_reset(DEVICE *dptr) +{ + PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt; + + if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */ + sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ibchdcdev, "ibchdcdev", TRUE); + } else { + /* Connect IBC_HDC at base address */ + if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ibchdcdev, "ibchdcdev", FALSE) != 0) { + sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base); + return SCPE_ARG; + } + } + + ibc_hdc_info->status_reg = 0x80; + ibc_hdc_info->error_reg = 0; + ibc_hdc_info->sel_drive = 0; + return SCPE_OK; +} + + +/* Attach routine */ +static t_stat ibc_hdc_attach(UNIT *uptr, CONST char *cptr) +{ + t_stat r = SCPE_OK; + IBC_HDC_DRIVE_INFO *pDrive; + int i = 0; + + i = find_unit_index(uptr); + if (i == -1) { + return (SCPE_IERR); + } + pDrive = &ibc_hdc_info->drive[i]; + + /* Defaults for the Quantum 2020 Drive */ + pDrive->ready = 0; + if (pDrive->ncyls == 0) { + /* If geometry was not specified, default to Quantun 2020 */ + pDrive->ncyls = 512; + pDrive->nheads = 4; + pDrive->nsectors = 32; + pDrive->sectsize = 256; + } + + r = attach_unit(uptr, cptr); /* attach unit */ + if ( r != SCPE_OK) /* error? */ + return r; + + /* Determine length of this disk */ + if(sim_fsize(uptr->fileref) != 0) { + uptr->capac = sim_fsize(uptr->fileref); + } else { + uptr->capac = (pDrive->ncyls * pDrive->nsectors * pDrive->nheads * pDrive->sectsize); + } + + pDrive->uptr = uptr; + + /* Default for new file is DSK */ + uptr->u3 = IMAGE_TYPE_DSK; + + if(uptr->capac > 0) { + r = assignDiskType(uptr); + if (r != SCPE_OK) { + ibc_hdc_detach(uptr); + return r; + } + } + + sim_debug(VERBOSE_MSG, &ibc_hdc_dev, DEV_NAME "%d, attached to '%s', type=DSK, len=%d\n", + i, cptr, uptr->capac); + + pDrive->readonly = (uptr->flags & UNIT_RO) ? 1 : 0; + ibc_hdc_info->error_reg = 0; + pDrive->ready = 1; + + return SCPE_OK; +} + + +/* Detach routine */ +static t_stat ibc_hdc_detach(UNIT *uptr) +{ + IBC_HDC_DRIVE_INFO *pDrive; + t_stat r; + int32 i; + + i = find_unit_index(uptr); + + if (i == -1) { + return (SCPE_IERR); + } + + pDrive = &ibc_hdc_info->drive[i]; + + pDrive->ready = 0; + + sim_debug(VERBOSE_MSG, &ibc_hdc_dev, "Detach " DEV_NAME "%d\n", i); + + r = detach_unit(uptr); /* detach unit */ + if ( r != SCPE_OK) + return r; + + return SCPE_OK; +} + +/* Set geometry of the disk drive */ +static t_stat ibc_hdc_unit_set_geometry(UNIT* uptr, int32 value, CONST char* cptr, void* desc) +{ + IBC_HDC_DRIVE_INFO* pDrive; + int32 i; + int32 result; + uint16 newCyls, newHeads, newSPT, newSecLen; + + i = find_unit_index(uptr); + + if (i == -1) { + return (SCPE_IERR); + } + + pDrive = &ibc_hdc_info->drive[i]; + + if (cptr == NULL) + return SCPE_ARG; + + result = sscanf(cptr, "C:%hd/H:%hd/S:%hd/N:%hd", &newCyls, &newHeads, &newSPT, &newSecLen); + if (result != 4) + return SCPE_ARG; + + /* Validate Cyl, Heads, Sector, Length */ + if (newCyls < 1 || newCyls > IBC_HDC_MAX_CYLS) { + sim_debug(ERROR_MSG, &ibc_hdc_dev, DEV_NAME "%d: Number of cylinders must be 1-%d.\n", + ibc_hdc_info->sel_drive, IBC_HDC_MAX_CYLS); + return SCPE_ARG; + } + if (newHeads < 1 || newHeads > IBC_HDC_MAX_HEADS) { + sim_debug(ERROR_MSG, &ibc_hdc_dev, DEV_NAME "%d: Number of heads must be 1-%d.\n", + ibc_hdc_info->sel_drive, IBC_HDC_MAX_HEADS); + return SCPE_ARG; + } + if (newSPT < 1 || newSPT > IBC_HDC_MAX_SPT) { + sim_debug(ERROR_MSG, &ibc_hdc_dev, DEV_NAME "%d: Number of sectors per track must be 1-%d.\n", + ibc_hdc_info->sel_drive, IBC_HDC_MAX_SPT); + return SCPE_ARG; + } + if (newSecLen != 512 && newSecLen != 256 && newSecLen != 128) { + sim_debug(ERROR_MSG, &ibc_hdc_dev,DEV_NAME "%d: Sector length must be 128, 256, or 512.\n", + ibc_hdc_info->sel_drive); + return SCPE_ARG; + } + + pDrive->ncyls = newCyls; + pDrive->nheads = newHeads; + pDrive->nsectors = newSPT; + pDrive->sectsize = newSecLen; + + return SCPE_OK; +} + +/* Show geometry of the disk drive */ +static t_stat ibc_hdc_unit_show_geometry(FILE* st, UNIT* uptr, int32 value, CONST void* desc) +{ + IBC_HDC_DRIVE_INFO* pDrive; + int32 i; + + i = find_unit_index(uptr); + + if (i == -1) { + return (SCPE_IERR); + } + + pDrive = &ibc_hdc_info->drive[i]; + + fprintf(st, "C:%d/H:%d/S:%d/N:%d", + pDrive->ncyls, pDrive->nheads, pDrive->nsectors, pDrive->sectsize); + + return SCPE_OK; +} + + +/* IBC HDC I/O Dispatch */ +static int32 ibchdcdev(const int32 port, const int32 io, const int32 data) +{ + if(io) { + IBC_HDC_Write(port, (uint8)data); + return 0; + } else { + return(IBC_HDC_Read(port)); + } +} + +/* I/O Write to IBC Disk Slave Task File */ +static uint8 IBC_HDC_Write(const uint32 Addr, uint8 cData) +{ + switch(Addr) { + case 0x40: + ibc_hdc_info->reg_temp_holding[0] = cData; + sim_debug(TF_MSG, &ibc_hdc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR 0x%02x=0x%02x, HL=0x%04x\n", PCX, Addr, cData, HL_S); + if (cData & 0x80) { + ibc_hdc_info->taskfile[TF_CMD] = ibc_hdc_info->reg_temp_holding[0]; + ibc_hdc_info->taskfile[TF_DRIVE] = ibc_hdc_info->reg_temp_holding[1]; + ibc_hdc_info->taskfile[TF_TRKL] = ibc_hdc_info->reg_temp_holding[2]; + ibc_hdc_info->taskfile[TF_TRKH] = ibc_hdc_info->reg_temp_holding[3]; + if ((ibc_hdc_info->taskfile[TF_CMD] & 0x80) != IBC_HDC_CMD_READ_PARAMETERS) { + ibc_hdc_info->sel_drive = ibc_hdc_info->taskfile[TF_DRIVE] & 0x03; + } + ibc_hdc_info->status_reg = 0x30; + } + else { + ibc_hdc_info->taskfile[TF_CSEC] = ibc_hdc_info->reg_temp_holding[0]; + ibc_hdc_info->taskfile[TF_HEAD] = ibc_hdc_info->reg_temp_holding[1]; + ibc_hdc_info->taskfile[TF_NSEC] = ibc_hdc_info->reg_temp_holding[2]; + ibc_hdc_info->taskfile[TF_SA3] = ibc_hdc_info->reg_temp_holding[3]; + ibc_hdc_info->status_reg = 0x20; + IBC_HDC_doCommand(); + } + break; + /* Fall through */ + case 0x41: + case 0x42: + case 0x43: + ibc_hdc_info->reg_temp_holding[Addr & 0x03] = cData; + sim_debug(TF_MSG, &ibc_hdc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR 0x%02x=0x%02x, HL=0x%04x\n", PCX, Addr, cData, HL_S); + break; + case IBC_HDC_REG_FIFO_STATUS: + ibc_hdc_info->secbuf_index = 0; + break; + case IBC_HDC_REG_FIFO: + sim_debug(FIFO_MSG, &ibc_hdc_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR FIFO 0x%02x=0x%02x, HL=0x%04x\n", PCX, Addr, cData, HL_S); + ibc_hdc_info->sectbuf[ibc_hdc_info->secbuf_index++] = cData; + break; + default: + sim_debug(TF_MSG, &ibc_hdc_dev, DEV_NAME ": " ADDRESS_FORMAT + " Unhandled WR 0x%02x=0x%02x\n", PCX, Addr, cData); + break; + } + + return 0; +} + + +/* I/O Read from IBC Disk Slave Task File */ +static uint8 IBC_HDC_Read(const uint32 Addr) +{ + uint8 cData = 0xFF; + + switch (Addr) { + case IBC_HDC_REG_STATUS: + cData = ibc_hdc_info->status_reg; + sim_debug(TF_MSG, &ibc_hdc_dev,DEV_NAME ": " ADDRESS_FORMAT + " RD TF[STATUS]=0x%02x\n", PCX, cData); + break; + case IBC_HDC_REG_FIFO: + cData = ibc_hdc_info->sectbuf[ibc_hdc_info->secbuf_index]; + + sim_debug(FIFO_MSG, &ibc_hdc_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD TF[FIFO][0x%02x]=0x%02x\n", PCX, ibc_hdc_info->secbuf_index, cData); + ibc_hdc_info->secbuf_index++; + break; + case IBC_HDC_REG_FIFO_STATUS: + break; + default: + sim_debug(TF_MSG, &ibc_hdc_dev, DEV_NAME ": " ADDRESS_FORMAT + " Unhandled RD 0x%02x=0x%02x\n", PCX, Addr, cData); + break; + } + + return (cData); +} + +/* Validate that Cyl, Head, Sector, Sector Length are valid for the current + * disk drive geometry. + */ +static int IBC_HDC_Validate_CHSN(IBC_HDC_DRIVE_INFO* pDrive) +{ + int status = SCPE_OK; + + /* Check to make sure we're operating on a valid C/H/S/N. */ + if ((pDrive->cur_cyl >= pDrive->ncyls) || + (pDrive->cur_head >= pDrive->nheads) || + (pDrive->cur_sect >= pDrive->nsectors) || + (pDrive->cur_sectsize != pDrive->sectsize)) + { + /* Set error bit in status register. */ + ibc_hdc_info->status_reg |= IBC_HDC_STATUS_ERROR; + + /* Set ID_NOT_FOUND bit in error register. */ + ibc_hdc_info->error_reg |= IBC_HDC_ERROR_ID_NOT_FOUND; + + sim_debug(ERROR_MSG, &ibc_hdc_dev,DEV_NAME "%d: " ADDRESS_FORMAT + " C:%d/H:%d/S:%d/N:%d: ID Not Found (check disk geometry.)\n", ibc_hdc_info->sel_drive, PCX, + pDrive->cur_cyl, + pDrive->cur_head, + pDrive->cur_sect, + pDrive->cur_sectsize); + + status = SCPE_IOERR; + } + else { + /* Clear ID_NOT_FOUND bit in error register. */ + ibc_hdc_info->error_reg &= ~IBC_HDC_ERROR_ID_NOT_FOUND; + } + + return (status); +} + +/* 85MB Fixed Disk Drive 0: C:680/H:15/N:32/L:256 + * 10MB Removable Cartridge Drive 3: C:612/H:2/N:32/L:256 + */ +unsigned char HDParameters[108] = { + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // 0x00 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, // 0x08 0088=136 + 0x00, 0x10, 0x01, 0x00, 0x00, 0x98, 0x01, 0x00, // 0x10 0110=272, 0198=408 + 0x00, 0x20, 0x02, 0x00, 0x03, 0x00, 0x00, 0x00, // 0x18 0220=544 + 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x61, 0x62, // 0x20 + 0x20, 0x00, 0x61, 0x02, 0x02, 0x00, 0x00, 0x00, // 0x28 + 0x0F, 0x00, 0x88, 0x00, 0x20, 0x00, 0x1D, 0x03, // 0x30=#heads + 0x0F, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // 0x38 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // 0x40 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x02, 0x00, // 0x48 + 0x61, 0x62, 0x20, 0x00, 0x61, 0x02, 0x02, 0x00, // 0x50 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // 0x58 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // 0x60 + 0xFF, 0xFF, 0xFF, 0xFF // 0x68 +}; + +/* Perform IBC Disk Controller Command */ +static t_stat IBC_HDC_doCommand(void) +{ + t_stat r = SCPE_OK; + IBC_HDC_DRIVE_INFO* pDrive = &ibc_hdc_info->drive[ibc_hdc_info->sel_drive]; + uint8 cmd = ibc_hdc_info->taskfile[TF_CMD] & 0x7F; + + pDrive->cur_cyl = ibc_hdc_info->taskfile[TF_TRKH] << 8; + pDrive->cur_cyl |= ibc_hdc_info->taskfile[TF_TRKL]; + pDrive->xfr_nsects = ibc_hdc_info->taskfile[TF_NSEC]; + pDrive->cur_head = ibc_hdc_info->taskfile[TF_HEAD]; + pDrive->cur_sect = ibc_hdc_info->taskfile[TF_CSEC]; + pDrive->cur_sectsize = 256; + if (pDrive->xfr_nsects == 0) { + pDrive->xfr_nsects = 1; + } + + switch (cmd) { + case IBC_HDC_CMD_RESET: /* Reset */ + sim_debug(ERROR_MSG, &ibc_hdc_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " RESET COMMAND 0x%02x\n", + ibc_hdc_info->sel_drive, PCX, + cmd); + ibc_hdc_info->status_reg = 0x20; + break; + case IBC_HDC_CMD_READ_SECT: + case IBC_HDC_CMD_WRITE_SECT: + { + uint32 xfr_len; + uint32 file_offset; + + sim_debug(CMD_MSG, &ibc_hdc_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " CMD: %02x: Params 0x%02x,%02x,%02x - 0x%02x,%02x,%02x,%02x.\n", ibc_hdc_info->sel_drive, PCX, + ibc_hdc_info->taskfile[TF_CMD], ibc_hdc_info->taskfile[TF_TRKH], ibc_hdc_info->taskfile[TF_TRKL], ibc_hdc_info->taskfile[TF_DRIVE], + ibc_hdc_info->taskfile[TF_SA3], ibc_hdc_info->taskfile[TF_NSEC], ibc_hdc_info->taskfile[TF_HEAD], ibc_hdc_info->taskfile[TF_CSEC]); + + /* Abort the read/write operation if C/H/S/N is not valid. */ + if (IBC_HDC_Validate_CHSN(pDrive) != SCPE_OK) break; + + /* Calculate file offset */ + file_offset = (pDrive->cur_cyl * pDrive->nheads * pDrive->nsectors); /* Full cylinders */ + file_offset += (pDrive->cur_head * pDrive->nsectors); /* Add full heads */ + file_offset += (pDrive->cur_sect); /* Add sectors for current request */ + file_offset *= pDrive->sectsize; /* Convert #sectors to byte offset */ + + xfr_len = pDrive->xfr_nsects * pDrive->sectsize; + + if (0 != (r = sim_fseek((pDrive->uptr)->fileref, file_offset, SEEK_SET))) + break; + + if (cmd == IBC_HDC_CMD_READ_SECT) { /* Read */ + sim_debug(RD_DATA_MSG, &ibc_hdc_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " READ SECTOR C:%04d/H:%d/S:%04d/#:%d, offset=%5x, len=%d\n", + ibc_hdc_info->sel_drive, PCX, + pDrive->cur_cyl, pDrive->cur_head, + pDrive->cur_sect, pDrive->xfr_nsects, file_offset, xfr_len); + if (sim_fread(ibc_hdc_info->sectbuf, 1, xfr_len, (pDrive->uptr)->fileref) != xfr_len) { + r = SCPE_IOERR; + } + ibc_hdc_info->status_reg = 0x60; + } + else { /* Write */ + sim_debug(WR_DATA_MSG, &ibc_hdc_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " WRITE SECTOR C:%04d/H:%d/S:%04d/#:%d, offset=%5x, len=%d\n", + ibc_hdc_info->sel_drive, PCX, + pDrive->cur_cyl, pDrive->cur_head, + pDrive->cur_sect, pDrive->xfr_nsects, file_offset, xfr_len); + + if (sim_fwrite(ibc_hdc_info->sectbuf, 1, xfr_len, (pDrive->uptr)->fileref) != xfr_len) { + r = SCPE_IOERR; + } + + ibc_hdc_info->status_reg = 0x60; + } + break; + } + case IBC_HDC_CMD_FORMAT_TRK: + { + uint32 data_len; + uint32 file_offset; + uint8* fmtBuffer; + + sim_debug(WR_DATA_MSG, &ibc_hdc_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " FORMAT TRACK C:%04d/H:%d\n", + ibc_hdc_info->sel_drive, PCX, + pDrive->cur_cyl, pDrive->cur_head); + + data_len = pDrive->nsectors * pDrive->sectsize; + + /* Abort the read/write operation if C/H/S/N is not valid. */ + if (IBC_HDC_Validate_CHSN(pDrive) != SCPE_OK) break; + + sim_debug(WR_DATA_MSG, &ibc_hdc_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " FORMAT TRACK: C:%d/H:%d/Fill=0x%02x/Len=%d\n", + ibc_hdc_info->sel_drive, PCX, pDrive->cur_cyl, + pDrive->cur_head, IBC_HDC_FORMAT_FILL_BYTE, data_len); + + /* Calculate file offset, formatting always handles a full track at a time. */ + file_offset = (pDrive->cur_cyl * pDrive->nheads * pDrive->nsectors); /* Full cylinders */ + file_offset += (pDrive->cur_head * pDrive->nsectors); /* Add full heads */ + file_offset *= pDrive->sectsize; /* Convert #sectors to byte offset */ + + fmtBuffer = calloc(data_len, sizeof(uint8)); + + if (fmtBuffer == 0) { + return sim_messagef(SCPE_MEM, "Cannot allocate %d bytes for format buffer.\n", data_len); + } + +#if (IBC_HDC_FORMAT_FILL_BYTE != 0) + memset(fmtBuffer, IBC_HDC_FORMAT_FILL_BYTE, data_len); +#endif + + if (0 != (r = sim_fseek((pDrive->uptr)->fileref, file_offset, SEEK_SET))) { + if (sim_fwrite(fmtBuffer, 1, data_len, (pDrive->uptr)->fileref) != data_len) { + r = SCPE_IOERR; + } + } + + free(fmtBuffer); + ibc_hdc_info->status_reg = 0x20; + + break; + } + case IBC_HDC_CMD_ACCESS_FIFO: /* Access FIFO */ + sim_debug(WR_DATA_MSG, &ibc_hdc_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " ACCESS FIFO %d blocks.\n", + ibc_hdc_info->sel_drive, PCX, + ibc_hdc_info->taskfile[TF_NSEC]); + ibc_hdc_info->secbuf_index = 0; + ibc_hdc_info->status_reg = 0x20; + break; + case IBC_HDC_CMD_READ_PARAMETERS: /* Read Drive Parameters */ + sim_debug(ERROR_MSG, &ibc_hdc_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " READ DRIVE PARAMETERS C:%0d/H:%d/S:%2d\n", + ibc_hdc_info->sel_drive, PCX, + pDrive->cur_cyl, pDrive->cur_head, pDrive->cur_sect); + memcpy(ibc_hdc_info->sectbuf, HDParameters, sizeof(HDParameters)); + ibc_hdc_info->status_reg = 0x60; + break; + default: + sim_debug(ERROR_MSG, &ibc_hdc_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " UNKNOWN COMMAND 0x%02x\n", + ibc_hdc_info->sel_drive, PCX, + cmd); + ibc_hdc_info->status_reg = 0x60; + break; + } + return r; +} diff --git a/AltairZ80/ibc_smd_hdc.c b/AltairZ80/ibc_smd_hdc.c new file mode 100644 index 00000000..421cb727 --- /dev/null +++ b/AltairZ80/ibc_smd_hdc.c @@ -0,0 +1,614 @@ +/************************************************************************* + * * + * Copyright (c) 2021-2023 Howard M. Harte. * + * https://github.com/hharte * + * * + * Permission is hereby granted, free of charge, to any person obtaining * + * a copy of this software and associated documentation files (the * + * "Software"), to deal in the Software without restriction, including * + * without limitation the rights to use, copy, modify, merge, publish, * + * distribute, sublicense, and/or sell copies of the Software, and to * + * permit persons to whom the Software is furnished to do so, subject to * + * the following conditions: * + * * + * The above copyright notice and this permission notice shall be * + * included in all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON- * + * INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE * + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * + * SOFTWARE. * + * * + * Except as contained in this notice, the names of The Authors shall * + * not be used in advertising or otherwise to promote the sale, use or * + * other dealings in this Software without prior written authorization * + * from the Authors. * + * * + * Module Description: * + * IBC/Integrated Business Computers SMD Hard Disk Controller module * + * for SIMH. * + * * + *************************************************************************/ + +#include "altairz80_defs.h" +#include "sim_imd.h" + +/* Debug flags */ +#define ERROR_MSG (1 << 0) +#define CMD_MSG (1 << 1) +#define RD_DATA_MSG (1 << 2) +#define WR_DATA_MSG (1 << 3) +#define FIFO_MSG (1 << 4) +#define REG_MSG (1 << 5) +#define VERBOSE_MSG (1 << 6) + +#define IBC_SMD_MAX_DRIVES 2 /* Maximum number of drives supported */ +#define IBC_SMD_MAX_SECLEN 1024 /* Maximum of 1024 bytes per sector */ +#define IBC_SMD_MAX_CYLS 1024 +#define IBC_SMD_MAX_HEADS 8 +#define IBC_SMD_MAX_SPT 256 + +#define DEV_NAME "IBCSMD" + +#define IBC_SMD_STATUS_ERROR (1 << 0) + +#define IBC_SMD_ERROR_ID_NOT_FOUND (1 << 4) + +#define IBC_SMD_CMD_00 0x00 +#define IBC_SMD_CMD_SELECT_UNIT 0x10 +#define IBC_SMD_CMD_SET_CYL 0x20 +#define IBC_SMD_CMD_SET_HEAD 0x40 +#define IBC_SMD_CMD_REZERO 0x80 +#define IBC_SMD_CMD_WRITE_SECT 0x81 +#define IBC_SMD_CMD_READ_SECT 0x88 + +#define IBC_SMD_REG_ERROR 0x0 /* Read */ +#define IBC_SMD_REG_ARG0 0x0 /* Write */ +#define IBC_SMD_REG_ARG1 0x1 /* Write */ +#define IBC_SMD_REG_CMD 0x2 /* Write */ +#define IBC_SMD_REG_SEC 0x3 /* Write */ +#define IBC_SMD_REG_STATUS 0x7 +#define IBC_SMD_REG_DATA 0x4 +#define IBC_SMD_REG_SECID 0x7 + +typedef struct { + UNIT *uptr; + uint8 readonly; /* Drive is read-only? */ + uint16 sectsize; /* sector size */ + uint16 nsectors; /* number of sectors/track */ + uint16 nheads; /* number of heads */ + uint16 ncyls; /* number of cylinders */ + uint16 cur_cyl; /* Current cylinder */ + uint8 cur_head; /* Current Head */ + uint8 cur_sect; /* current starting sector of transfer */ + uint8 ready; /* Is drive ready? */ +} IBC_SMD_DRIVE_INFO; + +typedef struct { + PNP_INFO pnp; /* Plug and Play */ + uint8 intenable; /* Interrupt Enable */ + uint8 intvector; /* Interrupt Vector */ + uint8 sel_drive; /* Currently selected drive */ + uint8 arg0; /* IBC SMD Argument 0 Register */ + uint8 arg1; /* IBC SMD Argument 1 Register */ + uint8 cmd; /* IBC SMD Command Register */ + uint8 sec; /* IBC SMD Sector Register */ + uint8 status_reg; /* Status Register */ + uint8 error_reg; /* Error Register */ + uint8 retries; /* Number of retries to attempt */ + uint8 ndrives; /* Number of drives attached to the controller */ + uint8 sectbuf[IBC_SMD_MAX_SECLEN]; + uint16 secbuf_index; + IBC_SMD_DRIVE_INFO drive[IBC_SMD_MAX_DRIVES]; +} IBC_SMD_INFO; + +static IBC_SMD_INFO ibc_smd_info_data = { { 0x0, 0, 0x40, 8 } }; +static IBC_SMD_INFO *ibc_smd_info = &ibc_smd_info_data; + +extern uint32 PCX; +extern int32 vectorInterrupt; /* Interrupt pending */ + +extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc); +extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc); +extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type, + int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap); +extern int32 find_unit_index(UNIT *uptr); + +#define UNIT_V_IBC_SMD_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */ +#define UNIT_IBC_SMD_VERBOSE (1 << UNIT_V_IBC_SMD_VERBOSE) +#define IBC_SMD_CAPACITY (512*4*16*512) /* Default Disk Capacity Quantum 2020 */ + +static t_stat ibc_smd_reset(DEVICE *ibc_smd_dev); +static t_stat ibc_smd_attach(UNIT *uptr, CONST char *cptr); +static t_stat ibc_smd_detach(UNIT *uptr); +static t_stat ibc_smd_unit_set_geometry(UNIT* uptr, int32 value, CONST char* cptr, void* desc); +static t_stat ibc_smd_unit_show_geometry(FILE* st, UNIT* uptr, int32 value, CONST void* desc); +static int32 ibcsmddev(const int32 port, const int32 io, const int32 data); + +static uint8 IBC_SMD_Read(const uint32 Addr); +static uint8 IBC_SMD_Write(const uint32 Addr, uint8 cData); +static t_stat IBC_SMD_doCommand(void); +static const char* ibc_smd_description(DEVICE *dptr); + +static UNIT ibc_smd_unit[] = { + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_SMD_CAPACITY) }, + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_SMD_CAPACITY) }, + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_SMD_CAPACITY) }, + { UDATA (NULL, UNIT_FIX + UNIT_ATTABLE + UNIT_DISABLE + UNIT_ROABLE, IBC_SMD_CAPACITY) } +}; + +static REG ibc_smd_reg[] = { + { HRDATAD (SMD_ERROR, ibc_smd_info_data.error_reg, 8, "SMD Error Register"), }, + { HRDATAD (SMD_STATUS, ibc_smd_info_data.status_reg, 8, "SMD Status Register"), }, + { HRDATAD (SMD_ARG0, ibc_smd_info_data.arg0, 8, "SMD ARG0 Register"), }, + { HRDATAD (SMD_ARG1, ibc_smd_info_data.arg1, 8, "SMD ARG1 Register"), }, + { HRDATAD (SMD_CMD, ibc_smd_info_data.cmd, 8, "SMD Command Register"), }, + { HRDATAD (SMD_SEC, ibc_smd_info_data.sec, 8, "SMD Sector Register"), }, + { FLDATAD (INTENABLE, ibc_smd_info_data.intenable, 1, "SMD Interrupt Enable"), }, + { DRDATAD (INTVECTOR, ibc_smd_info_data.intvector, 8, "SMD Interrupt Vector"), }, + + { NULL } +}; + +#define IBC_SMD_NAME "IBC SMD Hard Disk Controller" + +static const char* ibc_smd_description(DEVICE *dptr) { + if (dptr == NULL) { + return NULL; + } + + return IBC_SMD_NAME; +} + +static MTAB ibc_smd_mod[] = { + { MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", + &set_iobase, &show_iobase, NULL, "Sets disk controller I/O base address" }, + { MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "GEOMETRY", "GEOMETRY", + &ibc_smd_unit_set_geometry, &ibc_smd_unit_show_geometry, NULL, + "Set disk geometry C:nnnn/H:n/S:nnn/N:nnnn" }, + { 0 } +}; + +/* Debug Flags */ +static DEBTAB ibc_smd_dt[] = { + { "ERROR", ERROR_MSG, "Error messages" }, + { "REG", REG_MSG, "Register messages" }, + { "CMD", CMD_MSG, "Command messages" }, + { "READ", RD_DATA_MSG, "Read messages" }, + { "WRITE", WR_DATA_MSG, "Write messages" }, + { "FIFO", FIFO_MSG, "FIFO messages" }, + { "VERBOSE", VERBOSE_MSG, "Verbose messages" }, + { NULL, 0 } +}; + +DEVICE ibc_smd_dev = { + DEV_NAME, ibc_smd_unit, ibc_smd_reg, ibc_smd_mod, + IBC_SMD_MAX_DRIVES, 10, 31, 1, IBC_SMD_MAX_DRIVES, IBC_SMD_MAX_DRIVES, + NULL, NULL, &ibc_smd_reset, + NULL, &ibc_smd_attach, &ibc_smd_detach, + &ibc_smd_info_data, (DEV_DISABLE | DEV_DIS | DEV_DEBUG), ERROR_MSG, + ibc_smd_dt, NULL, NULL, NULL, NULL, NULL, &ibc_smd_description +}; + +/* Reset routine */ +static t_stat ibc_smd_reset(DEVICE *dptr) +{ + PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt; + + if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */ + sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ibcsmddev, "ibcsmddev", TRUE); + } else { + /* Connect IBC_SMD at base address */ + if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ibcsmddev, "ibcsmddev", FALSE) != 0) { + sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base); + return SCPE_ARG; + } + } + + ibc_smd_info->status_reg = 0xd1; + ibc_smd_info->error_reg = 0x80; + ibc_smd_info->sel_drive = 0; + return SCPE_OK; +} + + +/* Attach routine */ +static t_stat ibc_smd_attach(UNIT *uptr, CONST char *cptr) +{ + t_stat r = SCPE_OK; + IBC_SMD_DRIVE_INFO *pDrive; + int i = 0; + + i = find_unit_index(uptr); + if (i == -1) { + return (SCPE_IERR); + } + pDrive = &ibc_smd_info->drive[i]; + + /* Defaults for the Quantum 2020 Drive */ + pDrive->ready = 0; + if (pDrive->ncyls == 0) { + /* If geometry was not specified, default to Quantun 2020 */ + pDrive->ncyls = 512; + pDrive->nheads = 4; + pDrive->nsectors = 16; + pDrive->sectsize = 512; + } + + r = attach_unit(uptr, cptr); /* attach unit */ + if ( r != SCPE_OK) /* error? */ + return r; + + /* Determine length of this disk */ + if(sim_fsize(uptr->fileref) != 0) { + uptr->capac = sim_fsize(uptr->fileref); + } else { + uptr->capac = (pDrive->ncyls * pDrive->nsectors * pDrive->nheads * pDrive->sectsize); + } + + pDrive->uptr = uptr; + + /* Default for new file is DSK */ + uptr->u3 = IMAGE_TYPE_DSK; + + if(uptr->capac > 0) { + r = assignDiskType(uptr); + if (r != SCPE_OK) { + ibc_smd_detach(uptr); + return r; + } + } + + sim_debug(VERBOSE_MSG, &ibc_smd_dev, DEV_NAME "%d, attached to '%s', type=DSK, len=%d\n", + i, cptr, uptr->capac); + + pDrive->readonly = (uptr->flags & UNIT_RO) ? 1 : 0; + ibc_smd_info->error_reg = 0; + pDrive->ready = 1; + + ibc_smd_info->status_reg = 0; + + return SCPE_OK; +} + + +/* Detach routine */ +static t_stat ibc_smd_detach(UNIT *uptr) +{ + IBC_SMD_DRIVE_INFO *pDrive; + t_stat r; + int32 i; + + i = find_unit_index(uptr); + + if (i == -1) { + return (SCPE_IERR); + } + + pDrive = &ibc_smd_info->drive[i]; + + pDrive->ready = 0; + + sim_debug(VERBOSE_MSG, &ibc_smd_dev, "Detach " DEV_NAME "%d\n", i); + + r = detach_unit(uptr); /* detach unit */ + if ( r != SCPE_OK) + return r; + + return SCPE_OK; +} + +/* Set geometry of the disk drive */ +static t_stat ibc_smd_unit_set_geometry(UNIT* uptr, int32 value, CONST char* cptr, void* desc) +{ + IBC_SMD_DRIVE_INFO* pDrive; + int32 i; + int32 result; + uint16 newCyls, newHeads, newSPT, newSecLen; + + i = find_unit_index(uptr); + + if (i == -1) { + return (SCPE_IERR); + } + + pDrive = &ibc_smd_info->drive[i]; + + if (cptr == NULL) + return SCPE_ARG; + + result = sscanf(cptr, "C:%hd/H:%hd/S:%hd/N:%hd", &newCyls, &newHeads, &newSPT, &newSecLen); + if (result != 4) + return SCPE_ARG; + + /* Validate Cyl, Heads, Sector, Length */ + if (newCyls < 1 || newCyls > IBC_SMD_MAX_CYLS) { + sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME "%d: Number of cylinders must be 1-%d.\n", + ibc_smd_info->sel_drive, IBC_SMD_MAX_CYLS); + return SCPE_ARG; + } + if (newHeads < 1 || newHeads > IBC_SMD_MAX_HEADS) { + sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME "%d: Number of heads must be 1-%d.\n", + ibc_smd_info->sel_drive, IBC_SMD_MAX_HEADS); + return SCPE_ARG; + } + if (newSPT < 1 || newSPT > IBC_SMD_MAX_SPT) { + sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME "%d: Number of sectors per track must be 1-%d.\n", + ibc_smd_info->sel_drive, IBC_SMD_MAX_SPT); + return SCPE_ARG; + } + if (newSecLen != 512 && newSecLen != 256 && newSecLen != 128) { + sim_debug(ERROR_MSG, &ibc_smd_dev,DEV_NAME "%d: Sector length must be 128, 256, or 512.\n", + ibc_smd_info->sel_drive); + return SCPE_ARG; + } + + pDrive->ncyls = newCyls; + pDrive->nheads = newHeads; + pDrive->nsectors = newSPT; + pDrive->sectsize = newSecLen; + + return SCPE_OK; +} + +/* Show geometry of the disk drive */ +static t_stat ibc_smd_unit_show_geometry(FILE* st, UNIT* uptr, int32 value, CONST void* desc) +{ + IBC_SMD_DRIVE_INFO* pDrive; + int32 i; + + i = find_unit_index(uptr); + + if (i == -1) { + return (SCPE_IERR); + } + + pDrive = &ibc_smd_info->drive[i]; + + fprintf(st, "C:%d/H:%d/S:%d/N:%d", + pDrive->ncyls, pDrive->nheads, pDrive->nsectors, pDrive->sectsize); + + return SCPE_OK; +} + + +/* IBC SMD I/O Dispatch */ +static int32 ibcsmddev(const int32 port, const int32 io, const int32 data) +{ + if(io) { + IBC_SMD_Write(port, (uint8)data); + return 0; + } else { + return(IBC_SMD_Read(port)); + } +} + +/* I/O Write to IBC SMD Registers */ +static uint8 IBC_SMD_Write(const uint32 Addr, uint8 cData) +{ + switch(Addr & 7) { + case IBC_SMD_REG_ARG0: + switch (cData) { + case 0x00: + ibc_smd_info->error_reg = 0x0; + break; + case 0x01: + ibc_smd_info->error_reg = 0x20; + break; + case IBC_SMD_CMD_READ_SECT: + ibc_smd_info->error_reg = 0x30; + break; + default: + ibc_smd_info->error_reg = 0x30; + break; + } + ibc_smd_info->arg0 = cData; + sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR SMD_ARG0 0x%02x=0x%02x\n", PCX, Addr, cData); + break; + case IBC_SMD_REG_ARG1: + ibc_smd_info->arg1 = cData; + sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR SMD_ARG1 0x%02x=0x%02x\n", PCX, Addr, cData); + break; + case IBC_SMD_REG_CMD: + ibc_smd_info->cmd = cData; + sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR SMD_CMD 0x%02x=0x%02x\n", PCX, Addr, cData); + IBC_SMD_doCommand(); + break; + case IBC_SMD_REG_SEC: + ibc_smd_info->sec = cData; + sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR SMD_SEC 0x%02x=0x%02x\n", PCX, Addr, cData); + break; + case IBC_SMD_REG_SECID: + sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR SECID 0x%02x=0x%02x\n", PCX, Addr, cData); + ibc_smd_info->secbuf_index = 0; + break; + case IBC_SMD_REG_DATA: + sim_debug(FIFO_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT + " WR FIFO 0x%02x=0x%02x\n", PCX, Addr, cData); + ibc_smd_info->sectbuf[ibc_smd_info->secbuf_index] = cData; + ibc_smd_info->secbuf_index++; + break; + default: + sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT + " Unhandled WR 0x%02x=0x%02x\n", PCX, Addr, cData); + break; + } + + return 0; +} + +/* I/O Read from IBC SMD Registers */ +static uint8 IBC_SMD_Read(const uint32 Addr) +{ + uint8 cData = 0xFF; + + switch (Addr & 7) { + case IBC_SMD_REG_ERROR: + cData = ibc_smd_info->error_reg; + sim_debug(REG_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD ERROR 0x%02x=0x%02x\n", PCX, Addr, cData); + break; + case 0x1: + cData = 0x7f; + sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD Unknown 0x%02x=0x%02x\n", PCX, Addr, cData); + case IBC_SMD_REG_DATA: + cData = ibc_smd_info->sectbuf[ibc_smd_info->secbuf_index]; + sim_debug(FIFO_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT + " RD DATA[0x%02x]=0x%02x\n", PCX, ibc_smd_info->secbuf_index, cData); + ibc_smd_info->secbuf_index++; + break; + case IBC_SMD_REG_STATUS: + cData = ibc_smd_info->status_reg; + sim_debug(REG_MSG, &ibc_smd_dev,DEV_NAME ": " ADDRESS_FORMAT + " RD STATUS 0x%02x=0x%02x\n", PCX, Addr, cData); + break; + default: + sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME ": " ADDRESS_FORMAT + " Unhandled RD 0x%02x=0x%02x\n", PCX, Addr, cData); + break; + } + + return (cData); +} + +/* Validate that Cyl, Head, Sector are valid for the current + * disk drive geometry. + */ +static int IBC_SMD_Validate_CHSN(IBC_SMD_DRIVE_INFO* pDrive) +{ + int status = SCPE_OK; + + /* Check to make sure we're operating on a valid C/H/S/N. */ + if ((pDrive->cur_cyl >= pDrive->ncyls) || + (pDrive->cur_head >= pDrive->nheads) || + (pDrive->cur_sect >= pDrive->nsectors)) + { + /* Set error bit in status register. */ + ibc_smd_info->status_reg |= IBC_SMD_STATUS_ERROR; + + /* Set ID_NOT_FOUND bit in error register. */ + ibc_smd_info->error_reg |= IBC_SMD_ERROR_ID_NOT_FOUND; + + sim_debug(ERROR_MSG, &ibc_smd_dev,DEV_NAME "%d: " ADDRESS_FORMAT + " C:%d/H:%d/S:%d: ID Not Found (check disk geometry.)\n", ibc_smd_info->sel_drive, PCX, + pDrive->cur_cyl, + pDrive->cur_head, + pDrive->cur_sect); + + status = SCPE_IOERR; + } + else { + /* Clear ID_NOT_FOUND bit in error register. */ + ibc_smd_info->error_reg &= ~IBC_SMD_ERROR_ID_NOT_FOUND; + } + + return (status); +} + +/* Perform SMD Disk Command */ +static t_stat IBC_SMD_doCommand(void) +{ + t_stat r = SCPE_OK; + IBC_SMD_DRIVE_INFO* pDrive = &ibc_smd_info->drive[ibc_smd_info->sel_drive]; + uint8 cmd = ibc_smd_info->cmd; + + switch (cmd) { + case IBC_SMD_CMD_00: + break; + case IBC_SMD_CMD_SELECT_UNIT: + ibc_smd_info->sel_drive = (ibc_smd_info->arg0 >> 4) & 1; + sim_debug(CMD_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " 0x%02x: Select Unit %d\n", + ibc_smd_info->sel_drive, PCX, + cmd, ibc_smd_info->arg0 >> 4); + break; + case IBC_SMD_CMD_SET_CYL: /* Set Cyl */ + pDrive->cur_cyl = ibc_smd_info->arg0 << 8; + pDrive->cur_cyl |= ibc_smd_info->arg1; + sim_debug(CMD_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " 0x%02x: Set Cylinder %d\n", + ibc_smd_info->sel_drive, PCX, + cmd, pDrive->cur_cyl); + break; + case IBC_SMD_CMD_SET_HEAD: /* Set Head */ + pDrive->cur_head = ibc_smd_info->arg1; + sim_debug(CMD_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " 0x%02x: Set Head %d\n", + ibc_smd_info->sel_drive, PCX, + cmd, pDrive->cur_head); + break; + case IBC_SMD_CMD_REZERO: + sim_debug(CMD_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " 0x%02x: Rezero %d\n", + ibc_smd_info->sel_drive, PCX, + cmd, ibc_smd_info->arg1); + ibc_smd_info->status_reg = 0xd1; + break; + case IBC_SMD_CMD_READ_SECT: + case IBC_SMD_CMD_WRITE_SECT: + { + uint32 xfr_len; + uint32 file_offset; + + pDrive->cur_sect = ibc_smd_info->sec; + ibc_smd_info->secbuf_index = 0; + ibc_smd_info->sectbuf[0] = (pDrive->cur_cyl >> 8) & 0xFF; + ibc_smd_info->sectbuf[1] = pDrive->cur_cyl & 0xFF; + ibc_smd_info->sectbuf[2] = pDrive->cur_head; + ibc_smd_info->sectbuf[3] = pDrive->cur_sect; + + /* Abort the read/write operation if C/H/S/N is not valid. */ + if (IBC_SMD_Validate_CHSN(pDrive) != SCPE_OK) break; + + /* Calculate file offset */ + file_offset = (pDrive->cur_cyl * pDrive->nheads * pDrive->nsectors); /* Full cylinders */ + file_offset += (pDrive->cur_head * pDrive->nsectors); /* Add full heads */ + file_offset += (pDrive->cur_sect); /* Add sectors for current request */ + file_offset *= pDrive->sectsize; /* Convert #sectors to byte offset */ + + xfr_len = pDrive->sectsize; + + if (0 != (r = sim_fseek((pDrive->uptr)->fileref, file_offset, SEEK_SET))) + break; + + if (cmd == IBC_SMD_CMD_READ_SECT) { /* Read */ + sim_debug(RD_DATA_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " RD SECTOR C:%04d/H:%d/S:%04d, offset=%5x, len=%d\n", + ibc_smd_info->sel_drive, PCX, + pDrive->cur_cyl, pDrive->cur_head, pDrive->cur_sect, + file_offset, xfr_len); + if (sim_fread(&ibc_smd_info->sectbuf[4], 1, xfr_len, (pDrive->uptr)->fileref) != xfr_len) { + r = SCPE_IOERR; + } + } + else { /* Write */ + sim_debug(WR_DATA_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " WR SECTOR C:%04d/H:%d/S:%04d offset=%5x, len=%d\n", + ibc_smd_info->sel_drive, PCX, + pDrive->cur_cyl, pDrive->cur_head, pDrive->cur_sect, + file_offset, xfr_len); + if (sim_fwrite(&ibc_smd_info->sectbuf[4], 1, xfr_len, (pDrive->uptr)->fileref) != xfr_len) { + r = SCPE_IOERR; + } + } + break; + } + default: + sim_debug(ERROR_MSG, &ibc_smd_dev, DEV_NAME "%d: " ADDRESS_FORMAT + " UNKNOWN COMMAND 0x%02x\n", + ibc_smd_info->sel_drive, PCX, + cmd); + break; + } + return r; +} diff --git a/AltairZ80/wd179x.c b/AltairZ80/wd179x.c index e6f44372..a771f7a3 100644 --- a/AltairZ80/wd179x.c +++ b/AltairZ80/wd179x.c @@ -133,6 +133,9 @@ typedef struct { uint8 fdc_sec_len; /* N Sector Length */ int8 step_dir; uint8 cmdtype; /* Type of current/former command */ + uint16 external_fifo_len; + uint8 *external_fifo; + uint16 fdc_fifo_index; WD179X_DRIVE_INFO drive[WD179X_MAX_DRIVES]; } WD179X_INFO; @@ -199,7 +202,6 @@ static uint8 Do1793Command(uint8 cCommand); static t_stat wd179x_trackWrite(WD179X_DRIVE_INFO* pDrive, uint8 Cyl, uint8 Head, uint8 fillbyte, uint32* flags); - WD179X_INFO wd179x_info_data = { { 0x0, 0, 0x30, 4 }, 1793, 0, 0 }; WD179X_INFO *wd179x_info = &wd179x_info_data; WD179X_INFO_PUB *wd179x_infop = (WD179X_INFO_PUB *)&wd179x_info_data; @@ -336,6 +338,18 @@ static t_stat wd179x_reset(DEVICE *dptr) return SCPE_OK; } +void wd179x_connect_external_fifo(uint16 fifo_len, uint8* storage) +{ + wd179x_info->external_fifo_len = fifo_len; + wd179x_info->external_fifo = storage; + wd179x_info->fdc_fifo_index = 0; +} + +void wd179x_reset_external_fifo(void) +{ + wd179x_info->fdc_fifo_index = 0; +} + void wd179x_external_restore(void) { WD179X_DRIVE_INFO *pDrive; @@ -613,12 +627,13 @@ uint8 WD179X_Read(const uint32 Addr) cData = 0xFF; /* Return High-Z data */ if (wd179x_info->fdc_read == TRUE) { if (wd179x_info->fdc_dataindex < wd179x_info->fdc_datacount) { + wd179x_info->fdc_status &= ~(WD179X_STAT_BUSY); /* Clear BUSY */ cData = sdata.raw[wd179x_info->fdc_dataindex]; if (wd179x_info->fdc_read_addr == TRUE) { sim_debug(STATUS_MSG, &wd179x_dev, "WD179X[%d]: " ADDRESS_FORMAT - " READ_ADDR[%d] = 0x%02x\n", + " READ_ADDR[%d/%d] = 0x%02x\n", wd179x_info->sel_drive, PCX, - wd179x_info->fdc_dataindex, cData); + wd179x_info->fdc_dataindex, wd179x_info->fdc_datacount, cData); } wd179x_info->fdc_dataindex++; @@ -877,6 +892,7 @@ static uint8 Do1793Command(uint8 cCommand) WD179X_DRIVE_INFO *pDrive; uint32 flags = 0; uint32 readlen; + uint32 writelen; if (wd179x_info->sel_drive >= WD179X_MAX_DRIVES) { return 0xFF; @@ -1073,6 +1089,37 @@ static uint8 Do1793Command(uint8 cCommand) wd179x_info->fdc_read_addr = FALSE; sdata.raw[wd179x_info->fdc_dataindex] = wd179x_info->fdc_data; + + if (wd179x_info->external_fifo_len) { + /* For external FIFO, write the sector immediately, as the sofware pre-fills a FIFO, which is then read out into the FDC using DRQ */ + wd179x_info->fdc_status &= ~(WD179X_STAT_DRQ | WD179X_STAT_BUSY); /* Clear DRQ, BUSY */ + wd179x_info->drq = 0; + wd179x_info->intrq = 1; + if (wd179x_info->intenable) { + vectorInterrupt |= (1 << wd179x_info->intvector); + dataBus[wd179x_info->intvector] = wd179x_info->intvector * 2; + } + + sim_debug(WR_DATA_MSG, &wd179x_dev, "WD179X[%d]: " ADDRESS_FORMAT + " Writing sector, T:%2d/S:%d/N:%2d, Len=%d\n", wd179x_info->sel_drive, PCX, pDrive->track, wd179x_info-> + fdc_head, wd179x_info->fdc_sector, 128 << wd179x_info->fdc_sec_len); + + /* Copy the data from the external FIFO */ + memcpy(sdata.raw, &wd179x_info->external_fifo[wd179x_info->fdc_fifo_index], 128 << wd179x_info->fdc_sec_len); + wd179x_info->fdc_fifo_index += 128 << wd179x_info->fdc_sec_len; + wd179x_info->fdc_fifo_index &= (wd179x_info->external_fifo_len - 1); + + wd179x_sectWrite(pDrive, + pDrive->track, + wd179x_info->fdc_head, + wd179x_info->fdc_sector, + sdata.raw, + 128 << wd179x_info->fdc_sec_len, + &flags, + &writelen); + + wd179x_info->fdc_write = FALSE; + } break; /* Type III Commands */ case WD179X_READ_ADDR: @@ -1235,6 +1282,14 @@ static uint8 Do1793Command(uint8 cCommand) case WD179X_READ_ADDR: case WD179X_READ_TRACK: case WD179X_WRITE_TRACK: + wd179x_info->fdc_status &= ~(WD179X_STAT_BUSY); /* Clear BUSY */ + if (wd179x_info->intenable) { + wd179x_info->intrq = 1; + vectorInterrupt |= (1 << wd179x_info->intvector); + dataBus[wd179x_info->intvector] = wd179x_info->intvector * 2; + } + wd179x_info->drq = 1; + break; /* Type IV Commands */ case WD179X_FORCE_INTR: default: @@ -1321,6 +1376,12 @@ done: wd179x_info->fdc_dataindex = 0; wd179x_info->fdc_read = TRUE; wd179x_info->fdc_read_addr = FALSE; + if (wd179x_info->external_fifo_len) { + /* Save the FDC data in the external FIFO */ + memcpy(&wd179x_info->external_fifo[wd179x_info->fdc_fifo_index], sdata.raw, 128 << wd179x_info->fdc_sec_len); + wd179x_info->fdc_fifo_index += 128 << wd179x_info->fdc_sec_len; + wd179x_info->fdc_fifo_index &= (wd179x_info->external_fifo_len - 1); + } } else { wd179x_info->fdc_status = 0; /* Clear DRQ, BUSY */ wd179x_info->fdc_status |= WD179X_STAT_NOT_FOUND; diff --git a/makefile b/makefile index f474487f..afba30eb 100644 --- a/makefile +++ b/makefile @@ -1896,6 +1896,7 @@ ALTAIRZ80 = ${ALTAIRZ80D}/altairz80_cpu.c ${ALTAIRZ80D}/altairz80_cpu_nommu.c \ ${ALTAIRZ80D}/flashwriter2.c ${ALTAIRZ80D}/i86_decode.c \ ${ALTAIRZ80D}/i86_ops.c ${ALTAIRZ80D}/i86_prim_ops.c \ ${ALTAIRZ80D}/i8272.c ${ALTAIRZ80D}/insnsd.c ${ALTAIRZ80D}/altairz80_mhdsk.c \ + ${ALTAIRZ80D}/ibc.c ${ALTAIRZ80D}/ibc_mcc_hdc.c ${ALTAIRZ80D}/ibc_smd_hdc.c \ ${ALTAIRZ80D}/mfdc.c ${ALTAIRZ80D}/n8vem.c ${ALTAIRZ80D}/vfdhd.c \ ${ALTAIRZ80D}/s100_disk1a.c ${ALTAIRZ80D}/s100_disk2.c ${ALTAIRZ80D}/s100_disk3.c \ ${ALTAIRZ80D}/s100_fif.c ${ALTAIRZ80D}/s100_mdriveh.c \