diff --git a/VAX/vax_watch.c b/VAX/vax_watch.c index 28051db3..7b92cb8c 100644 --- a/VAX/vax_watch.c +++ b/VAX/vax_watch.c @@ -36,24 +36,70 @@ /* control/status registers */ -#define WTC_CSRA_RS 0x0F +#define WTC_CSRA_RS 0x0F /* Rate Select Bits (Not Used by VMS) */ #define WTC_CSRA_V_DV 4 #define WTC_CSRA_M_DV 0x7 #define WTC_CSRA_DV (WTC_CSRA_M_DV << WTC_CSRA_V_DV) -#define WTC_CSRA_UIP 0x80 /* update in progess */ +#define WTC_CSRA_UIP 0x80 /* update in progess (BUSY) */ #define WTC_CSRA_WR (WTC_CSRA_RS | WTC_CSRA_DV) +char *wtc_dv_modes[] = {"4.194304MHz", "1.048576MHz", "32.768KHz", "Any", "Any", "Test-Only", "Test-Only", "Test-Only"}; +BITFIELD wtc_csra_bits[] = { + BITNCF(4), /* Rate Select - unused MBZ for VMS */ + BITFNAM(DV,3,wtc_dv_modes), /* Divider Select */ + BIT(UIP), /* Update In Progress */ + ENDBITS +}; #define WTC_CSRB_DSE 0x01 /* daylight saving en */ -#define WTC_CSRB_2412 0x02 /* 24/12hr select */ -#define WTC_CSRB_DM 0x04 /* data mode */ +#define WTC_CSRB_2412 0x02 /* 24/12hr select (1 -> 24 hr) */ +#define WTC_CSRB_DM 0x04 /* data mode (1 -> binary, 0 -> BCD) */ #define WTC_CSRB_SET 0x80 /* set time */ +#define WTC_CSRB_PIE 0x40 /* periodic interrupt enable (Not Used by VMS) */ +#define WTC_CSRB_AIE 0x20 /* alarm interrupt enable (Not Used by VMS) */ +#define WTC_CSRB_UIE 0x10 /* update ended interrupt enable (Not Used by VMS) */ +#define WTC_CSRB_SQWE 0x08 /* square wave enable (Not Used by VMS) */ #define WTC_CSRB_WR (WTC_CSRB_DSE | WTC_CSRB_2412 | WTC_CSRB_DM | WTC_CSRB_SET) +char *wtc_dse_modes[] = {"Disabled", "Enabled"}; +char *wtc_hr_modes[] = {"12Hr", "24Hr"}; +char *wtc_data_modes[] = {"BCD", "Binary"}; +BITFIELD wtc_csrb_bits[] = { + BITFNAM(DST,1,wtc_dse_modes), /* Daylight Savings Time Enable */ + BITFNAM(24HR,1,wtc_hr_modes), /* 24/12 Hour Mode */ + BITFNAM(DM,1,wtc_data_modes), /* Data Mode */ + BITNCF(4), /* Unused SQWE, UIE, AIE, PIE */ + BIT(SET), /* Set In Progress */ + ENDBITS +}; +BITFIELD wtc_csrc_bits[] = { + BITF(VALUE,8), /* Should be unused */ + ENDBITS +}; #define WTC_CSRD_VRT 0x80 /* valid time */ #define WTC_CSRD_RD (WTC_CSRD_VRT) +#define WTC_CSRD_WR (WTC_CSRD_VRT) +BITFIELD wtc_csrd_bits[] = { + BITNCF(7), + BIT(VALID), /* Valid RAM and Time (VRT) */ + ENDBITS +}; + +BITFIELD wtc_value_bits[] = { + BITFFMT(VALUE,8,%d), /* Decimal Value */ + ENDBITS +}; +BITFIELD* wtc_bitdefs[] = {wtc_value_bits, wtc_value_bits, wtc_value_bits, wtc_value_bits, + wtc_value_bits, wtc_value_bits, wtc_value_bits, wtc_value_bits, + wtc_value_bits, wtc_value_bits, wtc_csra_bits, wtc_csrb_bits, + wtc_csrc_bits, wtc_csrd_bits, wtc_value_bits, wtc_value_bits}; #define WTC_MODE_STD 0 #define WTC_MODE_VMS 1 +char *wtc_modes[] = {"Std", "VMS"}; +BITFIELD wtc_mode_bits[] = { + BITFNAM(MODE,1,wtc_modes), /* Watch Date/Time mode */ + ENDBITS +}; int32 wtc_csra = 0; int32 wtc_csrb = 0; @@ -72,11 +118,11 @@ void wtc_set_invalid (void); UNIT wtc_unit = { UDATA (NULL, 0, 0) }; REG wtc_reg[] = { - { HRDATA (CSRA, wtc_csra, 8) }, - { HRDATA (CSRB, wtc_csrb, 8) }, - { HRDATA (CSRC, wtc_csrc, 8) }, - { HRDATA (CSRD, wtc_csrd, 8) }, - { HRDATA (MODE, wtc_mode, 8) }, + { HRDATADF (CSRA, wtc_csra, 8, "CSRA", wtc_csra_bits) }, + { HRDATADF (CSRB, wtc_csrb, 8, "CSRB", wtc_csrb_bits) }, + { HRDATADF (CSRC, wtc_csrc, 8, "CSRC", wtc_csrc_bits) }, + { HRDATADF (CSRD, wtc_csrd, 8, "CSRD", wtc_csrd_bits) }, + { HRDATADF (MODE, wtc_mode, 8, "Watch Mode", wtc_mode_bits) }, { NULL } }; @@ -85,15 +131,32 @@ MTAB wtc_mod[] = { { 0 } }; +/* debugging bitmaps */ +#define DBG_REG 0x0001 /* trace read/write registers */ + +DEBTAB wtc_debug[] = { + {"REG", DBG_REG}, + {0} +}; + DEVICE wtc_dev = { "WTC", &wtc_unit, wtc_reg, wtc_mod, 1, 16, 16, 1, 16, 8, NULL, NULL, &wtc_reset, NULL, NULL, NULL, - NULL, 0, 0, NULL, NULL, NULL, &wtc_help, NULL, NULL, + NULL, DEV_DEBUG, 0, wtc_debug, NULL, NULL, &wtc_help, NULL, NULL, &wtc_description }; +/* Register names for Debug tracing */ +static char *wtc_regs[] = + {"SEC ", "SECA", "MIN ", "MINA", + "HR ", "HRA ", "DOW ", "DOM ", + "MON ", "YEAR", "CSRA", "CSRB", + "CSRC", "CSRD" }; + + + int32 wtc_rd (int32 pa) { int32 rg = (pa >> 1) & 0xF; @@ -160,26 +223,46 @@ switch(rg) { break; } -return ((rg & 1) ? (val << 16) : val); /* word aligned? */ +sim_debug(DBG_REG, &wtc_dev, "wtc_rd(pa=0x%08X [%s], data=0x%X) ", pa, wtc_regs[rg], val); +sim_debug_bits(DBG_REG, &wtc_dev, wtc_bitdefs[rg], (uint32)val, (uint32)val, TRUE); + +if (rg & 1) + val = (val << 16); /* word aligned? */ + +return val; } void wtc_wr (int32 pa, int32 val, int32 lnt) { int32 rg = (pa >> 1) & 0xF; +int32 new_val = val; + val = val & 0xFF; switch(rg) { case 10: /* CSR A */ val = val & WTC_CSRA_WR; - wtc_csra = (wtc_csra & ~WTC_CSRA_WR) | val; + new_val = wtc_csra = (wtc_csra & ~WTC_CSRA_WR) | val; break; case 11: /* CSR B */ val = val & WTC_CSRB_WR; - wtc_csrb = (wtc_csrb & ~WTC_CSRB_WR) | val; + new_val = wtc_csrb = (wtc_csrb & ~WTC_CSRB_WR) | val; + break; + + case 12: /* CSR C */ + break; + + case 13: /* CSR D */ + val = val & WTC_CSRD_WR; + new_val = wtc_csrd = (wtc_csrd & ~WTC_CSRD_WR) | val; break; } + +sim_debug(DBG_REG, &wtc_dev, "wtc_wr(pa=0x%08X [%s], data=0x%X) ", pa, wtc_regs[rg], val); +sim_debug_bits(DBG_REG, &wtc_dev, wtc_bitdefs[rg], (uint32)new_val, (uint32)new_val, TRUE); + } t_stat wtc_reset (DEVICE *dptr)