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3b2: Refactoring in preparation for Rev 3

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Refactor in preparation for the addition of a Rev 3 simulator for the
3B2/1000 system.

This change also includes a full cleanup of the rat's-nest of includes
and externs that plagued the 3B2 simulator and made it difficult to
understand and maintain. Headers are now required in the following
order:

  compilation unit -> "3b2_defs.h" -> {... dependencies ...}

Finally, HELP has been added to the CPU device.
This commit is contained in:
Seth Morabito 2020-03-26 13:30:08 -07:00
parent 083080e71d
commit 1a3e5af755
34 changed files with 8865 additions and 664 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

34
3B2/3b2_1000_defs.h Normal file
View file

@ -0,0 +1,34 @@
/* 3b2_1000_defs.h: AT&T 3B2 Model 400 Simulator Definitions
Copyright (c) 2020, Seth J. Morabito
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use, copy,
modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
Except as contained in this notice, the name of the author shall
not be used in advertising or otherwise to promote the sale, use or
other dealings in this Software without prior written authorization
from the author.
*/
#ifndef _3B2_1000_DEFS_H_
#define _3B2_1000_DEFS_H_
#endif

137
3B2/3b2_cpu.c → 3B2/3b2_400_cpu.c
View file

@ -1,4 +1,4 @@
/* 3b2_cpu.c: AT&T 3B2 Model 400 CPU (WE32100) Implementation
/* 3b2_400_cpu.c: AT&T 3B2 Model 400 CPU (WE32100) Implementation
Copyright (c) 2017, Seth J. Morabito
@ -28,8 +28,10 @@
from the author.
*/
#include "3b2_cpu.h"
#include "3b2_defs.h"
#include "3b2_400_cpu.h"
#include "rom_400_bin.h"
#include <sim_defs.h>
#define MAX_SUB_RETURN_SKIP 9
@ -97,8 +99,6 @@ volatile size_t cpu_exception_stack_depth = 0;
volatile int32 stop_reason;
volatile uint32 abort_reason;
extern uint16 csr_data;
/* Register data */
uint32 R[16];
@ -295,7 +295,7 @@ DEVICE cpu_dev = {
cpu_deb_tab, /* Debug flag names */
&cpu_set_size, /* Memory size change */
NULL, /* Logical names */
NULL, /* Help routine */
&cpu_help, /* Help routine */
NULL, /* Attach Help Routine */
NULL, /* Help Context */
&cpu_description /* Device Description */
@ -874,43 +874,6 @@ t_bool cpu_is_pc_a_subroutine_call (t_addr **ret_addrs)
}
}
t_stat cpu_set_hist(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
{
uint32 i, size;
t_stat result;
if (cptr == NULL) {
/* Disable the feature */
if (INST != NULL) {
for (i = 0; i < cpu_hist_size; i++) {
INST[i].valid = FALSE;
}
}
cpu_hist_size = 0;
cpu_hist_p = 0;
return SCPE_OK;
}
size = (uint32) get_uint(cptr, 10, MAX_HIST_SIZE, &result);
if ((result != SCPE_OK) || (size < MIN_HIST_SIZE)) {
return SCPE_ARG;
}
cpu_hist_p = 0;
if (size > 0) {
if (INST != NULL) {
free(INST);
}
INST = (instr *)calloc(size, sizeof(instr));
if (INST == NULL) {
return SCPE_MEM;
}
memset(INST, 0, sizeof(instr) * size);
cpu_hist_size = size;
}
return SCPE_OK;
}
t_stat fprint_sym_m(FILE *of, t_addr addr, t_value *val)
{
uint8 desc, mode, reg, etype;
@ -1151,6 +1114,55 @@ t_stat cpu_show_virt(FILE *of, UNIT *uptr, int32 val, CONST void *desc)
return SCPE_ARG;
}
t_stat cpu_set_hist(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
{
uint32 i, size;
t_stat result;
/* Clear the history buffer if no argument */
if (cptr == NULL) {
for (i = 0; i < cpu_hist_size; i++) {
INST[i].valid = FALSE;
}
return SCPE_OK;
}
/* Otherwise, get the new length */
size = (uint32) get_uint(cptr, 10, MAX_HIST_SIZE, &result);
/* If no length was provided, give up */
if (result != SCPE_OK) {
return SCPE_ARG;
}
/* Legnth 0 is a special flag that means disable the feature. */
if (size == 0) {
if (INST != NULL) {
for (i = 0; i < cpu_hist_size; i++) {
INST[i].valid = FALSE;
}
}
cpu_hist_size = 0;
cpu_hist_p = 0;
return SCPE_OK;
}
/* Reinitialize the new history ring bufer */
cpu_hist_p = 0;
if (size > 0) {
if (INST != NULL) {
free(INST);
}
INST = (instr *)calloc(size, sizeof(instr));
if (INST == NULL) {
return SCPE_MEM;
}
memset(INST, 0, sizeof(instr) * size);
cpu_hist_size = size;
}
return SCPE_OK;
}
t_stat cpu_show_hist(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
{
@ -3809,5 +3821,44 @@ void cpu_abort(uint8 et, uint8 isc)
CONST char *cpu_description(DEVICE *dptr)
{
return "WE32100";
return "3B2/400 CPU (WE 32100)";
}
t_stat cpu_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
{
fprintf(st, "3B2/400 CPU Help\n\n");
fprintf(st, "The 3B2/400 CPU simulates a WE 32100 at 10 MHz.\n\n");
fprintf(st, "CPU options include the size of main memory.\n\n");
if (dptr->modifiers) {
MTAB *mptr;
for (mptr = dptr->modifiers; mptr->mask != 0; mptr++) {
if (mptr->valid == &cpu_set_size) {
fprintf(st, " sim> SET CPU %4s set memory size = %sB\n",
mptr->mstring, mptr->mstring);
}
}
fprintf(st, "\n");
}
fprintf(st, "The CPU also implements a command to display a virtual to physical address\n");
fprintf(st, "translation:\n\n");
fprintf(st, " sim> SHOW CPU VIRTUAL=n show translation for address n\n\n");
fprintf(st, "The CPU attempts to detect when the simulator is idle. When idle, the\n");
fprintf(st, "simulator does not use any resources on the host system. Idle detetion is\n");
fprintf(st, "controlled by the SET CPU IDLE and SET CPU NOIDLE commands:\n\n");
fprintf(st, " sim> SET CPU IDLE enable idle detection\n");
fprintf(st, " sim> SET CPU NOIDLE disable idle detection\n\n");
fprintf(st, "Idle detection is disabled by default.\n\n");
fprintf(st, "The CPU can maintain a history of the most recently executed instructions.\n");
fprintf(st, "This is controlled by the SET CPU HISTORY and SHOW CPU HISTORY commands:\n\n");
fprintf(st, " sim> SET CPU HISTORY clear history buffer\n");
fprintf(st, " sim> SET CPU HISTORY=0 disable history\n");
fprintf(st, " sim> SET CPU HISTORY=n enable history, length = n\n");
fprintf(st, " sim> SHOW CPU HISTORY print CPU history\n");
fprintf(st, " sim> SHOW CPU HISTORY=n print last n entries of CPU history\n\n");
fprintf(st, "Additional docuentation for the 3B2/400 Simulator is available on the web:\n\n");
fprintf(st, " https://loomcom.com/3b2/emulator.html\n\n");
return SCPE_OK;
}

195
3B2/3b2_cpu.h → 3B2/3b2_400_cpu.h
View file

@ -1,4 +1,4 @@
/* 3b2_cpu.h: AT&T 3B2 Model 400 CPU (WE32100) Header
/* 3b2_400_cpu.h: AT&T 3B2 Model 400 CPU (WE32100) Header
Copyright (c) 2017, Seth J. Morabito
@ -31,8 +31,7 @@
#ifndef _3B2_CPU_H_
#define _3B2_CPU_H_
#include "3b2_defs.h"
#include "3b2_io.h"
#include "sim_defs.h"
/* Execution Modes */
#define EX_LVL_KERN 0
@ -40,6 +39,139 @@
#define EX_LVL_SUPR 2
#define EX_LVL_USER 3
#define MAX_HIST_SIZE 10000000
#define MIN_HIST_SIZE 64
#define MEM_SIZE (cpu_unit.capac)
#define UNIT_V_MSIZE (UNIT_V_UF)
#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
#define WD_MSB 0x80000000
#define HW_MSB 0x8000
#define BT_MSB 0x80
#define WORD_MASK 0xffffffff
#define HALF_MASK 0xffffu
#define BYTE_MASK 0xff
/* Exception Types */
#define RESET_EXCEPTION 0
#define PROCESS_EXCEPTION 1
#define STACK_EXCEPTION 2
#define NORMAL_EXCEPTION 3
/* Reset Exceptions */
#define OLD_PCB_FAULT 0
#define SYSTEM_DATA_FAULT 1
#define INTERRUPT_STACK_FAULT 2
#define EXTERNAL_RESET 3
#define NEW_PCB_FAULT 4
#define GATE_VECTOR_FAULT 6
/* Processor Exceptions */
#define GATE_PCB_FAULT 1
/* Stack Exceptions */
#define STACK_BOUND 0
#define STACK_FAULT 1
#define INTERRUPT_ID_FETCH 3
/* Normal Exceptions */
#define INTEGER_ZERO_DIVIDE 0
#define TRACE_TRAP 1
#define ILLEGAL_OPCODE 2
#define RESERVED_OPCODE 3
#define INVALID_DESCRIPTOR 4
#define EXTERNAL_MEMORY_FAULT 5
#define N_GATE_VECTOR 6
#define ILLEGAL_LEVEL_CHANGE 7
#define RESERVED_DATATYPE 8
#define INTEGER_OVERFLOW 9
#define PRIVILEGED_OPCODE 10
#define BREAKPOINT_TRAP 14
#define PRIVILEGED_REGISTER 15
#define PSW_ET 0
#define PSW_TM 2u
#define PSW_ISC 3u
#define PSW_I 7
#define PSW_R 8
#define PSW_PM 9
#define PSW_CM 11
#define PSW_IPL 13
#define PSW_TE 17
#define PSW_C 18
#define PSW_V 19
#define PSW_Z 20
#define PSW_N 21
#define PSW_OE 22
#define PSW_CD 23
#define PSW_QIE 24
#define PSW_CFD 25
#define PSW_ET_MASK 3u
#define PSW_TM_MASK (1u << PSW_TM)
#define PSW_ISC_MASK (15u << PSW_ISC)
#define PSW_I_MASK (1u << PSW_I)
#define PSW_R_MASK (1u << PSW_R)
#define PSW_PM_MASK (3u << PSW_PM)
#define PSW_CM_MASK (3u << PSW_CM)
#define PSW_IPL_MASK (15u << PSW_IPL)
#define PSW_TE_MASK (1u << PSW_TE)
#define PSW_C_MASK (1u << PSW_C)
#define PSW_V_MASK (1u << PSW_V)
#define PSW_N_MASK (1u << PSW_N)
#define PSW_Z_MASK (1u << PSW_Z)
#define PSW_OE_MASK (1u << PSW_OE)
#define PSW_CD_MASK (1u << PSW_CD)
#define PSW_QIE_MASK (1u << PSW_QIE)
#define PSW_CFD_MASK (1u << PSW_CFD)
#define PSW_CUR_IPL (((R[NUM_PSW] & PSW_IPL_MASK) >> PSW_IPL) & 0xf)
/* Exceptional conditions handled within the instruction loop */
#define ABORT_EXC 1 /* CPU exception */
/* Contexts for aborts */
#define C_NONE 0 /* No context. Normal handling. */
#define C_NORMAL_GATE_VECTOR 1
#define C_PROCESS_GATE_PCB 2
#define C_PROCESS_OLD_PCB 3
#define C_PROCESS_NEW_PCB 4
#define C_RESET_GATE_VECTOR 5
#define C_RESET_INT_STACK 6
#define C_RESET_NEW_PCB 7
#define C_RESET_SYSTEM_DATA 8
#define C_STACK_FAULT 9
/* Register numbers */
#define NUM_FP 9
#define NUM_AP 10
#define NUM_PSW 11
#define NUM_SP 12
#define NUM_PCBP 13
#define NUM_ISP 14
#define NUM_PC 15
/* System board interrupt priority levels */
#define CPU_PIR8_IPL 8
#define CPU_PIR9_IPL 9
#define CPU_ID_IF_IPL 11
#define CPU_IU_DMA_IPL 13
#define CPU_TMR_IPL 15
#define CPU_CM (cpu_km ? L_KERNEL : ((R[NUM_PSW] >> PSW_CM) & 3))
/* Data types operated on by instructions. NB: These integer values
have meaning when decoding instructions, so this is not just an
enum. Please don't change them. */
#define UW 0 /* Unsigned Word */
#define UH 2 /* Unsigned Halfword */
#define BT 3 /* Unsigned Byte */
#define WD 4 /* Signed Word */
#define HW 6 /* Signed Halfword */
#define SB 7 /* Signed Byte */
#define NA -1
/* Processor Version Number */
#define WE32100_VER 0x1A
@ -112,7 +244,7 @@ typedef enum {
CALL = 0x2C,
BPT = 0x2E,
WAIT = 0x2F,
EMB = 0x30, // Multi-byte
EMB = 0x30, /* Multi-byte */
SPOP = 0x32,
SPOPWS = 0x33,
JSB = 0x34,
@ -137,14 +269,14 @@ typedef enum {
BLEH = 0x4E,
BLEB = 0x4F,
RGEQU = 0x50,
BGEUH = 0x52, // Also BCCH
BGEUB = 0x53, // Also BCCB
BGEUH = 0x52,
BGEUB = 0x53,
RGTRU = 0x54,
BGUH = 0x56,
BGUB = 0x57,
BLSSU = 0x58, // Also BCS
BLUH = 0x5A, // Also BCSH
BLUB = 0x5B, // Also BCSB
BLSSU = 0x58,
BLUH = 0x5A,
BLUB = 0x5B,
RLEQU = 0x5C,
BLEUH = 0x5E,
BLEUB = 0x5F,
@ -152,14 +284,14 @@ typedef enum {
BVCH = 0x62,
BVCB = 0x63,
RNEQU = 0x64,
BNEH_D = 0x66, // Duplicate of 0x76
BNEB_D = 0x67, // Duplicate of 0x77
BNEH_D = 0x66,
BNEB_D = 0x67,
RVS = 0x68,
BVSH = 0x6A,
BVSB = 0x6B,
REQLU = 0x6C,
BEH_D = 0x6E, // Duplicate of 0x7E
BEB_D = 0x6F, // Duplicate of 0x7F
BEH_D = 0x6E,
BEB_D = 0x6F,
NOP = 0x70,
NOP3 = 0x72,
NOP2 = 0x73,
@ -176,9 +308,9 @@ typedef enum {
CLRW = 0x80,
CLRH = 0x82,
CLRB = 0x83,
MOVW = 0x84, /* done */
MOVH = 0x86, /* done */
MOVB = 0x87, /* done */
MOVW = 0x84,
MOVH = 0x86,
MOVB = 0x87,
MCOMW = 0x88,
MCOMH = 0x8A,
MCOMB = 0x8B,
@ -269,33 +401,6 @@ typedef enum {
RETPS = 0x30c8
} opcode;
typedef enum {
DECODE_SUCCESS,
DECODE_ERROR
} decode_result;
/* Addressing Mode enum */
typedef enum {
ABS, // Absolute
ABS_DEF, // Absolute Deferred
BYTE_DISP, // Byte Displacement
BYTE_DISP_DEF, // Byte Displacement Deferred
HFWD_DISP, // Halfword Displacement
HFWD_DISP_DEF, // Halfword Displacement Deferred
WORD_DISP, // Word Displacement
WORD_DISP_DEF, // Word Displacement Deferred
AP_SHORT_OFF, // AP Short Offset
FP_SHORT_OFF, // FP Short Offset
BYTE_IMM, // Byte Immediate
HFWD_IMM, // Halfword Immediate
WORD_IMM, // Word Immediate
POS_LIT, // Positive Literal
NEG_LIT, // Negative Literal
REGISTER, // Register
REGISTER_DEF, // Register Deferred
EXP // Expanded-operand type
} addr_mode;
/*
* Each instruction expects operands of a certain type.
*
@ -401,6 +506,7 @@ t_stat cpu_show_cio(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat cpu_set_halt(UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat cpu_clear_halt(UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat cpu_boot(int32 unit_num, DEVICE *dptr);
t_stat cpu_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
CONST char *cpu_description(DEVICE *dptr);
t_bool cpu_is_pc_a_subroutine_call (t_addr **ret_addrs);
@ -414,6 +520,9 @@ instr *cpu_next_instruction(void);
uint8 decode_instruction(instr *instr);
void cpu_on_interrupt(uint16 vec);
void cpu_abort(uint8 et, uint8 isc);
void cpu_set_irq(uint8 ipl, uint8 id, uint16 csr_flags);
void cpu_clear_irq(uint8 ipl, uint16 csr_flags);
/* Helper macros */

111
3B2/3b2_400_defs.h Normal file
View file

@ -0,0 +1,111 @@
/* 3b2_400_defs.h: AT&T 3B2 Model 400 Simulator Definitions
Copyright (c) 2017, Seth J. Morabito
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use, copy,
modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
Except as contained in this notice, the name of the author shall
not be used in advertising or otherwise to promote the sale, use or
other dealings in this Software without prior written authorization
from the author.
*/
#ifndef _3B2_400_DEFS_H_
#define _3B2_400_DEFS_H_
#include "sim_defs.h"
#define MAXMEMSIZE (1 << 22) /* 4 MB */
#define TODBASE 0x41000
#define TODSIZE 0x40
#define TIMERBASE 0x42000
#define TIMERSIZE 0x20
#define NVRAMBASE 0x43000
#define NVRAMSIZE 0x1000
#define CSRBASE 0x44000
#define CSRSIZE 0x100
#define IFBASE 0x4d000
#define IFSIZE 0x10
#define IDBASE 0x4a000
#define IDSIZE 0x2
#define IF_STATUS_REG 0
#define IF_CMD_REG 0
#define IF_TRACK_REG 1
#define IF_SECTOR_REG 2
#define IF_DATA_REG 3
#define ID_DATA_REG 0
#define ID_CMD_STAT_REG 1
/* CSR Flags */
#define CSRTIMO 0x8000 /* Bus Timeout Error */
#define CSRPARE 0x4000 /* Memory Parity Error */
#define CSRRRST 0x2000 /* System Reset Request */
#define CSRALGN 0x1000 /* Memory Alignment Fault */
#define CSRLED 0x0800 /* Failure LED */
#define CSRFLOP 0x0400 /* Floppy Motor On */
#define CSRRES 0x0200 /* Reserved */
#define CSRITIM 0x0100 /* Inhibit Timers */
#define CSRIFLT 0x0080 /* Inhibit Faults */
#define CSRCLK 0x0040 /* Clock Interrupt */
#define CSRPIR8 0x0020 /* Programmed Interrupt 8 */
#define CSRPIR9 0x0010 /* Programmed Interrupt 9 */
#define CSRUART 0x0008 /* UART Interrupt */
#define CSRDISK 0x0004 /* Floppy Interrupt */
#define CSRDMA 0x0002 /* DMA Interrupt */
#define CSRIOF 0x0001 /* I/O Board Fail */
#define MEMSIZE_REG 0x4C003
/* DMA Controller */
#define DMACBASE 0x48000
#define DMACSIZE 0x11
/* DMA integrated disk page buffer */
#define DMAIDBASE 0x45000
#define DMAIDSIZE 0x5
/* DMA integrated uart A page buffer */
#define DMAIUABASE 0x46000
#define DMAIUASIZE 0x5
/* DMA integrated uart B page buffer */
#define DMAIUBBASE 0x47000
#define DMAIUBSIZE 0x5
/* DMA integrated floppy page buffer */
#define DMAIFBASE 0x4E000
#define DMAIFSIZE 0x5
#define DMA_ID_CHAN 0
#define DMA_IF_CHAN 1
#define DMA_IUA_CHAN 2
#define DMA_IUB_CHAN 3
#define DMA_ID 0x45
#define DMA_IUA 0x46
#define DMA_IUB 0x47
#define DMA_C 0x48
#define DMA_IF 0x4E
#endif /* _3B2_400_DEFS_H_ */

7
3B2/3b2_mau.c → 3B2/3b2_400_mau.c
View file

@ -1,4 +1,4 @@
/* 3b2_mmu.c: AT&T 3B2 Model 400 Math Acceleration Unit (WE32106 MAU)
/* 3b2_400_mau.c: AT&T 3B2 Model 400 Math Acceleration Unit (WE32106 MAU)
Implementation
Copyright (c) 2019, Seth J. Morabito
@ -83,7 +83,8 @@
#include <math.h>
#include "3b2_mau.h"
#include "3b2_defs.h"
#include "3b2_400_mau.h"
#define MAU_ID 0 /* Coprocessor ID of MAU */
@ -199,8 +200,6 @@ static void mau_remainder();
static void mau_execute();
extern volatile int32 stop_reason;
UNIT mau_unit = { UDATA(NULL, 0, 0) };
MAU_STATE mau_state;

13
3B2/3b2_mau.h → 3B2/3b2_400_mau.h
View file

@ -1,4 +1,4 @@
/* 3b2_mmu.c: AT&T 3B2 Model 400 Math Acceleration Unit (WE32106 MAU)
/* 3b2_400_mau.c: AT&T 3B2 Model 400 Math Acceleration Unit (WE32106 MAU)
Header
Copyright (c) 2019, Seth J. Morabito
@ -139,10 +139,10 @@
*/
#ifndef _3B2_MAU_H
#define _3B2_MAU_H
#ifndef _3B2_400_MAU_H_
#define _3B2_400_MAU_H_
#include "3b2_defs.h"
#include "sim_defs.h"
#define SRC_LEN_INVALID 0
#define SRC_LEN_SINGLE 1
@ -373,12 +373,11 @@ typedef struct {
XFP f3;
} MAU_STATE;
extern DEVICE mau_dev;
t_stat mau_reset(DEVICE *dptr);
t_stat mau_attach(UNIT *uptr, CONST char *cptr);
t_stat mau_detach(UNIT *uptr);
t_stat mau_broadcast(uint32 cmd, uint32 src, uint32 dst);
CONST char *mau_description(DEVICE *dptr);
t_stat mau_broadcast(uint32 cmd, uint32 src, uint32 dst);
#endif
#endif /* _3B2_400_MAU_H_ */

5
3B2/3b2_mmu.c → 3B2/3b2_400_mmu.c
View file

@ -1,4 +1,4 @@
/* 3b2_mmu.c: AT&T 3B2 Model 400 MMU (WE32101) Implementation
/* 3b2_400_mmu.c: AT&T 3B2 Model 400 MMU (WE32101) Implementation
Copyright (c) 2017, Seth J. Morabito
@ -28,7 +28,8 @@
from the author.
*/
#include "3b2_mmu.h"
#include "3b2_defs.h"
#include "3b2_400_mmu.h"
UNIT mmu_unit = { UDATA(NULL, 0, 0) };

46
3B2/3b2_mmu.h → 3B2/3b2_400_mmu.h
View file

@ -1,4 +1,4 @@
/* 3b2_mmu.c: AT&T 3B2 Model 400 MMU (WE32101) Header
/* 3b2_400_mmu.c: AT&T 3B2 Model 400 MMU (WE32101) Header
Copyright (c) 2017, Seth J. Morabito
@ -28,11 +28,11 @@
from the author.
*/
#ifndef _3B2_MMU_H
#define _3B2_MMU_H
#include "3b2_defs.h"
#ifndef _3B2_400_MMU_H_
#define _3B2_400_MMU_H_
#include "sim_defs.h"
#include "3b2_400_defs.h"
/************************************************************************
*
@ -203,6 +203,23 @@
#define MMU_F_ACC 0x0d
#define MMU_F_SEG_OFFSET 0x0e
/* Access Request types */
#define ACC_MT 0 /* Move Translated */
#define ACC_SPW 1 /* Support processor write */
#define ACC_SPF 3 /* Support processor fetch */
#define ACC_IR 7 /* Interlocked read */
#define ACC_AF 8 /* Address fetch */
#define ACC_OF 9 /* Operand fetch */
#define ACC_W 10 /* Write */
#define ACC_IFAD 12 /* Instruction fetch after discontinuity */
#define ACC_IF 13 /* Instruction fetch */
/* Memory access levels */
#define L_KERNEL 0
#define L_EXEC 1
#define L_SUPER 2
#define L_USER 3
/* Pluck out Virtual Address fields */
#define SID(va) (((va) >> 30) & 3)
#define SSL(va) (((va) >> 17) & 0x1fff)
@ -314,11 +331,6 @@ typedef struct _mmu_state {
} MMU_STATE;
extern MMU_STATE mmu_state;
extern volatile int32 stop_reason;
extern DEVICE mmu_dev;
t_stat mmu_init(DEVICE *dptr);
uint32 mmu_read(uint32 pa, size_t size);
void mmu_write(uint32 pa, uint32 val, size_t size);
@ -341,22 +353,22 @@ uint32 mmu_xlate_addr(uint32 va, uint8 r_acc);
t_stat mmu_decode_vaddr(uint32 vaddr, uint8 r_acc,
t_bool fc, uint32 *pa);
#define SHOULD_CACHE_PD(pd) \
#define SHOULD_CACHE_PD(pd) \
(fc && PD_PRESENT(pd))
#define SHOULD_CACHE_SD(sd) \
#define SHOULD_CACHE_SD(sd) \
(fc && SD_VALID(sd) && SD_PRESENT(sd))
#define SHOULD_UPDATE_SD_R_BIT(sd) \
(MMU_CONF_R && !((sd) & SD_R_MASK))
#define SHOULD_UPDATE_SD_M_BIT(sd) \
#define SHOULD_UPDATE_SD_M_BIT(sd) \
(MMU_CONF_M && r_acc == ACC_W && !((sd) & SD_M_MASK))
#define SHOULD_UPDATE_PD_R_BIT(pd) \
(!((pd) & PD_R_MASK))
#define SHOULD_UPDATE_PD_M_BIT(pd) \
#define SHOULD_UPDATE_PD_M_BIT(pd) \
(r_acc == ACC_W && !((pd) & PD_M_MASK))
/* Special functions for reading operands and examining memory
@ -378,4 +390,8 @@ t_bool addr_is_rom(uint32 pa);
t_bool addr_is_mem(uint32 pa);
t_bool addr_is_io(uint32 pa);
#endif
t_stat mmu_decode_va(uint32 va, uint8 r_acc, t_bool fc, uint32 *pa);
void mmu_enable();
void mmu_disable();
#endif /* _3B2_400_MMU_H_ */

14
3B2/3b2_sysdev.c → 3B2/3b2_400_stddev.c
View file

@ -1,4 +1,4 @@
/* 3b2_cpu.h: AT&T 3B2 Model 400 System Devices implementation
/* 3b2_400_stddev.h: AT&T 3B2 Model 400 System Devices implementation
Copyright (c) 2017, Seth J. Morabito
@ -40,8 +40,8 @@
#include <time.h>
#include "3b2_sysdev.h"
#include "3b2_iu.h"
#include "3b2_defs.h"
#include "3b2_400_stddev.h"
DEBTAB sys_deb_tab[] = {
{ "INIT", INIT_MSG, "Init" },
@ -57,8 +57,6 @@ struct timer_ctr TIMERS[3];
uint32 *NVRAM = NULL;
extern DEVICE cpu_dev;
int32 tmxr_poll = 16667;
/* CSR */
@ -447,12 +445,6 @@ DEVICE timer_dev = {
DEV_DEBUG, 0, sys_deb_tab
};
#define TIMER_STP_US 10 /* 10 us delay per timer step */
#define tmrnum u3
#define tmr up7
t_stat timer_reset(DEVICE *dptr) {
int32 i, t;

29
3B2/3b2_sysdev.h → 3B2/3b2_400_stddev.h
View file

@ -1,4 +1,4 @@
/* 3b2_cpu.h: AT&T 3B2 Model 400 System Devices (Header)
/* 3b2_400_stddev.h: AT&T 3B2 Model 400 System Devices (Header)
Copyright (c) 2017, Seth J. Morabito
@ -31,15 +31,26 @@
#ifndef _3B2_SYSDEV_H_
#define _3B2_SYSDEV_H_
#include "3b2_defs.h"
#include "3b2_sys.h"
#include "3b2_cpu.h"
#include "sim_defs.h"
extern DEVICE nvram_dev;
extern DEVICE timer_dev;
extern DEVICE csr_dev;
extern DEVICE tod_dev;
extern DEBTAB sys_deb_tab[];
/* Timer definitions */
#define TMR_CLK 0 /* The clock responsible for IPL 15 interrupts */
#define TPS_CLK 100 /* 100 ticks per second */
#define TIMER_STP_US 1
#define tmrnum u3
#define tmr up7
#define TIMER_REG_DIVA 0x03
#define TIMER_REG_DIVB 0x07
#define TIMER_REG_DIVC 0x0b
#define TIMER_REG_CTRL 0x0f
#define TIMER_CLR_LATCH 0x13
#define CLK_RW 0x30
#define CLK_LSB 0x10
#define CLK_MSB 0x20
#define CLK_LMB 0x30
struct timer_ctr {
uint16 divider;

16
3B2/3b2_sys.c → 3B2/3b2_400_sys.c
View file

@ -28,18 +28,8 @@
from the author.
*/
#include "3b2_sys.h"
#include "3b2_cpu.h"
#include "3b2_iu.h"
#include "3b2_if.h"
#include "3b2_id.h"
#include "3b2_mmu.h"
#include "3b2_ctc.h"
#include "3b2_ports.h"
#include "3b2_ni.h"
#include "3b2_mau.h"
#include "3b2_sysdev.h"
#include "3b2_defs.h"
#include "3b2_400_sys.h"
char sim_name[] = "AT&T 3B2 Model 400";
@ -49,8 +39,6 @@ REG *sim_PC = &cpu_reg[0];
there may be up to 3 operands, for a maximum of 20 bytes */
int32 sim_emax = 20;
extern instr *cpu_instr;
DEVICE *sim_devices[] = {
&cpu_dev,
&mmu_dev,

16
3B2/3b2_sys.h → 3B2/3b2_400_sys.h
View file

@ -1,4 +1,4 @@
/* 3b2_sys.h: AT&T 3B2 Model 400 system-specific logic headers
/* 3b2_400_sys.h: AT&T 3B2 Model 400 system-specific logic headers
Copyright (c) 2017, Seth J. Morabito
@ -28,16 +28,10 @@
from the author.
*/
#ifndef _3B2_SYS_H
#define _3B2_SYS_H
#ifndef _3B2_400_SYS_H_
#define _3B2_400_SYS_H_
#include "3b2_defs.h"
extern uint32 R[16];
extern char sim_name[];
extern REG *sim_PC;
extern int32 sim_emax;
extern DEVICE *sim_devices[];
#include "sim_defs.h"
void full_reset();
t_stat sim_load(FILE *fileref, CONST char *cptr, CONST char *fnam, int flag);
@ -45,4 +39,4 @@ t_stat parse_sym(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val,
int32 sw);
t_stat fprint_sym(FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw);
#endif
#endif /* _3B2_400_SYS_H_ */

4
3B2/3b2_ctc.c
View file

@ -28,11 +28,9 @@
from the author.
*/
#include "3b2_defs.h"
#include "3b2_ctc.h"
extern CIO_STATE cio[CIO_SLOTS];
extern UNIT cio_unit;
#define CTQRESIZE 20
#define CTQCESIZE 16

4
3B2/3b2_ctc.h
View file

@ -51,7 +51,7 @@
#ifndef _3B2_CTC_H_
#define _3B2_CTC_H_
#include "3b2_defs.h"
#include "sim_defs.h"
#include "3b2_io.h"
#define UNIT_V_WLK (DKUF_V_UF + 0) /* Write-locked tape */
@ -146,8 +146,6 @@ typedef struct {
uint32 bytnum; /* Byte number, for streaming mode */
} CTC_STATE;
extern DEVICE ctc_dev;
t_stat ctc_reset(DEVICE *dptr);
t_stat ctc_svc(UNIT *uptr);
t_stat ctc_attach(UNIT *uptr, CONST char *cptr);

475
3B2/3b2_defs.h
View file

@ -1,4 +1,4 @@
/* 3b2_defs.h: AT&T 3B2 Model 400 Simulator Definitions
/* 3b2_defs.h: AT&T 3B2 Shared Simulator Definitions
Copyright (c) 2017, Seth J. Morabito
@ -35,10 +35,35 @@
#include "sim_tmxr.h"
#include <setjmp.h>
#define FALSE 0
#define TRUE 1
#if defined(REV3)
#include "3b2_1000_defs.h"
#else
#include "3b2_400_defs.h"
#include "3b2_400_cpu.h"
#include "3b2_400_mau.h"
#include "3b2_400_mmu.h"
#include "3b2_400_stddev.h"
#include "3b2_400_sys.h"
#include "3b2_id.h"
#endif
#if defined (__GNUC__)
#include "3b2_io.h"
#include "3b2_dmac.h"
#include "3b2_if.h"
#include "3b2_iu.h"
#include "3b2_ports.h"
#include "3b2_ctc.h"
#include "3b2_ni.h"
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
#if defined(__GNUC__)
#define noret void __attribute__((noreturn))
#else
#define noret void
@ -46,392 +71,104 @@
#if defined(__GLIBC__) && !defined(__cplusplus)
/* use glibc internal longjmp to bypass fortify checks */
noret __libc_longjmp (jmp_buf buf, int val);
noret __libc_longjmp(jmp_buf buf, int val);
#define longjmp __libc_longjmp
#endif
#ifndef MAX
#define MAX(x,y) ((x) > (y) ? (x) : (y))
#define MAX(x, y) ((x) > (y) ? (x) : (y))
#endif
#ifndef MIN
#define MIN(x,y) ((x) < (y) ? (x) : (y))
#define MIN(x, y) ((x) < (y) ? (x) : (y))
#endif
#ifndef UNUSED
#define UNUSED(x) ((void)((x)))
#define UNUSED(x) ((void)((x)))
#endif
#define UNIT_V_EXHALT (UNIT_V_UF + 0)
#define UNIT_EXHALT (1u << UNIT_V_EXHALT)
#define UNIT_V_EXHALT (UNIT_V_UF + 0)
#define UNIT_EXHALT (1u << UNIT_V_EXHALT)
#define EX_V_FLAG 1 << 21
/* -t flag: Translate a virtual address */
#define EX_T_FLAG 1 << 19
/* -v flag for examine routine */
#define EX_V_FLAG 1 << 21
#define MAX_HIST_SIZE 10000000
#define MIN_HIST_SIZE 64
#define MAXMEMSIZE (1 << 22) /* 4 MB */
#define MEM_SIZE (cpu_unit.capac) /* actual memory size */
#define UNIT_V_MSIZE (UNIT_V_UF)
#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
#define WD_MSB 0x80000000
#define HW_MSB 0x8000
#define BT_MSB 0x80
#define WORD_MASK 0xffffffff
#define HALF_MASK 0xffffu
#define BYTE_MASK 0xff
/*
* Custom t_stat
*/
#define SCPE_PEND (SCPE_OK + 1) /* CIO job already pending */
#define SCPE_NOJOB (SCPE_OK + 2) /* No CIO job on the request queue */
/*
*
* Physical memory in the 3B2 is arranged as follows:
*
* 0x00000000 - 0x0000FFFF: 64KB ROM (32K used)
* 0x00040000 - 0x0004FFFF: IO
* 0x02000000 - 0x023FFFFF: 4MB RAM ("Mainstore"),
*
*/
#define PHYS_MEM_BASE 0x2000000
#define ROM_BASE 0
/* IO area */
#define IO_BOTTOM 0x40000
#define IO_TOP 0x50000
/* Register numbers */
#define NUM_FP 9
#define NUM_AP 10
#define NUM_PSW 11
#define NUM_SP 12
#define NUM_PCBP 13
#define NUM_ISP 14
#define NUM_PC 15
/* System board interrupt priority levels */
#define CPU_PIR8_IPL 8
#define CPU_PIR9_IPL 9
#define CPU_ID_IF_IPL 11
#define CPU_IU_DMA_IPL 13
#define CPU_TMR_IPL 15
#define CPU_CM (cpu_km ? L_KERNEL : ((R[NUM_PSW] >> PSW_CM) & 3))
#define PHYS_MEM_BASE 0x2000000
/* Simulator stop codes */
#define STOP_RSRV 1
#define STOP_IBKPT 2 /* Breakpoint encountered */
#define STOP_OPCODE 3 /* Invalid opcode */
#define STOP_IRQ 4 /* Interrupt */
#define STOP_EX 5 /* Exception */
#define STOP_ESTK 6 /* Exception stack too deep */
#define STOP_MMU 7 /* Unimplemented MMU Feature */
#define STOP_POWER 8 /* System power-off */
#define STOP_LOOP 9 /* Infinite loop stop */
#define STOP_ERR 10 /* Other error */
/* Exceptional conditions handled within the instruction loop */
#define ABORT_EXC 1 /* CPU exception */
#define ABORT_TRAP 2 /* CPU trap */
/* Contexts for aborts */
#define C_NONE 0 /* No context. Normal handling. */
#define C_NORMAL_GATE_VECTOR 1
#define C_PROCESS_GATE_PCB 2
#define C_PROCESS_OLD_PCB 3
#define C_PROCESS_NEW_PCB 4
#define C_RESET_GATE_VECTOR 5
#define C_RESET_INT_STACK 6
#define C_RESET_NEW_PCB 7
#define C_RESET_SYSTEM_DATA 8
#define C_STACK_FAULT 9
#define STOP_RSRV 1
#define STOP_IBKPT 2 /* Breakpoint encountered */
#define STOP_OPCODE 3 /* Invalid opcode */
#define STOP_IRQ 4 /* Interrupt */
#define STOP_EX 5 /* Exception */
#define STOP_ESTK 6 /* Exception stack too deep */
#define STOP_MMU 7 /* Unimplemented MMU Feature */
#define STOP_POWER 8 /* System power-off */
#define STOP_LOOP 9 /* Infinite loop stop */
#define STOP_ERR 10 /* Other error */
/* Debug flags */
#define READ_MSG 0x0001
#define WRITE_MSG 0x0002
#define DECODE_MSG 0x0004
#define EXECUTE_MSG 0x0008
#define INIT_MSG 0x0010
#define IRQ_MSG 0x0020
#define IO_DBG 0x0040
#define CIO_DBG 0x0080
#define TRACE_DBG 0x0100
#define CALL_DBG 0x0200
#define PKT_DBG 0x0400
#define ERR_MSG 0x0800
#define CACHE_DBG 0x1000
#define DECODE_DBG 0x2000
#define READ_MSG 0x0001
#define WRITE_MSG 0x0002
#define DECODE_MSG 0x0004
#define EXECUTE_MSG 0x0008
#define INIT_MSG 0x0010
#define IRQ_MSG 0x0020
#define IO_DBG 0x0040
#define CIO_DBG 0x0080
#define TRACE_DBG 0x0100
#define CALL_DBG 0x0200
#define PKT_DBG 0x0400
#define ERR_MSG 0x0800
#define CACHE_DBG 0x1000
#define DECODE_DBG 0x2000
/* Data types operated on by instructions. NB: These integer values
have meaning when decoding instructions, so this is not just an
enum. Please don't change them. */
#define UW 0 /* Unsigned Word */
#define UH 2 /* Unsigned Halfword */
#define BT 3 /* Unsigned Byte */
#define WD 4 /* Signed Word */
#define HW 6 /* Signed Halfword */
#define SB 7 /* Signed Byte */
/* Global symbols */
#define NA -1
extern volatile int32 stop_reason;
/*
* Exceptions are described on page 2-66 of the WE32100 manual
*/
extern CIO_STATE cio[CIO_SLOTS];
/* Exception Types */
extern instr *cpu_instr;
extern uint32 *ROM;
extern uint32 *RAM;
extern uint32 R[16];
extern REG cpu_reg[];
extern UNIT cpu_unit;
extern uint8 fault;
extern t_bool cpu_km;
extern uint32 R[16];
extern char sim_name[];
extern REG *sim_PC;
extern int32 sim_emax;
extern uint16 csr_data;
extern int32 tmxr_poll;
#define RESET_EXCEPTION 0
#define PROCESS_EXCEPTION 1
#define STACK_EXCEPTION 2
#define NORMAL_EXCEPTION 3
extern DEBTAB sys_deb_tab[];
extern DEVICE contty_dev;
extern DEVICE cpu_dev;
extern DEVICE csr_dev;
extern DEVICE ctc_dev;
extern DEVICE dmac_dev;
extern DEVICE id_dev;
extern DEVICE if_dev;
extern DEVICE iu_timer_dev;
extern DEVICE mau_dev;
extern DEVICE mmu_dev;
extern DEVICE ni_dev;
extern DEVICE nvram_dev;
extern DEVICE ports_dev;
extern DEVICE timer_dev;
extern DEVICE tod_dev;
extern DEVICE tti_dev;
extern DEVICE tto_dev;
/* Reset Exceptions */
#define OLD_PCB_FAULT 0
#define SYSTEM_DATA_FAULT 1
#define INTERRUPT_STACK_FAULT 2
#define EXTERNAL_RESET 3
#define NEW_PCB_FAULT 4
#define GATE_VECTOR_FAULT 6
extern IU_PORT iu_console;
extern IU_PORT iu_contty;
extern IF_STATE if_state;
extern MMU_STATE mmu_state;
extern DMA_STATE dma_state;
/* Processor Exceptions */
#define GATE_PCB_FAULT 1
/* Stack Exceptions */
#define STACK_BOUND 0
#define STACK_FAULT 1
#define INTERRUPT_ID_FETCH 3
/* Normal Exceptions */
#define INTEGER_ZERO_DIVIDE 0
#define TRACE_TRAP 1
#define ILLEGAL_OPCODE 2
#define RESERVED_OPCODE 3
#define INVALID_DESCRIPTOR 4
#define EXTERNAL_MEMORY_FAULT 5
#define N_GATE_VECTOR 6
#define ILLEGAL_LEVEL_CHANGE 7
#define RESERVED_DATATYPE 8
#define INTEGER_OVERFLOW 9
#define PRIVILEGED_OPCODE 10
#define BREAKPOINT_TRAP 14
#define PRIVILEGED_REGISTER 15
#define PSW_ET 0
#define PSW_TM 2u
#define PSW_ISC 3u
#define PSW_I 7
#define PSW_R 8
#define PSW_PM 9
#define PSW_CM 11
#define PSW_IPL 13
#define PSW_TE 17
#define PSW_C 18
#define PSW_V 19
#define PSW_Z 20
#define PSW_N 21
#define PSW_OE 22
#define PSW_CD 23
#define PSW_QIE 24
#define PSW_CFD 25
/* Access Request types */
#define ACC_MT 0 /* Move Translated */
#define ACC_SPW 1 /* Support processor write */
#define ACC_SPF 3 /* Support processor fetch */
#define ACC_IR 7 /* Interlocked read */
#define ACC_AF 8 /* Address fetch */
#define ACC_OF 9 /* Operand fetch */
#define ACC_W 10 /* Write */
#define ACC_IFAD 12 /* Instruction fetch after discontinuity */
#define ACC_IF 13 /* Instruction fetch */
#define L_KERNEL 0
#define L_EXEC 1
#define L_SUPER 2
#define L_USER 3
#define PSW_ET_MASK 3u
#define PSW_TM_MASK (1u << PSW_TM)
#define PSW_ISC_MASK (15u << PSW_ISC)
#define PSW_I_MASK (1u << PSW_I)
#define PSW_R_MASK (1u << PSW_R)
#define PSW_PM_MASK (3u << PSW_PM)
#define PSW_CM_MASK (3u << PSW_CM)
#define PSW_IPL_MASK (15u << PSW_IPL)
#define PSW_TE_MASK (1u << PSW_TE)
#define PSW_C_MASK (1u << PSW_C)
#define PSW_V_MASK (1u << PSW_V)
#define PSW_N_MASK (1u << PSW_N)
#define PSW_Z_MASK (1u << PSW_Z)
#define PSW_OE_MASK (1u << PSW_OE)
#define PSW_CD_MASK (1u << PSW_CD)
#define PSW_QIE_MASK (1u << PSW_QIE)
#define PSW_CFD_MASK (1u << PSW_CFD)
#define PSW_CUR_IPL (((R[NUM_PSW] & PSW_IPL_MASK) >> PSW_IPL) & 0xf)
#define TODBASE 0x41000
#define TODSIZE 0x40
#define TIMERBASE 0x42000
#define TIMERSIZE 0x20
#define NVRAMBASE 0x43000
#define NVRAMSIZE 0x1000
#define CSRBASE 0x44000
#define CSRSIZE 0x100
#define CSRTIMO 0x8000 /* Bus Timeout Error */
#define CSRPARE 0x4000 /* Memory Parity Error */
#define CSRRRST 0x2000 /* System Reset Request */
#define CSRALGN 0x1000 /* Memory Alignment Fault */
#define CSRLED 0x0800 /* Failure LED */
#define CSRFLOP 0x0400 /* Floppy Motor On */
#define CSRRES 0x0200 /* Reserved */
#define CSRITIM 0x0100 /* Inhibit Timers */
#define CSRIFLT 0x0080 /* Inhibit Faults */
#define CSRCLK 0x0040 /* Clock Interrupt */
#define CSRPIR8 0x0020 /* Programmed Interrupt 8 */
#define CSRPIR9 0x0010 /* Programmed Interrupt 9 */
#define CSRUART 0x0008 /* UART Interrupt */
#define CSRDISK 0x0004 /* Floppy Interrupt */
#define CSRDMA 0x0002 /* DMA Interrupt */
#define CSRIOF 0x0001 /* I/O Board Fail */
#define TIMER_REG_DIVA 0x03
#define TIMER_REG_DIVB 0x07
#define TIMER_REG_DIVC 0x0b
#define TIMER_REG_CTRL 0x0f
#define TIMER_CLR_LATCH 0x13
/* Clock state bitmasks */
#define CLK_MD 0x0E /* Mode mask */
#define CLK_RW 0x30 /* RW mask */
#define CLK_SC 0xC0 /* SC mask */
#define CLK_LAT 0x00
#define CLK_LSB 0x10
#define CLK_MSB 0x20
#define CLK_LMB 0x30
#define CLK_MD0 0x00
#define CLK_MD1 0x02
#define CLK_MD2 0x04
#define CLK_MD3 0x06
#define CLK_MD4 0x08
#define CLK_MD5 0x0a
/* IO area */
#define MEMSIZE_REG 0x4C003
#define CIO_BOTTOM 0x200000
#define CIO_TOP 0x2000000
#define CIO_SLOTS 12
#define CIO_CMDSTAT 0x80
#define CIO_SEQBIT 0x40
#define CIO_INT_DELAY 8000
/* Timer definitions */
#define TMR_CLK 0 /* The clock responsible for IPL 15 interrupts */
#define TPS_CLK 100 /* 100 ticks per second */
/* global symbols from the CPU */
extern jmp_buf save_env;
extern uint32 *ROM;
extern uint32 *RAM;
extern uint32 R[16];
extern REG cpu_reg[];
extern DEVICE cpu_dev;
extern UNIT cpu_unit;
extern uint8 fault;
extern DEBTAB sys_deb_tab[];
extern t_bool cpu_km;
/* global symbols from the DMAC */
typedef struct {
uint8 page;
uint16 addr; /* Original addr */
uint16 wcount; /* Original wcount */
uint16 addr_c; /* Current addr */
int32 wcount_c; /* Current word-count */
uint16 ptr; /* Pointer into memory */
} dma_channel;
typedef struct {
/* Byte (high/low) flip-flop */
uint8 bff;
/* Address and count registers for channels 0-3 */
dma_channel channels[4];
/* DMAC programmable registers */
uint8 command;
uint8 mode;
uint8 request;
uint8 mask;
uint8 status;
} DMA_STATE;
/* global symbols from DMA */
extern DMA_STATE dma_state;
extern DEVICE dmac_dev;
uint32 dma_address(uint8 channel, uint32 offset, t_bool r);
/* global symbols from the CSR */
extern uint16 csr_data;
/* global symbols from the timer */
extern int32 tmxr_poll;
/* global symbols from the IU */
extern t_bool iu_increment_a;
extern t_bool iu_increment_b;
extern void increment_modep_a();
extern void increment_modep_b();
/* global symbols from the MMU */
extern t_stat mmu_decode_va(uint32 va, uint8 r_acc, t_bool fc, uint32 *pa);
extern void mmu_enable();
extern void mmu_disable();
extern uint8 read_b(uint32 va, uint8 acc);
extern uint16 read_h(uint32 va, uint8 acc);
extern uint32 read_w(uint32 va, uint8 acc);
extern void write_b(uint32 va, uint8 val);
extern void write_h(uint32 va, uint16 val);
extern void write_w(uint32 va, uint32 val);
extern void pwrite_w(uint32 pa, uint32 val);
extern uint32 pread_w(uint32 pa);
/* global symbols from the MAU */
extern t_stat mau_broadcast(uint32 cmd, uint32 src, uint32 dst);
/* Globally scoped CPU functions */
extern void cpu_abort(uint8 et, uint8 isc);
extern void cpu_set_irq(uint8 ipl, uint8 id, uint16 csr_flags);
extern void cpu_clear_irq(uint8 ipl, uint16 csr_flags);
/* global symbols from the IO system */
extern uint32 io_read(uint32 pa, size_t size);
extern void io_write(uint32 pa, uint32 val, size_t size);
extern void cio_clear(uint8 cid);
extern void cio_xfer();
extern uint8 cio_int;
extern uint16 cio_ipl;
/* Future Use: Global symbols from the PORTS card */
/* extern void ports_express(uint8 cid); */
/* extern void ports_full(uint8 cid); */
/* extern void ports_xfer(uint8 cid); */
extern t_bool id_drq;
extern t_bool if_irq;
extern t_bool cio_skip_seqbit;
extern t_bool iu_increment_a;
extern t_bool iu_increment_b;
#endif

1
3B2/3b2_dmac.c
View file

@ -28,6 +28,7 @@
from the author.
*/
#include "3b2_defs.h"
#include "3b2_dmac.h"
DMA_STATE dma_state;

60
3B2/3b2_dmac.h
View file

@ -31,40 +31,7 @@
#ifndef _3B2_DMAC_H_
#define _3B2_DMAC_H_
#include "3b2_sysdev.h"
#include "3b2_id.h"
#include "3b2_if.h"
/* DMA Controller */
#define DMACBASE 0x48000
#define DMACSIZE 0x11
/* DMA integrated disk page buffer */
#define DMAIDBASE 0x45000
#define DMAIDSIZE 0x5
/* DMA integrated uart A page buffer */
#define DMAIUABASE 0x46000
#define DMAIUASIZE 0x5
/* DMA integrated uart B page buffer */
#define DMAIUBBASE 0x47000
#define DMAIUBSIZE 0x5
/* DMA integrated floppy page buffer */
#define DMAIFBASE 0x4E000
#define DMAIFSIZE 0x5
#define DMA_ID_CHAN 0
#define DMA_IF_CHAN 1
#define DMA_IUA_CHAN 2
#define DMA_IUB_CHAN 3
#define DMA_ID 0x45
#define DMA_IUA 0x46
#define DMA_IUB 0x47
#define DMA_C 0x48
#define DMA_IF 0x4E
#include "sim_defs.h"
#define DMA_MODE_VERIFY 0
#define DMA_MODE_WRITE 1 /* Write to memory from device */
@ -72,6 +39,30 @@
#define DMA_IF_READ (IFBASE + IF_DATA_REG)
typedef struct {
uint8 page;
uint16 addr; /* Original addr */
uint16 wcount; /* Original wcount */
uint16 addr_c; /* Current addr */
int32 wcount_c; /* Current word-count */
uint16 ptr; /* Pointer into memory */
} dma_channel;
typedef struct {
/* Byte (high/low) flip-flop */
uint8 bff;
/* Address and count registers for channels 0-3 */
dma_channel channels[4];
/* DMAC programmable registers */
uint8 command;
uint8 mode;
uint8 request;
uint8 mask;
uint8 status;
} DMA_STATE;
typedef struct {
uint8 channel;
uint32 service_address;
@ -86,5 +77,6 @@ uint32 dmac_read(uint32 pa, size_t size);
void dmac_write(uint32 pa, uint32 val, size_t size);
void dmac_service_drqs();
void dmac_generic_dma(uint8 channel, uint32 service_address);
uint32 dma_address(uint8 channel, uint32 offset, t_bool r);
#endif

3
3B2/3b2_id.c
View file

@ -1,4 +1,4 @@
/* 3b2_cpu.h: AT&T 3B2 Model 400 Hard Disk (uPD7261) Implementation
/* 3b2_d.h: AT&T 3B2 Model 400 Hard Disk (uPD7261) Implementation
Copyright (c) 2017, Seth J. Morabito
@ -42,6 +42,7 @@
* HD135 11 1224 15 18 512 Maxtor XT1190
*/
#include "3b2_defs.h"
#include "3b2_id.h"
#define ID_SEEK_WAIT 50

18
3B2/3b2_id.h
View file

@ -1,4 +1,4 @@
/* 3b2_cpu.h: AT&T 3B2 Model 400 Hard Disk (uPD7261) Header
/* 3b2_id.h: AT&T 3B2 Model 400 Hard Disk (uPD7261) Header
Copyright (c) 2017, Seth J. Morabito
@ -31,17 +31,13 @@
#ifndef __3B2_ID_H__
#define __3B2_ID_H__
#include "3b2_defs.h"
#include "3b2_sysdev.h"
#include "sim_defs.h"
#include "sim_disk.h"
#define ID0 0
#define ID1 1
#define ID_CTLR 2
#define ID_DATA_REG 0
#define ID_CMD_STAT_REG 1
/* Command Codes (bits 3-7 of command byte) */
#define ID_CMD_AUX 0x00 /* Auxiliary Command */
@ -157,15 +153,7 @@
#define DMA_ID_SVC IDBASE+ID_DATA_REG
extern DEVICE id_dev;
extern DEBTAB sys_deb_tab[];
extern t_bool id_drq;
extern t_bool id_int();
#define IDBASE 0x4a000
#define IDSIZE 0x2
#define CMD_NUM ((id_cmd >> 4) & 0xf)
#define CMD_NUM ((id_cmd >> 4) & 0xf)
/* Function prototypes */

3
3B2/3b2_if.c
View file

@ -1,4 +1,4 @@
/* 3b2_cpu.h: AT&T 3B2 Model 400 Floppy (TMS2797NL) Implementation
/* 3b2_if.c: AT&T 3B2 Floppy Controller (TMS2797NL) Implementation
Copyright (c) 2017, Seth J. Morabito
@ -28,6 +28,7 @@
from the author.
*/
#include "3b2_defs.h"
#include "3b2_if.h"
/* Static function declarations */

21
3B2/3b2_if.h
View file

@ -1,4 +1,4 @@
/* 3b2_cpu.h: AT&T 3B2 Model 400 Floppy (TMS2797NL) Header
/* 3b2_if.h: AT&T 3B2 Model Floppy Controller (TMS2797NL) Header
Copyright (c) 2017, Seth J. Morabito
@ -31,9 +31,7 @@
#ifndef __3B2_IF_H__
#define __3B2_IF_H__
#include "3b2_defs.h"
#include "3b2_sysdev.h"
#include "3b2_sys.h"
#include "sim_defs.h"
typedef struct {
uint8 data;
@ -48,21 +46,6 @@ typedef struct {
t_bool drq;
} IF_STATE;
extern DEVICE if_dev;
extern DEBTAB sys_deb_tab[];
extern IF_STATE if_state;
extern t_bool if_irq;
#define IFBASE 0x4d000
#define IFSIZE 0x10
#define IF_STATUS_REG 0
#define IF_CMD_REG 0
#define IF_TRACK_REG 1
#define IF_SECTOR_REG 2
#define IF_DATA_REG 3
/* Status Bits */
#define IF_BUSY 0x01
#define IF_DRQ 0x02

5
3B2/3b2_io.c
View file

@ -1,4 +1,4 @@
/* 3b2_cpu.h: AT&T 3B2 Model 400 IO and CIO feature cards
/* 3b2_io.c: AT&T 3B2 Model 400 IO and CIO feature cards
Copyright (c) 2017, Seth J. Morabito
@ -28,10 +28,9 @@
from the author.
*/
#include "3b2_defs.h"
#include "3b2_io.h"
#define CRC_POLYNOMIAL 0xEDB88320
CIO_STATE cio[CIO_SLOTS] = {{0}};
struct iolink iotable[] = {

29
3B2/3b2_io.h
View file

@ -1,4 +1,4 @@
/* 3b2_cpu.h: AT&T 3B2 Model 400 IO dispatch (Header)
/* 3b2_io.h: AT&T 3B2 Model 400 IO dispatch (Header)
Copyright (c) 2017, Seth J. Morabito
@ -111,15 +111,21 @@
#ifndef _3B2_IO_H_
#define _3B2_IO_H_
#include "3b2_sysdev.h"
#include "3b2_iu.h"
#include "3b2_if.h"
#include "3b2_id.h"
#include "3b2_dmac.h"
#include "3b2_mmu.h"
#include "sim_defs.h"
#include "sim_tmxr.h"
#define CRC_POLYNOMIAL 0xEDB88320
#define CIO_SLOTS 12
/* IO area */
#define IO_BOTTOM 0x40000
#define IO_TOP 0x50000
/* CIO area */
#define CIO_BOTTOM 0x200000
#define CIO_TOP 0x2000000
#define IOF_ID 0
#define IOF_VEC 1
#define IOF_CTRL 3
@ -219,10 +225,6 @@ typedef struct {
uint32 retcode;
} pump;
extern t_bool cio_skip_seqbit;
extern uint16 cio_ints;
extern CIO_STATE cio[CIO_SLOTS];
t_stat cio_reset(DEVICE *dptr);
t_stat cio_svc(UNIT *uptr);
@ -240,6 +242,9 @@ uint16 cio_c_lp(uint8 cid, uint32 esize);
uint16 cio_c_ulp(uint8 cid, uint32 esize);
void cio_sysgen(uint8 cid);
uint32 io_read(uint32 pa, size_t size);
void io_write(uint32 pa, uint32 val, size_t size);
void dump_entry(uint32 dbits, DEVICE *dev, CONST char *type,
uint32 esize, cio_entry *entry, uint8 *app_data);

4
3B2/3b2_iu.c
View file

@ -28,8 +28,8 @@
from the author.
*/
#include "3b2_defs.h"
#include "3b2_iu.h"
#include "sim_tmxr.h"
/* Static function declarations */
static SIM_INLINE void iu_w_cmd(uint8 portno, uint8 val);
@ -73,8 +73,6 @@ IU_TIMER_STATE iu_timer_state;
t_bool iu_increment_a = FALSE;
t_bool iu_increment_b = FALSE;
extern uint16 csr_data;
BITFIELD sr_bits[] = {
BIT(RXRDY),
BIT(FFULL),

14
3B2/3b2_iu.h
View file

@ -31,8 +31,8 @@
#ifndef __3B2_IU_H__
#define __3B2_IU_H__
#include "3b2_defs.h"
#include "3b2_sysdev.h"
#include "sim_defs.h"
#include "sim_tmxr.h"
#define CMD_ERX 0x01 /* Enable receiver */
#define CMD_DRX 0x02 /* Disable receiver */
@ -135,11 +135,6 @@
#define IU_MODE(x) ((x & UM_MASK) >> UM_SHIFT)
extern DEVICE tti_dev;
extern DEVICE tto_dev;
extern DEVICE contty_dev;
extern DEVICE iu_timer_dev;
#define IUBASE 0x49000
#define IUSIZE 0x100
@ -189,9 +184,6 @@ typedef struct iu_timer_state {
t_bool c_en;
} IU_TIMER_STATE;
extern IU_PORT iu_console;
extern IU_PORT iu_contty;
/* Function prototypes */
t_stat contty_attach(UNIT *uptr, CONST char *cptr);
t_stat contty_detach(UNIT *uptr);
@ -212,5 +204,7 @@ void iu_txrdy_a_irq();
void iu_txrdy_b_irq();
void iu_dma_console(uint8 channel, uint32 service_address);
void iu_dma_contty(uint8 channel, uint32 service_address);
void increment_modep_a();
void increment_modep_b();
#endif

3
3B2/3b2_ni.c
View file

@ -93,12 +93,11 @@
*
*/
#include "3b2_defs.h"
#include "3b2_ni.h"
#include <math.h>
extern CIO_STATE cio[CIO_SLOTS];
/* State container for the card */
NI_STATE ni;

5
3B2/3b2_ni.h
View file

@ -31,8 +31,7 @@
#ifndef _3B2_NI_H_
#define _3B2_NI_H_
#include "3b2_defs.h"
#include "3b2_io.h"
#include "sim_defs.h"
#include "sim_ether.h"
#define NI_ID 0x0002
@ -188,8 +187,6 @@ typedef struct {
ETH_PCALLBACK callback;
} NI_STATE;
extern DEVICE ni_dev;
void ni_recv_callback(int status);
t_stat ni_reset(DEVICE *dptr);
t_stat ni_rcv_svc(UNIT *uptr);

4
3B2/3b2_ports.c
View file

@ -42,15 +42,13 @@
*
*/
#include "3b2_defs.h"
#include "3b2_ports.h"
/* Static function declarations */
static t_stat ports_show_queue_common(FILE *st, UNIT *uptr, int32 val,
CONST void *desc, t_bool rq);
extern CIO_STATE cio[CIO_SLOTS];
extern UNIT cio_unit;
/* Device and units for PORTS cards
* --------------------------------
*

5
3B2/3b2_ports.h
View file

@ -45,8 +45,7 @@
#ifndef _3B2_PORTS_H_
#define _3B2_PORTS_H_
#include "3b2_defs.h"
#include "3b2_io.h"
#include "sim_defs.h"
#define PORTS_ID 0x0003
#define PORTS_IPL 10
@ -216,8 +215,6 @@ typedef struct {
uint16 pad3;
} PORTS_OPTIONS;
extern DEVICE ports_dev;
t_stat ports_reset(DEVICE *dptr);
t_stat ports_setnl(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
t_stat ports_show_cqueue(FILE *st, UNIT *uptr, int32 val, CONST void *desc);

BIN
3B2/rom_1000.bin Normal file
View file

Binary file not shown.

8205
3B2/rom_1000_bin.h Normal file
View file

File diff suppressed because it is too large Load diff

24
Visual Studio Projects/3B2.vcproj
View file

@ -192,7 +192,7 @@
Filter="cpp;c;cxx;def;odl;idl;hpj;bat;asm"
>
<File
RelativePath="..\3B2\3b2_cpu.c"
RelativePath="..\3B2\3b2_400_cpu.c"
>
</File>
<File
@ -220,11 +220,11 @@
>
</File>
<File
RelativePath="..\3B2\3b2_mau.c"
RelativePath="..\3B2\3b2_400_mau.c"
>
</File>
<File
RelativePath="..\3B2\3b2_mmu.c"
RelativePath="..\3B2\3b2_400_mmu.c"
>
</File>
<File
@ -236,11 +236,11 @@
>
</File>
<File
RelativePath="..\3B2\3b2_sys.c"
RelativePath="..\3B2\3b2_400_sys.c"
>
</File>
<File
RelativePath="..\3B2\3b2_sysdev.c"
RelativePath="..\3B2\3b2_400_stddev.c"
>
</File>
<File
@ -480,7 +480,7 @@
Filter="h;hpp;hxx;hm;inl;inc"
>
<File
RelativePath="..\3B2\3b2_cpu.h"
RelativePath="..\3B2\3b2_400_cpu.h"
>
</File>
<File
@ -491,6 +491,10 @@
RelativePath="..\3B2\3b2_defs.h"
>
</File>
<File
RelativePath="..\3B2\3b2_400_defs.h"
>
</File>
<File
RelativePath="..\3B2\3b2_dmac.h"
>
@ -512,11 +516,11 @@
>
</File>
<File
RelativePath="..\3B2\3b2_mau.h"
RelativePath="..\3B2\3b2_400_mau.h"
>
</File>
<File
RelativePath="..\3B2\3b2_mmu.h"
RelativePath="..\3B2\3b2_400_mmu.h"
>
</File>
<File
@ -528,11 +532,11 @@
>
</File>
<File
RelativePath="..\3B2\3b2_sys.h"
RelativePath="..\3B2\3b2_400_sys.h"
>
</File>
<File
RelativePath="..\3B2\3b2_sysdev.h"
RelativePath="..\3B2\3b2_400_stddev.h"
>
</File>
<File

18
makefile
View file

@ -2054,14 +2054,14 @@ KL10 = ${KL10D}/kx10_cpu.c ${KL10D}/kx10_sys.c ${KL10D}/kx10_df.c \
KL10_OPT = -DKL=1 -DUSE_INT64 -I $(KL10D) -DUSE_SIM_CARD ${NETWORK_OPT}
ATT3B2D = ${SIMHD}/3B2
ATT3B2 = ${ATT3B2D}/3b2_cpu.c ${ATT3B2D}/3b2_mmu.c \
${ATT3B2D}/3b2_iu.c ${ATT3B2D}/3b2_if.c \
${ATT3B2D}/3b2_id.c ${ATT3B2D}/3b2_dmac.c \
${ATT3B2D}/3b2_sys.c ${ATT3B2D}/3b2_io.c \
ATT3B2M400 = ${ATT3B2D}/3b2_400_cpu.c ${ATT3B2D}/3b2_400_sys.c \
${ATT3B2D}/3b2_400_stddev.c ${ATT3B2D}/3b2_400_mmu.c \
${ATT3B2D}/3b2_400_mau.c ${ATT3B2D}/3b2_iu.c \
${ATT3B2D}/3b2_if.c ${ATT3B2D}/3b2_id.c \
${ATT3B2D}/3b2_dmac.c ${ATT3B2D}/3b2_io.c \
${ATT3B2D}/3b2_ports.c ${ATT3B2D}/3b2_ctc.c \
${ATT3B2D}/3b2_ni.c ${ATT3B2D}/3b2_mau.c \
${ATT3B2D}/3b2_sysdev.c
ATT3B2_OPT = -DUSE_INT64 -DUSE_ADDR64 -I ${ATT3B2D} ${NETWORK_OPT}
${ATT3B2D}/3b2_ni.c
ATT3B2_OPT = -DUSE_INT64 -DUSE_ADDR64 -I ${ATT3B2M400B2D} ${NETWORK_OPT}
###
### Experimental simulators
@ -2824,9 +2824,9 @@ endif
3b2 : ${BIN}3b2${EXE}
${BIN}3b2${EXE} : ${ATT3B2} ${SIM} ${BUILD_ROMS}
${BIN}3b2${EXE} : ${ATT3B2M400} ${SIM} ${BUILD_ROMS}
${MKDIRBIN}
${CC} ${ATT3B2} ${SIM} ${ATT3B2_OPT} ${CC_OUTSPEC} ${LDFLAGS}
${CC} ${ATT3B2M400} ${SIM} ${ATT3B2_OPT} ${CC_OUTSPEC} ${LDFLAGS}
ifneq (,$(call find_test,${ATT3B2D},3b2))
$@ $(call find_test,${ATT3B2D},3b2) ${TEST_ARG}
endif

1
sim_BuildROMs.c
View file

@ -71,6 +71,7 @@ struct ROM_File_Descriptor {
{"PDP11/11logo/11logo.lda", "PDP11/pdp11_11logo_rom.h", 26009, 0xFFDD77F7, "logo_lda"},
{"swtp6800/swtp6800/swtbug.bin", "swtp6800/swtp6800/swtp_swtbug_bin.h", 1024, 0xFFFE4FBC, "swtp_swtbug_bin"},
{"3B2/rom_400.bin", "3B2/rom_400_bin.h", 32768, 0xFFD55762, "rom_400_bin"},
{"3B2/rom_1000.bin", "3B2/rom_1000_bin.h", 131072, 0xFFDC0EB8, "rom_1000_bin"},
};