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sigma: add wait code to WAIT instruction

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Bob Supnik 2023-05-09 23:09:05 -07:00 • committed by ken rector
parent 609d46e801
commit 1ea82bd127
2 changed files with 13 additions and 7 deletions
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7
sigma/sigma_cpu.c Normal file → Executable file
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@ -174,6 +174,7 @@ uint32 cpu_pdf = 0; /* proc detected fault *
uint32 cons_alarm = 0; /* console alarm */
uint32 cons_alarm_enb = 0; /* alarm enable */
uint32 cons_pcf = 0;
uint32 wait_state = 0; /* wait state */
uint32 rf_bmax = 4; /* num reg blocks */
uint32 exu_lim = 32; /* nested EXU limit */
uint32 stop_op = 0; /* stop on ill op */
@ -447,6 +448,7 @@ while (reason == 0) { /* loop until stop */
if (int_hireq < NO_INT) { /* interrupt req? */
uint32 sav_hi, vec, wd, op;
wait_state = 0; /* exit wait state */
sav_hi = int_hireq; /* save level */
vec = io_ackn_int (int_hireq); /* get vector */
if (vec == 0) { /* illegal vector? */
@ -474,6 +476,8 @@ while (reason == 0) { /* loop until stop */
}
else reason = tr2; /* normal status code */
}
else if (wait_state != 0) /* wait state? don't fetch */
continue;
else { /* normal instruction */
if (sim_brk_summ &&
sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */
@ -1501,7 +1505,7 @@ switch (op) {
if (!io_poss_int ()) /* intr possible? */
return STOP_WAITNOINT; /* machine is hung */
// put idle here
int_hireq = io_eval_int (); /* re-eval intr */
wait_state = 1; /* wait for intr */
break;
case OP_AIO: /* acknowledge int */
@ -2513,6 +2517,7 @@ cpu_new_PSD (1, PSW1_DFLT | (PSW1 & PSW1_PCMASK), PSW2_DFLT);
cpu_pdf = 0;
cons_alarm = 0;
cons_pcf = 0;
wait_state = 0;
set_rf_display (R);
if (M == NULL)
M = (uint32 *) calloc (MAXMEMSIZE, sizeof (uint32));

11
sigma/sigma_io.c Normal file → Executable file
View file

@ -1,4 +1,4 @@
/* sigma_io.c: XDS Sigma IO simulator
/* sigma_io.c: XDS Sigma IO simulator
Copyright (c) 2007-2022, Robert M Supnik
@ -499,11 +499,12 @@ if ((rn != 0) && !(dvst & DVT_NOST)) { /* return status? */
if (tdv)
mrgst = (DVT_GETDVS (dvst) << 8) | (chan[ch].chf[dev] & 0xFF);
else mrgst = ((DVT_GETDVS(dvst) << 8) & ~CHF_ALL) | (chan[ch].chf[dev] & CHF_ALL);
R[rn] = chan[ch].clc[dev]; /* even reg */
if (!odd) /* even pair? */
WritePW (0x20, R[rn]); /* write to 20 */
if ((rn & 1) == 0) { /* even reg? */
R[rn] = chan[ch].clc[dev]; /* current addr to R */
WritePW (0x20, R[rn]); /* and loc 20 */
}
R[rn|1] = (mrgst << 16) | chan[ch].bc[dev]; /* odd reg */
WritePW (0x20 + odd, R[rn|1]); /* write to 20/21 */
WritePW (0x21, R[rn|1]); /* write loc 21 */
}
return DVT_GETCC (dvst);
}