ISYS8020: Fix spaces in i8259.c
This commit is contained in:
Bill Beech
parent
a1002569a1
commit
218dac51fe
1 changed files with 139 additions and 139 deletions
|
|
@ -27,8 +27,8 @@
|
|||
24 Jan 13 - Original file.
|
||||
*/
|
||||
|
||||
#include "system_defs.h" /* system header in system dir */
|
||||
#define i8259_DEV 2 /* number of devices */
|
||||
#include "system_defs.h" /* system header in system dir */
|
||||
#define i8259_DEV 2 /* number of devices */
|
||||
|
||||
/* function prototypes */
|
||||
|
||||
|
|
@ -98,7 +98,7 @@ DEVICE i8259_dev = {
|
|||
NULL, //examine
|
||||
NULL, //deposit
|
||||
// &i8259_reset, //reset
|
||||
NULL, //reset
|
||||
NULL, //reset
|
||||
NULL, //boot
|
||||
NULL, //attach
|
||||
NULL, //detach
|
||||
|
|
@ -119,67 +119,67 @@ int32 i8259a0(int32 io, int32 data)
|
|||
int32 bit;
|
||||
|
||||
if (io == 0) { /* read data port */
|
||||
if ((i8259_ocw3[0] & 0x03) == 0x02)
|
||||
return (i8259_unit[0].u3); /* IRR */
|
||||
if ((i8259_ocw3[0] & 0x03) == 0x03)
|
||||
return (i8259_unit[0].u4); /* ISR */
|
||||
if ((i8259_ocw3[0] & 0x03) == 0x02)
|
||||
return (i8259_unit[0].u3); /* IRR */
|
||||
if ((i8259_ocw3[0] & 0x03) == 0x03)
|
||||
return (i8259_unit[0].u4); /* ISR */
|
||||
} else { /* write data port */
|
||||
if (data & 0x10) {
|
||||
icw_num0 = 1;
|
||||
}
|
||||
if (icw_num0 == 1) {
|
||||
i8259_icw1[0] = data; /* ICW1 */
|
||||
i8259_unit[0].u5 = 0x00; /* clear IMR */
|
||||
i8259_ocw3[0] = 0x02; /* clear OCW3, Sel IRR */
|
||||
} else {
|
||||
switch (data & 0x18) {
|
||||
case 0: /* OCW2 */
|
||||
i8259_ocw2[0] = data;
|
||||
break;
|
||||
case 8: /* OCW3 */
|
||||
i8259_ocw3[0] = data;
|
||||
break;
|
||||
default:
|
||||
sim_printf("8259b-0: OCW Error %02X\n", data);
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (data & 0x10) {
|
||||
icw_num0 = 1;
|
||||
}
|
||||
if (icw_num0 == 1) {
|
||||
i8259_icw1[0] = data; /* ICW1 */
|
||||
i8259_unit[0].u5 = 0x00; /* clear IMR */
|
||||
i8259_ocw3[0] = 0x02; /* clear OCW3, Sel IRR */
|
||||
} else {
|
||||
switch (data & 0x18) {
|
||||
case 0: /* OCW2 */
|
||||
i8259_ocw2[0] = data;
|
||||
break;
|
||||
case 8: /* OCW3 */
|
||||
i8259_ocw3[0] = data;
|
||||
break;
|
||||
default:
|
||||
sim_printf("8259b-0: OCW Error %02X\n", data);
|
||||
break;
|
||||
}
|
||||
}
|
||||
sim_printf("8259a-0: data = %02X\n", data);
|
||||
icw_num0++; /* step ICW number */
|
||||
icw_num0++; /* step ICW number */
|
||||
}
|
||||
i8259_dump(0);
|
||||
i8259_dump(0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32 i8259b0(int32 io, int32 data)
|
||||
{
|
||||
if (io == 0) { /* read data port */
|
||||
return (i8259_unit[0].u5); /* IMR */
|
||||
return (i8259_unit[0].u5); /* IMR */
|
||||
} else { /* write data port */
|
||||
if (icw_num0 >= 2 && icw_num0 < 5) { /* ICW mode */
|
||||
switch (icw_num0) {
|
||||
case 2: /* ICW2 */
|
||||
i8259_icw2[0] = data;
|
||||
break;
|
||||
case 3: /* ICW3 */
|
||||
i8259_icw3[0] = data;
|
||||
break;
|
||||
case 4: /* ICW4 */
|
||||
if (i8259_icw1[0] & 0x01)
|
||||
i8259_icw4[0] = data;
|
||||
else
|
||||
sim_printf("8259b-0: ICW4 not enabled - data=%02X\n", data);
|
||||
break;
|
||||
default:
|
||||
sim_printf("8259b-0: ICW Error %02X\n", data);
|
||||
break;
|
||||
}
|
||||
icw_num0++;
|
||||
} else {
|
||||
i8259_ocw1[0] = data; /* OCW0 */
|
||||
}
|
||||
if (icw_num0 >= 2 && icw_num0 < 5) { /* ICW mode */
|
||||
switch (icw_num0) {
|
||||
case 2: /* ICW2 */
|
||||
i8259_icw2[0] = data;
|
||||
break;
|
||||
case 3: /* ICW3 */
|
||||
i8259_icw3[0] = data;
|
||||
break;
|
||||
case 4: /* ICW4 */
|
||||
if (i8259_icw1[0] & 0x01)
|
||||
i8259_icw4[0] = data;
|
||||
else
|
||||
sim_printf("8259b-0: ICW4 not enabled - data=%02X\n", data);
|
||||
break;
|
||||
default:
|
||||
sim_printf("8259b-0: ICW Error %02X\n", data);
|
||||
break;
|
||||
}
|
||||
icw_num0++;
|
||||
} else {
|
||||
i8259_ocw1[0] = data; /* OCW0 */
|
||||
}
|
||||
}
|
||||
i8259_dump(0);
|
||||
i8259_dump(0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -188,35 +188,35 @@ int32 i8259a1(int32 io, int32 data)
|
|||
int32 bit;
|
||||
|
||||
if (io == 0) { /* read data port */
|
||||
if ((i8259_ocw3[1] & 0x03) == 0x02)
|
||||
return (i8259_unit[1].u3); /* IRR */
|
||||
if ((i8259_ocw3[1] & 0x03) == 0x03)
|
||||
return (i8259_unit[1].u4); /* ISR */
|
||||
if ((i8259_ocw3[1] & 0x03) == 0x02)
|
||||
return (i8259_unit[1].u3); /* IRR */
|
||||
if ((i8259_ocw3[1] & 0x03) == 0x03)
|
||||
return (i8259_unit[1].u4); /* ISR */
|
||||
} else { /* write data port */
|
||||
if (data & 0x10) {
|
||||
icw_num1 = 1;
|
||||
}
|
||||
if (icw_num1 == 1) {
|
||||
i8259_icw1[1] = data; /* ICW1 */
|
||||
i8259_unit[1].u5 = 0x00; /* clear IMR */
|
||||
i8259_ocw3[1] = 0x02; /* clear OCW3, Sel IRR */
|
||||
} else {
|
||||
switch (data & 0x18) {
|
||||
case 0: /* OCW2 */
|
||||
i8259_ocw2[1] = data;
|
||||
break;
|
||||
case 8: /* OCW3 */
|
||||
i8259_ocw3[1] = data;
|
||||
break;
|
||||
default:
|
||||
sim_printf("8259b-1: OCW Error %02X\n", data);
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (data & 0x10) {
|
||||
icw_num1 = 1;
|
||||
}
|
||||
if (icw_num1 == 1) {
|
||||
i8259_icw1[1] = data; /* ICW1 */
|
||||
i8259_unit[1].u5 = 0x00; /* clear IMR */
|
||||
i8259_ocw3[1] = 0x02; /* clear OCW3, Sel IRR */
|
||||
} else {
|
||||
switch (data & 0x18) {
|
||||
case 0: /* OCW2 */
|
||||
i8259_ocw2[1] = data;
|
||||
break;
|
||||
case 8: /* OCW3 */
|
||||
i8259_ocw3[1] = data;
|
||||
break;
|
||||
default:
|
||||
sim_printf("8259b-1: OCW Error %02X\n", data);
|
||||
break;
|
||||
}
|
||||
}
|
||||
sim_printf("8259a-1: data = %02X\n", data);
|
||||
icw_num1++; /* step ICW number */
|
||||
icw_num1++; /* step ICW number */
|
||||
}
|
||||
i8259_dump(1);
|
||||
i8259_dump(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -225,79 +225,79 @@ int32 i8259b1(int32 io, int32 data)
|
|||
if (io == 0) { /* read data port */
|
||||
return (i8259_unit[1].u5); /* IMR */
|
||||
} else { /* write data port */
|
||||
if (icw_num1 >= 2 && icw_num1 < 5) { /* ICW mode */
|
||||
switch (icw_num1) {
|
||||
case 2: /* ICW2 */
|
||||
i8259_icw2[1] = data;
|
||||
break;
|
||||
case 3: /* ICW3 */
|
||||
i8259_icw3[1] = data;
|
||||
break;
|
||||
case 4: /* ICW4 */
|
||||
if (i8259_icw1[1] & 0x01)
|
||||
i8259_icw4[1] = data;
|
||||
else
|
||||
sim_printf("8259b-1: ICW4 not enabled - data=%02X\n", data);
|
||||
break;
|
||||
default:
|
||||
sim_printf("8259b-1: ICW Error %02X\n", data);
|
||||
break;
|
||||
}
|
||||
icw_num1++;
|
||||
} else {
|
||||
i8259_ocw1[1] = data; /* OCW0 */
|
||||
}
|
||||
if (icw_num1 >= 2 && icw_num1 < 5) { /* ICW mode */
|
||||
switch (icw_num1) {
|
||||
case 2: /* ICW2 */
|
||||
i8259_icw2[1] = data;
|
||||
break;
|
||||
case 3: /* ICW3 */
|
||||
i8259_icw3[1] = data;
|
||||
break;
|
||||
case 4: /* ICW4 */
|
||||
if (i8259_icw1[1] & 0x01)
|
||||
i8259_icw4[1] = data;
|
||||
else
|
||||
sim_printf("8259b-1: ICW4 not enabled - data=%02X\n", data);
|
||||
break;
|
||||
default:
|
||||
sim_printf("8259b-1: ICW Error %02X\n", data);
|
||||
break;
|
||||
}
|
||||
icw_num1++;
|
||||
} else {
|
||||
i8259_ocw1[1] = data; /* OCW0 */
|
||||
}
|
||||
}
|
||||
i8259_dump(1);
|
||||
i8259_dump(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void i8259_dump(int32 dev)
|
||||
{
|
||||
sim_printf("Device %d\n", dev);
|
||||
sim_printf(" IRR = %02X\n", i8259_unit[dev].u3);
|
||||
sim_printf(" ISR = %02X\n", i8259_unit[dev].u4);
|
||||
sim_printf(" IMR = %02X\n", i8259_unit[dev].u5);
|
||||
sim_printf(" ICW1 = %02X\n", i8259_icw1[dev]);
|
||||
sim_printf(" ICW2 = %02X\n", i8259_icw2[dev]);
|
||||
sim_printf(" ICW3 = %02X\n", i8259_icw3[dev]);
|
||||
sim_printf(" ICW4 = %02X\n", i8259_icw4[dev]);
|
||||
sim_printf(" OCW1 = %02X\n", i8259_ocw1[dev]);
|
||||
sim_printf(" OCW2 = %02X\n", i8259_ocw2[dev]);
|
||||
sim_printf(" OCW3 = %02X\n", i8259_ocw3[dev]);
|
||||
sim_printf("Device %d\n", dev);
|
||||
sim_printf(" IRR = %02X\n", i8259_unit[dev].u3);
|
||||
sim_printf(" ISR = %02X\n", i8259_unit[dev].u4);
|
||||
sim_printf(" IMR = %02X\n", i8259_unit[dev].u5);
|
||||
sim_printf(" ICW1 = %02X\n", i8259_icw1[dev]);
|
||||
sim_printf(" ICW2 = %02X\n", i8259_icw2[dev]);
|
||||
sim_printf(" ICW3 = %02X\n", i8259_icw3[dev]);
|
||||
sim_printf(" ICW4 = %02X\n", i8259_icw4[dev]);
|
||||
sim_printf(" OCW1 = %02X\n", i8259_ocw1[dev]);
|
||||
sim_printf(" OCW2 = %02X\n", i8259_ocw2[dev]);
|
||||
sim_printf(" OCW3 = %02X\n", i8259_ocw3[dev]);
|
||||
}
|
||||
|
||||
/* Reset routine */
|
||||
|
||||
t_stat i8259_reset (DEVICE *dptr, int32 base)
|
||||
{
|
||||
switch (i8259_cnt) {
|
||||
case 0:
|
||||
reg_dev(i8259a0, base);
|
||||
reg_dev(i8259b0, base + 1);
|
||||
reg_dev(i8259a0, base + 2);
|
||||
reg_dev(i8259b0, base + 3);
|
||||
i8259_unit[0].u3 = 0x00; /* IRR */
|
||||
i8259_unit[0].u4 = 0x00; /* ISR */
|
||||
i8259_unit[0].u5 = 0x00; /* IMR */
|
||||
sim_printf(" 8259-0: Reset\n");
|
||||
break;
|
||||
case 1:
|
||||
reg_dev(i8259a1, base);
|
||||
reg_dev(i8259b1, base + 1);
|
||||
reg_dev(i8259a1, base + 2);
|
||||
reg_dev(i8259b1, base + 3);
|
||||
i8259_unit[1].u3 = 0x00; /* IRR */
|
||||
i8259_unit[1].u4 = 0x00; /* ISR */
|
||||
i8259_unit[1].u5 = 0x00; /* IMR */
|
||||
sim_printf(" 8259-1: Reset\n");
|
||||
break;
|
||||
default:
|
||||
sim_printf(" 8259: Bad device\n");
|
||||
break;
|
||||
}
|
||||
switch (i8259_cnt) {
|
||||
case 0:
|
||||
reg_dev(i8259a0, base);
|
||||
reg_dev(i8259b0, base + 1);
|
||||
reg_dev(i8259a0, base + 2);
|
||||
reg_dev(i8259b0, base + 3);
|
||||
i8259_unit[0].u3 = 0x00; /* IRR */
|
||||
i8259_unit[0].u4 = 0x00; /* ISR */
|
||||
i8259_unit[0].u5 = 0x00; /* IMR */
|
||||
sim_printf(" 8259-0: Reset\n");
|
||||
break;
|
||||
case 1:
|
||||
reg_dev(i8259a1, base);
|
||||
reg_dev(i8259b1, base + 1);
|
||||
reg_dev(i8259a1, base + 2);
|
||||
reg_dev(i8259b1, base + 3);
|
||||
i8259_unit[1].u3 = 0x00; /* IRR */
|
||||
i8259_unit[1].u4 = 0x00; /* ISR */
|
||||
i8259_unit[1].u5 = 0x00; /* IMR */
|
||||
sim_printf(" 8259-1: Reset\n");
|
||||
break;
|
||||
default:
|
||||
sim_printf(" 8259: Bad device\n");
|
||||
break;
|
||||
}
|
||||
sim_printf(" 8259-%d: Registered at %02X\n", i8259_cnt, base);
|
||||
i8259_cnt++;
|
||||
i8259_cnt++;
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue