PDP10, PDP11, VAX: Make DMC/DMR initialization more accurate.
These changes cure a number of issues in RSTS/E, which is more sensitive to details of emulation than most: 1. Additional KMC opcodes supported for ROMI 2. MCLR now initializes the CSRs per the spec 3. MCLR and ROMI are processed immediately at CSR write rather than being deferred, because these actions are implemented in the device hardware rather than in the microprogram.
This commit is contained in:
Paul Koning
parent
f48d1f418d
commit
223f080724
1 changed files with 201 additions and 44 deletions
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@ -247,12 +247,15 @@ extern int32 tmr_poll; /* instructions per tick
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#define DMC_SEL6_M_HDX 0x0400
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#define DMC_SEL6_V_LONGSTRT 11
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#define DMC_SEL6_M_LONGSTRT 0x0800
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/* Bit flags used in DMR modem status after RDI */
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#define DMC_SEL6_V_LMODEM 11
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#define DMC_SEL6_M_LMODEM 0x0800
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#define DSPDSR 0x22b3 /* KMC opcode to move line unit status to SEL2 */
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#define DROPDTR 0xa40b /* KMC opcode to drop DTR */
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#define UINST_CNF 0x2296 /* KMC opcode to get config switches */
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#define UINST_RROM 0x814d /* KMC opcode to read DMC ROM */
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#define UINST_CNF3 0x2293 /* KMC opcode ditto but to BSEL3 */
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#define UINST_RROM 0x8100 /* KMC opcode to read DMC ROM, address in low bits */
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#define SEL2_TYPEO_BIT 0
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#define SEL2_RDO_BIT 7
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@ -291,6 +294,140 @@ typedef enum {
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OutputControl
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} TransferState;
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/* 129 words taken from RSTS/E ECO checker listing; the rest is not
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used so we can leave it as zeroes. */
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static const uint16 hi_speed_ucode[256] = {
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063220,
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063223,
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063237,
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063232,
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061200,
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061202,
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03370,
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063130,
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076423,
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063060,
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0101414,
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0100407,
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03401,
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063231,
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010162,
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0626,
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062234,
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016403,
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016402,
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016406,
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016407,
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016401,
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010210,
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016455,
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016472,
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010067,
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016471,
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02471,
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043236,
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010022,
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016424,
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02424,
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043235,
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010240,
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016642,
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02642,
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0600,
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061221,
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0110642,
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020620,
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0173202,
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020640,
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0167203,
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010210,
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0140620,
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020620,
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0103060,
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0100463,
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0433,
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060342,
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0101047,
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0123620,
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0113246,
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023240,
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060520,
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0103451,
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010211,
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0140620,
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060601,
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0103100,
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0123400,
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01620,
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0117034,
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0100447,
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02611,
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0100447,
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0123400,
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0103505,
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0114434,
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060520,
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0103603,
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0120400,
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01620,
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0103047,
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02514,
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0100447,
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0123400,
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0102527,
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02654,
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0102124,
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01620,
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02722,
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0102524,
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02701,
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060601,
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0102130,
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0100447,
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0102140,
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02472,
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0500,
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061260,
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010177,
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016402,
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02400,
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042233,
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0114474,
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060721,
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0102130,
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02472,
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010017,
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0136500,
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0136520,
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0122560,
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0123000,
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0500,
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061260,
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02133,
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040620,
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0103164,
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010151,
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016406,
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02700,
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063161,
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0641,
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03374,
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0110727,
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03004,
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063070,
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010017,
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0731,
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0110463,
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010154,
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057310,
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057231,
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057235,
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043237,
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043232,
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063170,
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063161
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};
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/* Queue elements
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* A queue is a double-linked list of element headers.
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* The head of the queue is an element without a body.
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@ -946,6 +1083,7 @@ void dmc_set_count (CTLR *controller, uint16 count);
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uint8 dmc_get_modem (CTLR *controller);
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void dmc_set_modem_dtr (CTLR *controller);
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void dmc_clr_modem_dtr (CTLR *controller);
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void dmc_process_immediate(CTLR *controller);
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void dmc_process_command (CTLR *controller);
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t_bool dmc_buffer_fill_receive_buffers (CTLR *controller);
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void dmc_start_transfer_buffer (CTLR *controller);
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@ -2201,8 +2339,12 @@ void dmc_set_rdyi(CTLR *controller)
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{
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if (dmc_is_dmc(controller)) {
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dmc_setreg(controller, 0, *controller->csrs->sel0 | DMC_SEL0_M_RDI, DBG_RGC);
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dmc_setreg(controller, 4, *controller->modem | 0x0800, DBG_RGC);
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dmc_setreg(controller, 6, *controller->modem & DMC_SEL4_M_DTR, DBG_RGC);
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if (controller->dev_type == DMR) {
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dmc_setreg(controller, 4, *controller->modem | 0x0800, DBG_RGC);
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dmc_setreg(controller, 6,
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(*controller->modem & DMC_SEL4_M_DTR) | DMC_SEL6_M_LMODEM,
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DBG_RGC);
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}
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}
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else
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dmc_setreg(controller, 2, *controller->csrs->sel2 | DMP_SEL2_M_RDI, DBG_RGC);
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@ -2301,7 +2443,8 @@ dmc_setreg(controller, 6, *controller->csrs->sel6 | DMC_SEL6_M_LOSTDATA, DBG_RGC
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void dmc_clear_master_clear(CTLR *controller)
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{
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dmc_setreg(controller, 0, *controller->csrs->sel0 & ~DMC_SEL0_M_MCLEAR, DBG_RGC);
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dmc_setreg(controller, 0,
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*controller->csrs->sel0 & ~(DMC_SEL0_M_MCLEAR|DMC_SEL0_M_STEPUP|DMC_SEL0_M_ROMI|DMC_SEL0_M_ROMO|DMC_SEL0_M_LU_LOOP|DMC_SEL0_M_STEPLU), DBG_RGC);
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}
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void dmc_set_run(CTLR *controller)
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@ -2339,7 +2482,6 @@ while ((control = controller->control_out)) {
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free (control);
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}
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controller->control_out = NULL;
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dmc_setreg(controller, 0, 0, DBG_RGC);
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if (controller->dev_type == DMR) {
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if (dmc_is_attached(controller->unit)) {
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/* Indicates microdiagnostics complete */
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@ -2354,19 +2496,10 @@ if (controller->dev_type == DMR) {
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dmc_setreg(controller, 2, 0x0200, DBG_RGC);
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}
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}
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else {
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/* preserve contents of BSEL3 if DMC-11 */
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dmc_setreg(controller, 2, *controller->csrs->sel2 & 0xFF00, DBG_RGC);
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}
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if (controller->dev_type == DMP)
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if (controller->dev_type == DMP) {
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dmc_setreg(controller, 4, 077, DBG_RGC);
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else
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dmc_setreg(controller, 4, 0, DBG_RGC);
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if (controller->dev_type == DMP)
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dmc_setreg(controller, 6, 0305, DBG_RGC);
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else
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dmc_setreg(controller, 6, 0, DBG_RGC);
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}
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dmc_buffer_queue_init_all(controller);
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controller->transfer_state = Idle;
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@ -3483,12 +3616,58 @@ while (buffer) {
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}
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}
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void dmc_process_command(CTLR *controller)
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void dmc_check_romi(CTLR *controller)
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{
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if (dmc_is_dmc (controller) &&
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(*controller->csrs->sel0 & DMC_SEL0_M_ROMI) &&
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(*controller->csrs->sel0 & (DMC_SEL0_M_STEPUP | DMC_SEL0_M_RUN))) {
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/* DMC-11 or DMR-11, with ROMI and either STEP or RUN bits set. */
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switch (*controller->csrs->sel6) {
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case DSPDSR: /* 0x22b3 (read line status instruction), set the DSR and high speed bits in SEL2. */
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sim_debug(DBG_TRC, controller->device, "%s%d: dmc_check_romi(). report DSR\n", controller->device->name, controller->index);
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dmc_setreg (controller, 2, 0xa00, DBG_RGC);
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break;
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case DROPDTR: /* 0xa40b (drop DTR instruction) - VMS Driver uses this */
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sim_debug(DBG_TRC, controller->device, "%s%d: dmc_check_romi(). drop_DTR\n", controller->device->name, controller->index);
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dmc_clr_modem_dtr (controller);
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break;
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case UINST_CNF3: /* 0x2293 (config switches to BSEL3) RSTS uses this */
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sim_debug(DBG_TRC, controller->device, "%s%d: dmc_check_romi(). report config\n", controller->device->name, controller->index);
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dmc_setreg (controller, 2, 0x0600, DBG_RGC); /* 1 Mb, DMR */
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break;
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case UINST_CNF: /* 0x2296 (get configuration switches) - VMS Driver uses this */
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sim_debug(DBG_TRC, controller->device, "%s%d: dmc_check_romi(). report config\n", controller->device->name, controller->index);
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dmc_setreg (controller, 6, 0x0006, DBG_RGC); /* 1 Mb, DMR */
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break;
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default:
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if ((*controller->csrs->sel6 & 0xff00) == UINST_RROM) {
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/* Read ROM: VMS and RSTS do this */
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sim_debug(DBG_TRC, controller->device, "%s%d: dmc_check_romi(). read rom[0x%02x]\n", controller->device->name, controller->index, *controller->csrs->sel6 & 0xff);
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dmc_setreg (controller, 6,
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hi_speed_ucode[*controller->csrs->sel6 & 0xff],
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DBG_RGC);
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}
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else
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sim_debug(DBG_WRN, controller->device, "%s%d: dmc_check_romi(). Unknown Microcode instruction 0x%04x\n", controller->device->name, controller->index, *controller->csrs->sel6);
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break;
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}
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/* If it was a STEP we do this only once. */
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*controller->csrs->sel0 &= ~DMC_SEL0_M_STEPUP;
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controller->transfer_state = Idle;
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}
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}
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void dmc_process_immediate(CTLR *controller)
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{
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if (dmc_is_master_clear_set(controller)) {
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dmc_process_master_clear(controller);
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return;
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}
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dmc_check_romi(controller); /* Do any needed immediate actions */
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}
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void dmc_process_command(CTLR *controller)
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{
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if (controller->transfer_state == InputTransfer) {
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dmc_process_input_transfer_completion(controller);
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return;
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@ -3506,32 +3685,8 @@ if (dmc_is_rqi_set(controller)) {
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dmc_start_input_transfer(controller);
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return;
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}
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if (dmc_is_dmc (controller) &&
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(*controller->csrs->sel0 & DMC_SEL0_M_ROMI) &&
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(!dmc_is_run_set(controller)) &&
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(*controller->csrs->sel0 & DMC_SEL0_M_STEPUP)) {
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/* DMC-11 or DMR-11, with RUN off and step and ROMI bits set. */
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switch (*controller->csrs->sel6) {
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case DSPDSR: /* 0x22b3 (read line status instruction), set the DTR bit in SEL2. */
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dmc_setreg (controller, 2, 0x800, DBG_RGC);
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break;
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case DROPDTR: /* 0xa40b (drop DTR instruction) - VMS Driver uses this */
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dmc_clr_modem_dtr (controller);
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break;
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case UINST_CNF: /* 0x2296 (get configuration switches) - VMS Driver uses this */
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dmc_setreg (controller, 6, 0x0006, DBG_RGC);
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break;
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case UINST_RROM:/* 0x814d (read DMC ROM) - VMS Driver uses this */
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dmc_setreg (controller, 6, 0x0391, DBG_RGC); /* Not Low Speed uCode value (0x390) */
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break;
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default:
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sim_debug(DBG_WRN, controller->device, "%s%d: dmc_process_command(). Unknown Microcode instruction 0x%04x", controller->device->name, controller->index, *controller->csrs->sel6);
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break;
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}
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*controller->csrs->sel0 &= ~DMC_SEL0_M_STEPUP;
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controller->transfer_state = Idle;
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}
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else {
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if (!dmc_is_dmc (controller) ||
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(*controller->csrs->sel0 & DMC_SEL0_M_ROMI) == 0) {
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if (dmc_is_run_set(controller)) {
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dmc_start_control_output_transfer(controller);
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dmc_start_transfer_buffer(controller);
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@ -3591,6 +3746,8 @@ else {
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dmc_setreg(controller, PA, (oldValue & ~mask) | (data & mask), DBG_REG);
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}
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if (dmc_getsel(reg) == 0) /* writes to SEL0 may need immediate action */
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dmc_process_immediate(controller); /* Do any needed immediate actions */
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if ((dmc_getsel(reg) == 0) || (dmc_getsel(reg) == 1)) {/* writes to SEL0 and SEL2 are actionable */
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if (0 == controller->dmc_wr_delay) { /* Not waiting? */
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controller->dmc_wr_delay = 10; /* Wait a bit before acting on the changed register */
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