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Merge branch 'DMC11' into SerialMux

Browse source 
Conflicts:
	scp.c
	sim_ether.c
	sim_ether.h
	sim_tmxr.c
This commit is contained in:
Mark Pizzolato 2012-10-16 15:50:38 -07:00
commit 24696892fd
158 changed files with 4488 additions and 1193 deletions
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26
0readme_39.txt
View file

@ -34,25 +34,25 @@ components and build network capable simulators if they are available.
1.1.4 PDP11 and VAX (Mark Pizzolato)
- Added DELQA-Plus device.
- added DELQA-Plus device
1.1.5 IA64 VMS Ethernet Support
- Identified compiler version issues and added IA64 support (Matt Burke)
- identified compiler version issues and added IA64 support (Matt Burke)
1.1.6 Visual Studio Projects (Mark Pizzolato)
2. Bugs Fixed
Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.
3. Status Report
This is the last release of SimH for which I will be sole editor. After this
This is the last release of SimH for which I will be lead editor. After this
release, the source is moving to a public repository:
https://github.com/markpizz/simh
under the general editorship of Dave Hittner and Mark Pizzolato. The status
of the individual simulators is as follows:
@ -168,10 +168,23 @@ Bill Beech
3.25 Sigma 32b
Incomplete; more work is needed on the peripherals for accuracy.
Included in the beta simulators package.
3.26 Alpha
Incomplete; essentially just an EV-5 (21164) chip emulator.
Incomplete; essentially just an EV-5 (21164) chip emulator. Included
in the beta simulators package.
3.27 SAGE
Incomplete. Included in the beta simulators package.
3.28 SC1
Internal simulator for SiCortex supercomputer; intended as an example
of implementing an SMP system in the current SimH structure. Included
in the beta simulators package.
4. Suggestions for Future Work
@ -198,4 +211,3 @@ Incomplete; essentially just an EV-5 (21164) chip emulator.
- Data General MV8000 (if a hobbyist license can be obtained for AOS)
- Alpha simulator
- HP 3000 (16b) simulator with MPE

6
0readme_ethernet.txt
View file

@ -156,9 +156,9 @@ Note 2: Root access will likely be needed to configure or start the vde
Note 3: Simulators running using VDE networking can run without root
privilege.
Linux (Ubuntu 10.04):
Linux (Ubuntu 11.10):
apt-get install make
apt-get install libvdeplug-dev
apt-get install libvdeplug2-dev
apt-get install vde2
vde_switch -s /tmp/switch1 -tap tap0 -m 666
@ -207,7 +207,7 @@ Building on Windows:
The contents of the windows-build directory can be downloaded from:
https://github.com/downloads/markpizz/simh/windows-build.zip
https://github.com/downloads/simh/simh/windows-build.zip
There are Windows batch files provided to initiate compiles using the MinGW

2
ALTAIR/altair_cpu.c
View file

@ -313,7 +313,7 @@ int32 sim_instr (void)
while (reason == 0) { /* loop until halted */
if (sim_interval <= 0) { /* check clock queue */
if (reason = sim_process_event ()) break;
if ((reason = sim_process_event ())) break;
}
if (int_req > 0) { /* interrupt? */

4
ALTAIR/altair_dsk.c
View file

@ -218,8 +218,8 @@ int32 dsk10(int32 io, int32 data)
cur_disk = data & 0x0F;
if (data & 0x80) {
cur_flags[cur_disk] = 0; /* Disable drive */
cur_sect[cur_disk = 0377];
cur_byte[cur_disk = 0377];
cur_sect[cur_disk] = 0377;
cur_byte[cur_disk] = 0377;
return (0);
}
cur_flags[cur_disk] = 0x1A; /* Enable: head move true */

23
AltairZ80/altairz80_net.c
View file

@ -150,36 +150,33 @@ static t_stat net_reset(DEVICE *dptr) {
}
static t_stat net_attach(UNIT *uptr, char *cptr) {
uint32 i, ipa, ipp;
t_stat r = get_ipaddr(cptr, &ipa, &ipp);
uint32 i;
char host[CBUFSIZE], port[CBUFSIZE];
t_stat r;
r = sim_parse_addr (cptr, host, sizeof(host), "localhost", port, sizeof(port), "3000");
if (r != SCPE_OK)
return SCPE_ARG;
if (ipa == 0)
ipa = 0x7F000001; /* localhost = 127.0.0.1 */
if (ipp == 0)
ipp = 3000;
net_unit.u3 = ipp;
net_unit.u4 = ipa;
net_reset(&net_dev);
for (i = 0; i <= MAX_CONNECTIONS; i++)
serviceDescriptor[i].ioSocket = 0;
if (net_unit.flags & UNIT_SERVER) {
net_unit.wait = NET_INIT_POLL_SERVER;
serviceDescriptor[1].masterSocket = sim_master_sock(ipp);
serviceDescriptor[1].masterSocket = sim_master_sock(cptr, NULL);
if (serviceDescriptor[1].masterSocket == INVALID_SOCKET)
return SCPE_IOERR;
}
else {
net_unit.wait = NET_INIT_POLL_CLIENT;
serviceDescriptor[0].ioSocket = sim_connect_sock(ipa, ipp);
serviceDescriptor[0].ioSocket = sim_connect_sock(cptr, "localhost", "3000");
if (serviceDescriptor[0].ioSocket == INVALID_SOCKET)
return SCPE_IOERR;
}
net_unit.flags |= UNIT_ATT;
net_unit.filename = (char *) calloc(CBUFSIZE, sizeof (char)); /* alloc name buf */
net_unit.filename = (char *) calloc(1, strlen(cptr)+1); /* alloc name buf */
if (net_unit.filename == NULL)
return SCPE_MEM;
strncpy(net_unit.filename, cptr, CBUFSIZE); /* save name */
strcpy(net_unit.filename, cptr); /* save name */
return SCPE_OK;
}
@ -216,7 +213,7 @@ static t_stat net_svc(UNIT *uptr) {
}
}
else if (serviceDescriptor[0].ioSocket == 0) {
serviceDescriptor[0].ioSocket = sim_connect_sock(net_unit.u4, net_unit.u3);
serviceDescriptor[0].ioSocket = sim_connect_sock(net_unit.filename, "localhost", "3000");
if (serviceDescriptor[0].ioSocket == INVALID_SOCKET)
return SCPE_IOERR;
printf("\rWaiting for server ... Type g<return> (possibly twice) when ready" NLP);

2
GRI/gri_cpu.c
View file

@ -421,7 +421,7 @@ ao_update (); /* update AO */
while (reason == 0) { /* loop until halted */
if (sim_interval <= 0) { /* check clock queue */
if (reason = sim_process_event ())
if ((reason = sim_process_event ()))
break;
}

46
H316/h316_cpu.c
View file

@ -424,7 +424,7 @@ reason = 0;
while (reason == 0) { /* loop until halted */
if (sim_interval <= 0) { /* check clock queue */
if (reason = sim_process_event ())
if ((reason = sim_process_event ()))
break;
}
@ -458,7 +458,7 @@ if (chan_req) { /* channel request? */
t = iotab[dev] (ioOTA, 0, Read (ad), dev); /* output word */
if ((t & IOT_SKIP) == 0)
return STOP_DMAER;
if (r = (t >> IOT_V_REASON))
if ((r = (t >> IOT_V_REASON)))
return r;
}
if (Q_DMA (i)) { /* DMA? */
@ -528,7 +528,7 @@ if (hst_lnt) { /* instr hist? */
switch (I_GETOP (MB)) { /* case on <1:6> */
case 001: case 021: case 041: case 061: /* JMP */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
PCQ_ENTRY; /* save PC */
PC = NEWA (PC, Y); /* set new PC */
@ -537,7 +537,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 002: case 022: case 042: case 062: /* LDA */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
if (dp) { /* double prec? */
AR = Read (Y & ~1); /* get doubleword */
@ -548,13 +548,13 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 003: case 023: case 043: case 063: /* ANA */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
AR = AR & Read (Y);
break;
case 004: case 024: case 044: case 064: /* STA */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
Write (Y, AR); /* store A */
if (dp) { /* double prec? */
@ -564,13 +564,13 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 005: case 025: case 045: case 065: /* ERA */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
AR = AR ^ Read (Y);
break;
case 006: case 026: case 046: case 066: /* ADD */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
if (dp) { /* double prec? */
t1 = GETDBL_S (AR, BR); /* get A'B */
@ -583,7 +583,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 007: case 027: case 047: case 067: /* SUB */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
if (dp) { /* double prec? */
t1 = GETDBL_S (AR, BR); /* get A'B */
@ -596,7 +596,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 010: case 030: case 050: case 070: /* JST */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
MB = NEWA (Read (Y), PC); /* merge old PC */
Write (Y, MB);
@ -605,7 +605,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 011: case 031: case 051: case 071: /* CAS */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
MB = Read (Y);
if (AR == MB)
@ -615,7 +615,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 012: case 032: case 052: case 072: /* IRS */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
MB = (Read (Y) + 1) & DMASK; /* incr, rewrite */
Write (Y, MB);
@ -624,7 +624,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 013: case 033: case 053: case 073: /* IMA */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
MB = Read (Y);
Write (Y, AR); /* A to mem */
@ -632,13 +632,13 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 015: case 055: /* STX */
if (reason = Ea (MB & ~IDX, &Y)) /* eff addr */
if ((reason = Ea (MB & ~IDX, &Y))) /* eff addr */
break;
Write (Y, XR); /* store XR */
break;
case 035: case 075: /* LDX */
if (reason = Ea (MB & ~IDX, &Y)) /* eff addr */
if ((reason = Ea (MB & ~IDX, &Y))) /* eff addr */
break;
XR = Read (Y); /* load XR */
M[M_XR] = XR; /* update mem too */
@ -646,7 +646,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
case 016: case 036: case 056: case 076: /* MPY */
if (cpu_unit.flags & UNIT_HSA) { /* installed? */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
t1 = SEXT (AR) * SEXT (Read (Y));
PUTDBL_Z (t1);
@ -657,7 +657,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
case 017: case 037: case 057: case 077: /* DIV */
if (cpu_unit.flags & UNIT_HSA) { /* installed? */
if (reason = Ea (MB, &Y)) /* eff addr */
if ((reason = Ea (MB, &Y))) /* eff addr */
break;
t2 = SEXT (Read (Y)); /* divr */
if (t2) { /* divr != 0? */
@ -826,7 +826,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 003: /* "long right arot" */
if (reason = stop_inst) /* stop on undef? */
if ((reason = stop_inst)) /* stop on undef? */
break;
for (t2 = 0; t2 < t1; t2++) { /* bit by bit */
C = BR & 1; /* C = last out */
@ -859,7 +859,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 007: /* "short right arot" */
if (reason = stop_inst) /* stop on undef? */
if ((reason = stop_inst)) /* stop on undef? */
break;
for (t2 = 0; t2 < t1; t2++) { /* bit by bit */
C = AR & 1; /* C = last out */
@ -899,7 +899,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 013: /* "long left arot" */
if (reason = stop_inst) /* stop on undef? */
if ((reason = stop_inst)) /* stop on undef? */
break;
for (t2 = 0; t2 < t1; t2++) { /* bit by bit */
AR = (AR << 1) | ((BR >> 14) & 1);
@ -935,7 +935,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
break;
case 017: /* "short left arot" */
if (reason = stop_inst) /* stop on undef? */
if ((reason = stop_inst)) /* stop on undef? */
break;
for (t2 = 0; t2 < t1; t2++) { /* bit by bit */
if ((AR & SIGN) != ((AR << 1) & SIGN)) C = 1;
@ -1003,7 +1003,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
AR = (AR << 8) & DMASK;
else if (MB == 0141340) /* ICA */
AR = ((AR << 8) | (AR >> 8)) & DMASK;
else if (reason = stop_inst)
else if ((reason = stop_inst))
break;
else AR = Operate (MB, AR); /* undefined */
break;
@ -1500,7 +1500,7 @@ for (i = 0; i < DEV_MAX; i++)
iotab[i] = NULL;
for (i = 0; i < (DMA_MAX + DMC_MAX); i++)
chan_map[i] = 0;
for (i = 0; dptr = sim_devices[i]; i++) { /* loop thru devices */
for (i = 0; (dptr = sim_devices[i]); i++) { /* loop thru devices */
dibp = (DIB *) dptr->ctxt; /* get DIB */
if ((dibp == NULL) || (dptr->flags & DEV_DIS)) /* exist, enabled? */
continue;

12
H316/h316_dp.c
View file

@ -617,7 +617,7 @@ switch (uptr->FNC) { /* case on function */
case FNC_RCA: /* read current addr */
if (h >= dp_tab[dp_ctype].surf) /* invalid head? */
return dp_done (1, STA_ADRER); /* error */
if (r = dp_rdtrk (uptr, dpxb, uptr->CYL, h)) /* get track; error? */
if ((r = dp_rdtrk (uptr, dpxb, uptr->CYL, h))) /* get track; error? */
return r;
dp_rptr = 0; /* init rec ptr */
if (dpxb[dp_rptr + REC_LNT] == 0) /* unformated? */
@ -722,7 +722,7 @@ switch (uptr->FNC) { /* case on function */
case FNC_RW: /* read/write */
if (h >= dp_tab[dp_ctype].surf) /* invalid head? */
return dp_done (1, STA_ADRER); /* error */
if (r = dp_rdtrk (uptr, dpxb, uptr->CYL, h)) /* get track; error? */
if ((r = dp_rdtrk (uptr, dpxb, uptr->CYL, h))) /* get track; error? */
return r;
if (!dp_findrec (dp_cw2)) /* find rec; error? */
return dp_done (1, STA_ADRER); /* address error */
@ -750,7 +750,7 @@ switch (uptr->FNC) { /* case on function */
if (dp_cw1 & CW1_RW) { /* write? */
if (dp_sta & STA_RDY) /* timing failure? */
return dp_wrdone (uptr, STA_DTRER); /* yes, error */
if (r = dp_wrwd (uptr, dp_buf)) /* wr word, error? */
if ((r = dp_wrwd (uptr, dp_buf))) /* wr word, error? */
return r;
if (dp_eor) { /* transfer done? */
dpxb[dp_rptr + REC_DATA + dp_wptr] = dp_csum;
@ -855,7 +855,7 @@ if (dp_wptr < (lnt + REC_MAXEXT)) {
}
dpxb[dp_rptr + REC_DATA + dp_wptr] = dp_csum; /* write csum */
dpxb[dp_rptr + lnt + REC_OVHD] = 0; /* zap rest of track */
if (r = dp_wrdone (uptr, STA_UNSER)) /* dump track */
if ((r = dp_wrdone (uptr, STA_UNSER))) /* dump track */
return r;
return STOP_DPOVR;
}
@ -1017,7 +1017,7 @@ for (c = cntr = 0; c < dp_tab[dp_ctype].cyl; c++) {
else tbuf[rptr + REC_ADDR] = (c << 8) + (h << 3) + i;
rptr = rptr + nw + REC_OVHD;
}
if (r = dp_wrtrk (uptr, tbuf, c, h))
if ((r = dp_wrtrk (uptr, tbuf, c, h)))
return r;
}
}
@ -1043,7 +1043,7 @@ if ((uptr->flags & UNIT_ATT) == 0)
return SCPE_UNATT;
for (c = 0; c < dp_tab[dp_ctype].cyl; c++) {
for (h = 0; h < dp_tab[dp_ctype].surf; h++) {
if (r = dp_rdtrk (uptr, tbuf, c, h))
if ((r = dp_rdtrk (uptr, tbuf, c, h)))
return r;
rptr = 0;
rlnt = tbuf[rptr + REC_LNT];

8
H316/h316_mt.c
View file

@ -371,17 +371,17 @@ switch (uptr->FNC) { /* case on function */
return SCPE_OK;
case FNC_WEOF: /* write file mark */
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
r = mt_map_err (uptr, st); /* map error */
break; /* sched end motion */
case FNC_FSR: /* space fwd rec */
if (st = sim_tape_sprecf (uptr, &tbc)) /* space fwd, err? */
if ((st = sim_tape_sprecf (uptr, &tbc))) /* space fwd, err? */
r = mt_map_err (uptr, st); /* map error */
break; /* sched end motion */
case FNC_BSR: /* space rev rec */
if (st = sim_tape_sprecr (uptr, &tbc)) /* space rev, err? */
if ((st = sim_tape_sprecr (uptr, &tbc))) /* space rev, err? */
r = mt_map_err (uptr, st); /* map error */
break; /* sched end motion */
@ -455,7 +455,7 @@ switch (uptr->FNC) { /* case on function */
mt_wrwd (uptr, mt_buf);
else mt_rdy = 0; /* rdy must be clr */
if (mt_ptr) { /* any data? */
if (st = sim_tape_wrrecf (uptr, mtxb, mt_ptr)) /* write, err? */
if ((st = sim_tape_wrrecf (uptr, mtxb, mt_ptr)))/* write, err? */
r = mt_map_err (uptr, st); /* map error */
}
break; /* sched end motion */

2
H316/h316_stddev.c
View file

@ -390,7 +390,7 @@ t_stat r;
if (!(uptr->flags & UNIT_ATTABLE))
return SCPE_NOFNC;
if (r = attach_unit (uptr, cptr))
if ((r = attach_unit (uptr, cptr)))
return r;
if (sim_switches & SWMASK ('A')) /* -a? ASCII */
uptr->flags |= UNIT_ASC;

4
H316/h316_sys.c
View file

@ -364,11 +364,11 @@ switch (j) { /* case on class */
case I_V_MRF: case I_V_MRX: /* mem ref */
cptr = get_glyph (cptr, gbuf, ','); /* get next field */
if (k = (strcmp (gbuf, "C") == 0)) { /* C specified? */
if ((k = (strcmp (gbuf, "C") == 0))) { /* C specified? */
val[0] = val[0] | SC;
cptr = get_glyph (cptr, gbuf, 0);
}
else if (k = (strcmp (gbuf, "Z") == 0)) { /* Z specified? */
else if ((k = (strcmp (gbuf, "Z") == 0))) { /* Z specified? */
cptr = get_glyph (cptr, gbuf, ',');
}
d = get_uint (gbuf, 8, X_AMASK, &r); /* construe as addr */

28
HP2100/hp2100_bugfixes.txt
View file

@ -1,6 +1,6 @@
HP 2100 SIMULATOR BUG FIX WRITEUPS
==================================
Last update: 2012-03-25
Last update: 2012-05-07
1. PROBLEM: Booting from magnetic tape reports "HALT instruction, P: 77756
@ -6280,3 +6280,29 @@
(hp2100_mt.c).
STATUS: Fixed in version 3.9-0.
247. PROBLEM: The ICD disc read end-of-track delay is not optimal.
VERSION: 3.9-0
OBSERVATION: To avoid End of Cylinder errors when reading the last sector
of a track, the ICD controller must delay more than the usual intersector
time to allow the OS driver to send an Untalk if a read is to be
terminated. Currently, the longer delay is used if an end-of-cylinder
condition is present. However, the delay is needed only if the resulting
seek attempt would cause an error if the read is continued; the normal
delay should be used if the seek is permitted and would succeed.
Also, if the host does send an Untalk during this time, the longer delay
should be cancelled, and command termination should be scheduled for
immediate processing.
CAUSE: Suboptimal implementation.
RESOLUTION: Modify "end_read" (hp_disclib.c) to use the longer time only
if the seek would fail, and modify "complete_read" (hp2100_di_da.c) to
cancel the intersector delay and schedule the completion phase immediately.
STATUS: Patches prepared 2012-05-07.

22
HP2100/hp2100_cpu.c
View file

@ -29,6 +29,7 @@
DMA1,DMA2 12607B/12578A/12895A direct memory access controller
DCPC1,DCPC2 12897B dual channel port controller
09-May-12 JDB Separated assignments from conditional expressions
13-Jan-12 JDB Minor speedup in "is_mapped"
Added casts to cpu_mod, dmasio, dmapio, cpu_reset, dma_reset
07-Apr-11 JDB Fixed I/O return status bug for DMA cycles
@ -1054,7 +1055,8 @@ for (i = OPTDEV; i <= MAXDEV; i++) /* default optional devi
dtab [PWR] = &pwrf_dib; /* for now, powerfail is always present */
for (i = 0; dptr = sim_devices [i]; i++) { /* loop thru dev */
for (i = 0; sim_devices [i] != NULL; i++) { /* loop thru dev */
dptr = sim_devices [i];
dibptr = (DIB *) dptr->ctxt; /* get DIB */
if (dibptr && !(dptr->flags & DEV_DIS)) { /* handler exists and device is enabled? */
@ -3609,30 +3611,32 @@ DEVICE *dptr;
DIB *dibptr;
uint32 i, j, k;
t_bool is_conflict = FALSE;
uint32 conflicts[MAXDEV + 1] = { 0 };
uint32 conflicts [MAXDEV + 1] = { 0 };
for (i = 0; dptr = sim_devices[i]; i++) {
for (i = 0; sim_devices [i] != NULL; i++) {
dptr = sim_devices [i];
dibptr = (DIB *) dptr->ctxt;
if (dibptr && !(dptr->flags & DEV_DIS))
if (++conflicts[dibptr->select_code] > 1)
if (++conflicts [dibptr->select_code] > 1)
is_conflict = TRUE;
}
if (is_conflict) {
sim_ttcmd();
for (i = 0; i <= MAXDEV; i++) {
if (conflicts[i] > 1) {
k = conflicts[i];
if (conflicts [i] > 1) {
k = conflicts [i];
printf ("Select code %o conflict:", i);
if (sim_log)
fprintf (sim_log, "Select code %o conflict:", i);
for (j = 0; dptr = sim_devices[j]; j++) {
for (j = 0; sim_devices [j] != NULL; j++) {
dptr = sim_devices [j];
dibptr = (DIB *) dptr->ctxt;
if (dibptr && !(dptr->flags & DEV_DIS) && (i == dibptr->select_code)) {
if (k < conflicts[i]) {
if (dibptr && !(dptr->flags & DEV_DIS) && i == dibptr->select_code) {
if (k < conflicts [i]) {
printf (" and");
if (sim_log)

47
HP2100/hp2100_cpu0.c
View file

@ -1,6 +1,6 @@
/* hp2100_cpu0.c: HP 1000 user microcode and unimplemented instruction set stubs
Copyright (c) 2006-2010, J. David Bryan
Copyright (c) 2006-2012, J. David Bryan
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
CPU0 User microcode and unimplemented firmware options
09-May-12 JDB Separated assignments from conditional expressions
04-Nov-10 JDB Removed DS note regarding PIF card (is now implemented)
18-Sep-08 JDB .FLUN and self-tests for VIS and SIGNAL are NOP if not present
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
@ -129,9 +130,11 @@ uint32 entry;
entry = IR & 017; /* mask to entry point */
if (op_ds[entry] != OP_N)
if (reason = cpu_ops (op_ds[entry], op, intrq)) /* get instruction operands */
return reason;
if (op_ds [entry] != OP_N) {
reason = cpu_ops (op_ds[entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* did the evaluation fail? */
return reason; /* return the reason for failure */
}
switch (entry) { /* decode IR<3:0> */
@ -191,23 +194,23 @@ switch (IR) {
switch ((IR >> 4) & 037) { /* decode IR<8:4> */
/* case 000: /* 105000-105017 */
/* return cpu_user_00 (IR, intrq); /* uncomment to handle instruction */
/* case 000: ** 105000-105017 */
/* return cpu_user_00 (IR, intrq); ** uncomment to handle instruction */
/* case 001: /* 105020-105037 */
/* return cpu_user_01 (IR, intrq); /* uncomment to handle instruction */
/* case 001: ** 105020-105037 */
/* return cpu_user_01 (IR, intrq); ** uncomment to handle instruction */
/* case 0nn: /* other cases as needed */
/* return cpu_user_nn (IR, intrq); /* uncomment to handle instruction */
/* case 0nn: ** other cases as needed */
/* return cpu_user_nn (IR, intrq); ** uncomment to handle instruction */
case 020: /* 10x400-10x417 */
return cpu_user_20 (IR, intrq); /* call sample dispatcher */
/* case 021: /* 10x420-10x437 */
/* return cpu_user_21 (IR, intrq); /* uncomment to handle instruction */
/* case 021: ** 10x420-10x437 */
/* return cpu_user_21 (IR, intrq); ** uncomment to handle instruction */
/* case 0nn: /* other cases as needed */
/* return cpu_user_nn (IR, intrq); /* uncomment to handle instruction */
/* case 0nn: ** other cases as needed */
/* return cpu_user_nn (IR, intrq); ** uncomment to handle instruction */
default: /* others undefined */
reason = stop_inst;
@ -243,20 +246,22 @@ uint32 entry;
entry = IR & 017; /* mask to entry point */
if (op_user_20 [entry] != OP_N)
if (reason = cpu_ops (op_user_20 [entry], op, intrq)) /* get instruction operands */
return reason;
if (op_user_20 [entry] != OP_N) {
reason = cpu_ops (op_user_20 [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* did the evaluation fail? */
return reason; /* return the reason for failure */
}
switch (entry) { /* decode IR<4:0> */
case 000: /* 10x400 */
/* break; /* uncomment to handle instruction */
/* break; ** uncomment to handle instruction */
case 001: /* 10x401 */
/* break; /* uncomment to handle instruction */
/* break; ** uncomment to handle instruction */
/* case 0nn: /* other cases as needed */
/* break; /* uncomment to handle instruction */
/* case 0nn: ** other cases as needed */
/* break; ** uncomment to handle instruction */
default: /* others undefined */
reason = stop_inst;

30
HP2100/hp2100_cpu1.c
View file

@ -1,6 +1,6 @@
/* hp2100_cpu1.c: HP 2100/1000 EAU simulator and UIG dispatcher
Copyright (c) 2005-2008, Robert M. Supnik
Copyright (c) 2005-2012, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
CPU1 Extended arithmetic and optional microcode dispatchers
09-May-12 JDB Separated assignments from conditional expressions
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
05-Sep-08 JDB Moved option-present tests to UIG dispatchers
Call "user microcode" dispatcher for unclaimed UIG instructions
@ -245,14 +246,15 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */
case 010: /* MPY 100200 (OP_K) */
MPY:
if (reason = cpu_ops (OP_K, op, intrq)) /* get operand */
break;
reason = cpu_ops (OP_K, op, intrq); /* get operand */
if (reason == SCPE_OK) { /* successful eval? */
sop1 = SEXT (AR); /* sext AR */
sop2 = SEXT (op[0].word); /* sext mem */
sop1 = sop1 * sop2; /* signed mpy */
BR = (sop1 >> 16) & DMASK; /* to BR'AR */
AR = sop1 & DMASK;
O = 0; /* no overflow */
}
break;
default: /* others undefined */
@ -262,9 +264,11 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */
break;
case 0201: /* DIV 100400 (OP_K) */
if (reason = cpu_ops (OP_K, op, intrq)) /* get operand */
reason = cpu_ops (OP_K, op, intrq); /* get operand */
if (reason != SCPE_OK) /* eval failed? */
break;
if (rs = qs = BR & SIGN) { /* save divd sign, neg? */
rs = qs = BR & SIGN; /* save divd sign */
if (rs) { /* neg? */
AR = (~AR + 1) & DMASK; /* make B'A pos */
BR = (~BR + (AR == 0)) & DMASK; /* make divd pos */
}
@ -317,17 +321,19 @@ switch ((IR >> 8) & 0377) { /* decode IR<15:8> */
break;
case 0210: /* DLD 104200 (OP_D) */
if (reason = cpu_ops (OP_D, op, intrq)) /* get operand */
break;
reason = cpu_ops (OP_D, op, intrq); /* get operand */
if (reason == SCPE_OK) { /* successful eval? */
AR = (op[0].dword >> 16) & DMASK; /* load AR */
BR = op[0].dword & DMASK; /* load BR */
}
break;
case 0211: /* DST 104400 (OP_A) */
if (reason = cpu_ops (OP_A, op, intrq)) /* get operand */
break;
reason = cpu_ops (OP_A, op, intrq); /* get operand */
if (reason == SCPE_OK) { /* successful eval? */
WriteW (op[0].word, AR); /* store AR */
WriteW ((op[0].word + 1) & VAMASK, BR); /* store BR */
}
break;
default: /* should never get here */
@ -733,9 +739,11 @@ uint32 i, MA;
for (i = 0; i < OP_N_F; i++) {
flags = pattern & OP_M_FLAGS; /* get operand pattern */
if (flags >= OP_ADR) /* address operand? */
if (reason = resolve (ReadW (PC), &MA, irq)) /* resolve indirects */
if (flags >= OP_ADR) { /* address operand? */
reason = resolve (ReadW (PC), &MA, irq); /* resolve indirects */
if (reason != SCPE_OK) /* resolution failed? */
return reason;
}
switch (flags) {
case OP_NUL: /* null operand */

30
HP2100/hp2100_cpu2.c
View file

@ -1,6 +1,6 @@
/* hp2100_cpu2.c: HP 2100/1000 FP/DMS/EIG/IOP instructions
Copyright (c) 2005-2008, Robert M. Supnik
Copyright (c) 2005-2012, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -26,6 +26,7 @@
CPU2 Floating-point, dynamic mapping, extended, and I/O processor
instructions
09-May-12 JDB Separated assignments from conditional expressions
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
05-Aug-08 JDB Updated mp_dms_jmp calling sequence
@ -243,9 +244,12 @@ uint32 i, t, mapi, mapj;
absel = (IR & I_AB)? 1: 0; /* get A/B select */
entry = IR & 037; /* mask to entry point */
if (op_dms[entry] != OP_N)
if (reason = cpu_ops (op_dms[entry], op, intrq)) /* get instruction operands */
return reason;
if (op_dms [entry] != OP_N) {
reason = cpu_ops (op_dms [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<3:0> */
@ -609,9 +613,12 @@ int32 sop1, sop2;
absel = (IR & I_AB)? 1: 0; /* get A/B select */
entry = IR & 037; /* mask to entry point */
if (op_eig[entry] != OP_N)
if (reason = cpu_ops (op_eig[entry], op, intrq)) /* get instruction operands */
return reason;
if (op_eig [entry] != OP_N) {
reason = cpu_ops (op_eig [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<4:0> */
@ -988,9 +995,12 @@ else if (entry <= 057) /* IR = 10x440-457? */
entry = entry - 060; /* offset 10x460-477 */
if (op_iop[entry] != OP_N)
if (reason = cpu_ops (op_iop[entry], op, intrq)) /* get instruction operands */
return reason;
if (op_iop [entry] != OP_N) {
reason = cpu_ops (op_iop [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<5:0> */

36
HP2100/hp2100_cpu3.c
View file

@ -25,6 +25,7 @@
CPU3 Fast FORTRAN and Double Integer instructions
09-May-12 JDB Separated assignments from conditional expressions
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
05-Aug-08 JDB Updated mp_dms_jmp calling sequence
@ -185,17 +186,23 @@ int32 i;
entry = IR & 037; /* mask to entry point */
if (UNIT_CPU_MODEL != UNIT_1000_F) { /* 2100/M/E-Series? */
if (op_ffp_e[entry] != OP_N)
if (reason = cpu_ops (op_ffp_e[entry], op, intrq)) /* get instruction operands */
return reason;
if (op_ffp_e [entry] != OP_N) {
reason = cpu_ops (op_ffp_e [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
}
#if defined (HAVE_INT64) /* int64 support available */
else { /* F-Series */
if (op_ffp_f[entry] != OP_N)
if (reason = cpu_ops (op_ffp_f[entry], op, intrq)) /* get instruction operands */
return reason;
if (op_ffp_f [entry] != OP_N) {
reason = cpu_ops (op_ffp_f [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<4:0> */
@ -417,7 +424,8 @@ switch (entry) { /* decode IR<4:0> */
sa = op[0].word - 1;
da = ReadW (sa); /* get jump target */
if (reason = resolve (da, &MA, intrq)) { /* resolve indirects */
reason = resolve (da, &MA, intrq); /* resolve indirects */
if (reason != SCPE_OK) { /* resolution failed? */
PC = err_PC; /* irq restarts instruction */
break;
}
@ -435,7 +443,8 @@ switch (entry) { /* decode IR<4:0> */
op[1].word = op[1].word + /* compute element offset */
(op[2].word - 1) * op[3].word;
else { /* 3-dim access */
if (reason = cpu_ops (OP_KK, op2, intrq)) { /* get 1st, 2nd ranges */
reason = cpu_ops (OP_KK, op2, intrq); /* get 1st, 2nd ranges */
if (reason != SCPE_OK) { /* evaluation failed? */
PC = err_PC; /* irq restarts instruction */
break;
}
@ -461,7 +470,8 @@ switch (entry) { /* decode IR<4:0> */
for (j = 0; j < sc; j++) {
MA = ReadW (sa++); /* get addr of actual */
if (reason = resolve (MA, &MA, intrq)) { /* resolve indirect */
reason = resolve (MA, &MA, intrq); /* resolve indirect */
if (reason != SCPE_OK) { /* resolution failed? */
PC = err_PC; /* irq restarts instruction */
break;
}
@ -643,9 +653,11 @@ t_stat reason = SCPE_OK;
entry = IR & 017; /* mask to entry point */
if (op_dbi[entry] != OP_N)
if (reason = cpu_ops (op_dbi[entry], op, intrq)) /* get instruction operands */
return reason;
if (op_dbi[entry] != OP_N) {
reason = cpu_ops (op_dbi [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<3:0> */

19
HP2100/hp2100_cpu4.c
View file

@ -25,6 +25,7 @@
CPU4 Floating Point Processor and Scientific Instruction Set
09-May-12 JDB Separated assignments from conditional expressions
06-Feb-12 JDB Added OPSIZE casts to fp_accum calls in .FPWR/.TPWR
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
@ -260,9 +261,12 @@ else
entry = opcode & 0177; /* map to <6:0> */
if (op_fpp[entry] != OP_N)
if (reason = cpu_ops (op_fpp[entry], op, intrq)) /* get instruction operands */
return reason;
if (op_fpp [entry] != OP_N) {
reason = cpu_ops (op_fpp [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<6:0> */
case 0000: /* FAD 105000 (OP_RF) */
@ -599,9 +603,12 @@ static const OP t_one = { { 0040000, 0000000, 0000000, 0000002 } }; /* DEY 1.
entry = IR & 017; /* mask to entry point */
if (op_sis[entry] != OP_N)
if (reason = cpu_ops (op_sis[entry], op, intrq)) /* get instruction operands */
return reason;
if (op_sis [entry] != OP_N) {
reason = cpu_ops (op_sis [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
switch (entry) { /* decode IR<3:0> */

17
HP2100/hp2100_cpu5.c
View file

@ -26,6 +26,7 @@
CPU5 RTE-6/VM and RTE-IV firmware option instructions
09-May-12 JDB Separated assignments from conditional expressions
23-Mar-12 JDB Added sign extension for dim count in "cpu_ema_resolve"
28-Dec-11 JDB Eliminated unused variable in "cpu_ema_vset"
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
@ -649,9 +650,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_VMA);
entry = IR & 017; /* mask to entry point */
pattern = op_vma[entry]; /* get operand pattern */
if (pattern != OP_N)
if (reason = cpu_ops (pattern, op, intrq)) /* get instruction operands */
return reason;
if (pattern != OP_N) {
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
if (debug) { /* debugging? */
fprintf (sim_deb, ">>CPU VMA: IR = %06o (", IR); /* print preamble and IR */
@ -1360,9 +1363,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_EMA);
entry = IR & 017; /* mask to entry point */
pattern = op_ema[entry]; /* get operand pattern */
if (pattern != OP_N)
if (reason = cpu_ops (pattern, op, intrq)) /* get instruction operands */
return reason;
if (pattern != OP_N) {
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
if (debug) { /* debugging? */
fprintf (sim_deb, ">>CPU EMA: PC = %06o, IR = %06o (", err_PC,IR); /* print preamble and IR */

20
HP2100/hp2100_cpu6.c
View file

@ -1,6 +1,6 @@
/* hp2100_cpu6.c: HP 1000 RTE-6/VM OS instructions
Copyright (c) 2006-2010, J. David Bryan
Copyright (c) 2006-2012, J. David Bryan
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
CPU6 RTE-6/VM OS instructions
09-May-12 JDB Separated assignments from conditional expressions
29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation
18-Sep-08 JDB Corrected .SIP debug formatting
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
@ -393,9 +394,12 @@ static t_bool tbg_tick = FALSE; /* set if processing TBG
entry = IR & 017; /* mask to entry point */
pattern = op_os[entry]; /* get operand pattern */
if (pattern != OP_N)
if (reason = cpu_ops (pattern, op, intrq)) /* get instruction operands */
return reason;
if (pattern != OP_N) {
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
tbg_tick = tbg_tick || (IR == 0105357) && iotrap; /* set TBG interrupting flag */
@ -544,7 +548,9 @@ switch (entry) { /* decode IR<3:0> */
for (i = 0; i < count; i++) {
ma = ReadW (PC); /* get operand address */
if (reason = resolve (ma, &ma, intrq)) { /* resolve indirect */
reason = resolve (ma, &ma, intrq); /* resolve indirect */
if (reason != SCPE_OK) { /* resolution failed? */
PC = err_PC; /* IRQ restarts instruction */
break;
}
@ -710,7 +716,9 @@ switch (entry) { /* decode IR<3:0> */
ma = ReadW (sa); /* get addr of actual */
sa = (sa + 1) & VAMASK; /* increment address */
if (reason = resolve (ma, &ma, intrq)) { /* resolve indirect */
reason = resolve (ma, &ma, intrq); /* resolve indirect */
if (reason != SCPE_OK) { /* resolution failed? */
PC = err_PC; /* irq restarts instruction */
break;
}

19
HP2100/hp2100_cpu7.c
View file

@ -26,6 +26,7 @@
CPU7 Vector Instruction Set and SIGNAL firmware
09-May-12 JDB Separated assignments from conditional expressions
06-Feb-12 JDB Corrected "opsize" parameter type in vis_abs
11-Sep-08 JDB Moved microcode function prototypes to hp2100_cpu1.h
05-Sep-08 JDB Removed option-present tests (now in UIG dispatchers)
@ -383,16 +384,18 @@ if (entry==0) { /* retrieve sub opcode
subcode = AR; /* for reentry */
PC = (PC + 1) & VAMASK; /* bump to real argument list */
pattern = (subcode & 0400) ? OP_AAKAKK : OP_AKAKAKK; /* scalar or vector operation */
}
}
if (pattern != OP_N)
if (pattern != OP_N) {
if (op_ftnret[entry]) { /* most VIS instrs ignore RTN addr */
ret = ReadOp(PC, in_s);
rtn = rtn1 = ret.word; /* but save it just in case */
PC = (PC + 1) & VAMASK; /* move to next argument */
}
if (reason = cpu_ops (pattern, op, intrq)) /* get instruction operands */
return reason;
reason = cpu_ops (pattern, op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
if (debug) { /* debugging? */
fprintf (sim_deb, ">>CPU VIS: IR = %06o/%06o (", /* print preamble and IR */
@ -652,9 +655,11 @@ t_bool debug = DEBUG_PRI (cpu_dev, DEB_SIG);
entry = IR & 017; /* mask to entry point */
if (op_signal[entry] != OP_N)
if (reason = cpu_ops (op_signal[entry], op, intrq)) /* get instruction operands */
return reason;
if (op_signal [entry] != OP_N) {
reason = cpu_ops (op_signal [entry], op, intrq); /* get instruction operands */
if (reason != SCPE_OK) /* evaluation failed? */
return reason; /* return reason for failure */
}
if (debug) { /* debugging? */
fprintf (sim_deb, ">>CPU SIG: IR = %06o (", IR); /* print preamble and IR */

14
HP2100/hp2100_defs.h
View file

@ -23,6 +23,9 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
12-May-12 JDB Added pragmas to suppress logical operator precedence warnings
12-Feb-12 JDB Added MA device select code assignment
Added ma_boot_ext() declaration
10-Feb-12 JDB Added hp_setsc, hp_showsc functions to support SC modifier
28-Mar-11 JDB Tidied up signal handling
29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation
@ -73,6 +76,15 @@
#include "sim_defs.h" /* simulator defns */
/* Required to quell clang precedence warnings */
#if defined (__GNUC__)
#pragma GCC diagnostic ignored "-Wunknown-pragmas"
#pragma GCC diagnostic ignored "-Wpragmas"
#pragma GCC diagnostic ignored "-Wlogical-op-parentheses"
#endif
/* Simulator stop and notification codes */
#define STOP_RSRV 1 /* must be 1 */
@ -175,6 +187,7 @@ typedef enum { INITIAL, SERVICE } POLLMODE; /* poll synchronization
#define MUXC 042 /* 12920A control */
#define DI_DA 043 /* 12821A Disc Interface with Amigo disc devices */
#define DI_DC 044 /* 12821A Disc Interface with CS/80 disc and tape devices */
#define DI_MA 045 /* 12821A Disc Interface with Amigo mag tape devices */
#define OPTDEV 002 /* start of optional devices */
#define CRSDEV 006 /* start of devices that receive CRS */
@ -467,5 +480,6 @@ extern t_stat hp_showdev (FILE *st, UNIT *uptr, int32 val, void *desc);
/* Device-specific functions */
extern int32 sync_poll (POLLMODE poll_mode);
extern t_stat ma_boot_ext (uint32 SR);
#endif

10
HP2100/hp2100_di_da.c
View file

@ -25,6 +25,7 @@
DA 12821A Disc Interface with Amigo disc drives
07-May-12 JDB Cancel the intersector delay if an untalk is received
29-Mar-12 JDB First release
04-Nov-11 JDB Created DA device
@ -1962,6 +1963,11 @@ return;
2. There is no need to test if we are processing a disc command, as the
controller would not be busy otherwise.
3. If an auto-seek will be needed to continue the read, but the seek will
fail, then an extra delay is inserted before the service call to start
the next sector. Once an Untalk is received, this delay is no longer
needed, so it is cancelled before rescheduling the service routine.
*/
static void complete_read (uint32 unit)
@ -1974,7 +1980,9 @@ if ((if_state [unit] == command_exec /* is a command exec
if_state [unit] = command_exec; /* set to execute */
da_unit [unit].PHASE = end_phase; /* the completion phase */
da_unit [unit].wait = icd_cntlr [unit].data_time; /* ensure that the controller will finish */
sim_cancel (&da_unit [unit]); /* cancel the EOT delay */
da_unit [unit].wait = icd_cntlr [unit].data_time; /* reschedule for completion */
}
return;

24
HP2100/hp2100_dp.c
View file

@ -26,6 +26,7 @@
DP 12557A 2871 disk subsystem
13210A 7900 disk subsystem
09-May-12 JDB Separated assignments from conditional expressions
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Added CNTLR_TYPE cast to dp_settype
28-Mar-11 JDB Tidied up signal handling
@ -190,7 +191,7 @@
#define STA_PROT 0002000 /* protected (13210) */
#define STA_SKI 0001000 /* incomplete NI (u) */
#define STA_SKE 0000400 /* seek error */
/* 0000200 /* unused */
/* 0000200 (unused) */
#define STA_NRDY 0000100 /* not ready (d) */
#define STA_EOC 0000040 /* end of cylinder */
#define STA_AER 0000020 /* addr error */
@ -694,7 +695,8 @@ void dp_goc (int32 fnc, int32 drv, int32 time)
{
int32 t;
if (t = sim_is_active (&dpc_unit[drv])) { /* still seeking? */
t = sim_is_active (&dpc_unit[drv]);
if (t) { /* still seeking? */
sim_cancel (&dpc_unit[drv]); /* stop seek */
dpc_sta[drv] = dpc_sta[drv] & ~STA_BSY; /* clear busy */
time = time + t; /* include seek time */
@ -906,10 +908,13 @@ switch (uptr->FNC) { /* case function */
dpc_rarh = dpc_rarh ^ 1; /* incr head */
dpc_eoc = ((dpc_rarh & 1) == 0); /* calc eoc */
}
if (err = fseek (uptr->fileref, da * sizeof (int16),
SEEK_SET)) break;
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
if (err) /* error? */
break;
fxread (dpxb, sizeof (int16), DP_NUMWD, uptr->fileref);
if (err = ferror (uptr->fileref)) break;
err = ferror (uptr->fileref);
if (err) /* error? */
break;
}
dpd_ibuf = dpxb[dp_ptr++]; /* get word */
if (dp_ptr >= DP_NUMWD) { /* end of sector? */
@ -953,10 +958,13 @@ switch (uptr->FNC) { /* case function */
dpc_rarh = dpc_rarh ^ 1; /* incr head */
dpc_eoc = ((dpc_rarh & 1) == 0); /* calc eoc */
}
if (err = fseek (uptr->fileref, da * sizeof (int16),
SEEK_SET)) break;
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
if (err) /* error? */
break;
fxwrite (dpxb, sizeof (int16), DP_NUMWD, uptr->fileref);
if (err = ferror (uptr->fileref)) break; /* error? */
err = ferror (uptr->fileref);
if (err) /* error? */
break;
dp_ptr = 0; /* next sector */
}
if (dpd.command && dpd_xfer) /* dch on, xfer? */

25
HP2100/hp2100_dq.c
View file

@ -26,6 +26,7 @@
DQ 12565A 2883 disk system
09-May-12 JDB Separated assignments from conditional expressions
10-Feb-12 JDB Deprecated DEVNO in favor of SC
28-Mar-11 JDB Tidied up signal handling
26-Oct-10 JDB Changed I/O signal handler for revised signal model
@ -100,7 +101,7 @@
#define CW_V_FNC 12 /* function */
#define CW_M_FNC 017
#define CW_GETFNC(x) (((x) >> CW_V_FNC) & CW_M_FNC)
/* 000 /* unused */
/* 000 (unused) */
#define FNC_STA 001 /* status check */
#define FNC_RCL 002 /* recalibrate */
#define FNC_SEEK 003 /* seek */
@ -530,7 +531,9 @@ void dq_goc (int32 fnc, int32 drv, int32 time)
{
int32 t;
if (t = sim_is_active (&dqc_unit[drv])) { /* still seeking? */
t = sim_is_active (&dqc_unit[drv]);
if (t) { /* still seeking? */
sim_cancel (&dqc_unit[drv]); /* cancel */
time = time + t; /* include seek time */
}
@ -740,10 +743,13 @@ switch (uptr->FNC) { /* case function */
dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */
if (dqc_rars == 0) /* wrap? incr head */
dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1;
if (err = fseek (uptr->fileref, da * sizeof (int16),
SEEK_SET)) break;
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
if (err)
break;
fxread (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref);
if (err = ferror (uptr->fileref)) break;
err = ferror (uptr->fileref);
if (err)
break;
}
dqd_ibuf = dqxb[dq_ptr++]; /* get word */
if (dq_ptr >= DQ_NUMWD) { /* end of sector? */
@ -786,10 +792,13 @@ switch (uptr->FNC) { /* case function */
dqc_rars = (dqc_rars + 1) % DQ_NUMSC; /* incr sector */
if (dqc_rars == 0) /* wrap? incr head */
dqc_uhed[drv] = dqc_rarh = dqc_rarh + 1;
if (err = fseek (uptr->fileref, da * sizeof (int16),
SEEK_SET)) return TRUE;
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
if (err)
break;
fxwrite (dqxb, sizeof (int16), DQ_NUMWD, uptr->fileref);
if (err = ferror (uptr->fileref)) break;
err = ferror (uptr->fileref);
if (err)
break;
dq_ptr = 0;
}
if (dqd.command && dqd_xfer) { /* dch on, xfer? */

44
HP2100/hp2100_ipl.c
View file

@ -25,6 +25,7 @@
IPLI, IPLO 12875A interprocessor link
09-May-12 JDB Separated assignments from conditional expressions
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Added CARD_INDEX casts to dib.card_index
07-Apr-11 JDB A failed STC may now be retried
@ -569,61 +570,62 @@ return SCPE_OK;
t_stat ipl_attach (UNIT *uptr, char *cptr)
{
SOCKET newsock;
uint32 i, t, ipa, ipp, oldf;
char *tptr;
uint32 i, t, oldf;
char host[CBUFSIZE], port[CBUFSIZE], hostport[2*CBUFSIZE+3];
char *tptr = NULL;
t_stat r;
r = get_ipaddr (cptr, &ipa, &ipp);
if ((r != SCPE_OK) || (ipp == 0))
return SCPE_ARG;
oldf = uptr->flags;
if (oldf & UNIT_ATT)
ipl_detach (uptr);
if ((sim_switches & SWMASK ('C')) ||
((sim_switches & SIM_SW_REST) && (oldf & UNIT_ACTV))) {
if (ipa == 0)
ipa = 0x7F000001;
newsock = sim_connect_sock (ipa, ipp);
r = sim_parse_addr (cptr, host, sizeof(host), "localhost", port, sizeof(port), NULL);
if ((r != SCPE_OK) || (port[0] == '\0'))
return SCPE_ARG;
sprintf(hostport, "%s%s%s%s%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", host[0] ? ":" : "", port);
newsock = sim_connect_sock (hostport, NULL, NULL);
if (newsock == INVALID_SOCKET)
return SCPE_IOERR;
printf ("Connecting to IP address %d.%d.%d.%d, port %d\n",
(ipa >> 24) & 0xff, (ipa >> 16) & 0xff,
(ipa >> 8) & 0xff, ipa & 0xff, ipp);
printf ("Connecting to %s\n", hostport);
if (sim_log)
fprintf (sim_log,
"Connecting to IP address %d.%d.%d.%d, port %d\n",
(ipa >> 24) & 0xff, (ipa >> 16) & 0xff,
(ipa >> 8) & 0xff, ipa & 0xff, ipp);
"Connecting to %s\n", hostport);
uptr->flags = uptr->flags | UNIT_ACTV;
uptr->LSOCKET = 0;
uptr->DSOCKET = newsock;
}
else {
if (ipa != 0)
r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), NULL);
if (r != SCPE_OK)
return SCPE_ARG;
newsock = sim_master_sock (ipp);
sprintf(hostport, "%s%s%s%s%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", host[0] ? ":" : "", port);
newsock = sim_master_sock (hostport, &r);
if (r != SCPE_OK)
return r;
if (newsock == INVALID_SOCKET)
return SCPE_IOERR;
printf ("Listening on port %d\n", ipp);
printf ("Listening on port %s\n", hostport);
if (sim_log)
fprintf (sim_log, "Listening on port %d\n", ipp);
fprintf (sim_log, "Listening on port %s\n", hostport);
uptr->flags = uptr->flags & ~UNIT_ACTV;
uptr->LSOCKET = newsock;
uptr->DSOCKET = 0;
}
uptr->IBUF = uptr->OBUF = 0;
uptr->flags = (uptr->flags | UNIT_ATT) & ~(UNIT_ESTB | UNIT_HOLD);
tptr = (char *) malloc (strlen (cptr) + 1); /* get string buf */
tptr = (char *) malloc (strlen (hostport) + 1); /* get string buf */
if (tptr == NULL) { /* no memory? */
ipl_detach (uptr); /* close sockets */
return SCPE_MEM;
}
strcpy (tptr, cptr); /* copy ipaddr:port */
strcpy (tptr, hostport); /* copy ipaddr:port */
uptr->filename = tptr; /* save */
sim_activate (uptr, POLL_FIRST); /* activate first poll "immediately" */
if (sim_switches & SWMASK ('W')) { /* wait? */
for (i = 0; i < 30; i++) { /* check for 30 sec */
if (t = ipl_check_conn (uptr)) /* established? */
t = ipl_check_conn (uptr);
if (t) /* established? */
break;
if ((i % 10) == 0) /* status every 10 sec */
printf ("Waiting for connnection\n");

27
HP2100/hp2100_ms.c
View file

@ -26,6 +26,7 @@
MS 13181A 7970B 800bpi nine track magnetic tape
13183A 7970E 1600bpi nine track magnetic tape
09-May-12 JDB Separated assignments from conditional expressions
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Added CNTLR_TYPE cast to ms_settype
28-Mar-11 JDB Tidied up signal handling
@ -737,7 +738,8 @@ switch (uptr->FNC) { /* case on function */
fprintf (sim_deb,
">>MSC svc: Unit %d wrote initial gap\n",
unum);
if (st = ms_write_gap (uptr)) { /* write initial gap; error? */
st = ms_write_gap (uptr); /* write initial gap*/
if (st != MTSE_OK) { /* error? */
r = ms_map_err (uptr, st); /* map error */
break; /* terminate operation */
}
@ -747,13 +749,15 @@ switch (uptr->FNC) { /* case on function */
fprintf (sim_deb,
">>MSC svc: Unit %d wrote file mark\n",
unum);
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
st = sim_tape_wrtmk (uptr); /* write tmk */
if (st != MTSE_OK) /* error? */
r = ms_map_err (uptr, st); /* map error */
msc_sta = STA_EOF; /* set EOF status */
break;
case FNC_FSR: /* space forward */
if (st = sim_tape_sprecf (uptr, &tbc)) /* space rec fwd, err? */
st = sim_tape_sprecf (uptr, &tbc); /* space rec fwd */
if (st != MTSE_OK) /* error? */
r = ms_map_err (uptr, st); /* map error */
if (tbc & 1)
msc_sta = msc_sta | STA_ODD;
@ -761,7 +765,8 @@ switch (uptr->FNC) { /* case on function */
break;
case FNC_BSR: /* space reverse */
if (st = sim_tape_sprecr (uptr, &tbc)) /* space rec rev, err? */
st = sim_tape_sprecr (uptr, &tbc); /* space rec rev*/
if (st != MTSE_OK) /* error? */
r = ms_map_err (uptr, st); /* map error */
if (tbc & 1)
msc_sta = msc_sta | STA_ODD;
@ -831,7 +836,8 @@ switch (uptr->FNC) { /* case on function */
fprintf (sim_deb,
">>MSC svc: Unit %d wrote initial gap\n",
unum);
if (st = ms_write_gap (uptr)) { /* write initial gap; error? */
st = ms_write_gap (uptr); /* write initial gap */
if (st != MTSE_OK) { /* error? */
r = ms_map_err (uptr, st); /* map error */
break; /* terminate operation */
}
@ -855,7 +861,8 @@ switch (uptr->FNC) { /* case on function */
fprintf (sim_deb,
">>MSC svc: Unit %d wrote %d word record\n",
unum, ms_ptr / 2);
if (st = sim_tape_wrrecf (uptr, msxb, ms_ptr)) { /* write, err? */
st = sim_tape_wrrecf (uptr, msxb, ms_ptr); /* write */
if (st != MTSE_OK) {
r = ms_map_err (uptr, st); /* map error */
break;
}
@ -894,7 +901,9 @@ t_stat st;
uint32 gap_len = ms_ctype ? GAP_13183 : GAP_13181; /* establish gap length */
uint32 tape_bpi = ms_ctype ? BPI_13183 : BPI_13181; /* establish nominal bpi */
if (st = sim_tape_wrgap (uptr, gap_len, tape_bpi)) /* write gap */
st = sim_tape_wrgap (uptr, gap_len, tape_bpi); /* write gap */
if (st != MTSE_OK)
return ms_map_err (uptr, st); /* map error if failure */
else
return SCPE_OK;
@ -974,7 +983,9 @@ for (i = 0; i < MS_NUMDR; i++) { /* look for write in pro
fprintf (sim_deb,
">>MSC rws: Unit %d wrote %d word partial record\n", i, ms_ptr / 2);
if (st = sim_tape_wrrecf (uptr, msxb, ms_ptr | MTR_ERF))
st = sim_tape_wrrecf (uptr, msxb, ms_ptr | MTR_ERF);
if (st != MTSE_OK)
ms_map_err (uptr, st); /* discard any error */
ms_ptr = 0; /* clear partial */

16
HP2100/hp2100_mt.c
View file

@ -25,6 +25,7 @@
MT 12559A 3030 nine track magnetic tape
09-May-12 JDB Separated assignments from conditional expressions
25-Mar-12 JDB Removed redundant MTAB_VUN from "format" MTAB entry
10-Feb-12 JDB Deprecated DEVNO in favor of SC
28-Mar-11 JDB Tidied up signal handling
@ -495,7 +496,8 @@ switch (mtc_fnc) { /* case on function */
return sim_tape_detach (uptr); /* don't set cch flg */
case FNC_WFM: /* write file mark */
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
st = sim_tape_wrtmk (uptr); /* write tmk */
if (st != MTSE_OK) /* error? */
r = mt_map_err (uptr, st); /* map error */
mtc_sta = STA_EOF; /* set EOF status */
break;
@ -504,12 +506,14 @@ switch (mtc_fnc) { /* case on function */
break;
case FNC_FSR: /* space forward */
if (st = sim_tape_sprecf (uptr, &tbc)) /* space rec fwd, err? */
st = sim_tape_sprecf (uptr, &tbc); /* space rec fwd */
if (st != MTSE_OK) /* error? */
r = mt_map_err (uptr, st); /* map error */
break;
case FNC_BSR: /* space reverse */
if (st = sim_tape_sprecr (uptr, &tbc)) /* space rec rev, err? */
st = sim_tape_sprecr (uptr, &tbc); /* space rec rev */
if (st != MTSE_OK) /* error? */
r = mt_map_err (uptr, st); /* map error */
break;
@ -558,7 +562,8 @@ switch (mtc_fnc) { /* case on function */
return SCPE_OK;
}
if (mt_ptr) { /* write buffer */
if (st = sim_tape_wrrecf (uptr, mtxb, mt_ptr)) { /* write, err? */
st = sim_tape_wrrecf (uptr, mtxb, mt_ptr); /* write */
if (st != MTSE_OK) { /* error? */
r = mt_map_err (uptr, st); /* map error */
break; /* done */
}
@ -627,7 +632,8 @@ t_stat st;
if (sim_is_active (&mtc_unit) && /* write in prog? */
(mtc_fnc == FNC_WC) && (mt_ptr > 0)) { /* yes, bad rec */
if (st = sim_tape_wrrecf (&mtc_unit, mtxb, mt_ptr | MTR_ERF))
st = sim_tape_wrrecf (&mtc_unit, mtxb, mt_ptr | MTR_ERF);
if (st != MTSE_OK)
mt_map_err (&mtc_unit, st);
}

5
HP2100/hp2100_stddev.c
View file

@ -28,6 +28,7 @@
TTY 12531C buffered teleprinter interface
CLK 12539C time base generator
09-May-12 JDB Separated assignments from conditional expressions
12-Feb-12 JDB Add TBG as a logical name for the CLK device
10-Feb-12 JDB Deprecated DEVNO in favor of SC
28-Mar-11 JDB Tidied up signal handling
@ -942,7 +943,9 @@ t_stat r;
if (tty_mode & TM_PRI) { /* printing? */
c = sim_tt_outcvt (c, TT_GET_MODE (tty_unit[TTO].flags));
if (c >= 0) { /* valid? */
if (r = sim_putchar_s (c)) return r; /* output char */
r = sim_putchar_s (c); /* output char */
if (r != SCPE_OK)
return r;
tty_unit[TTO].pos = tty_unit[TTO].pos + 1;
}
}

5
HP2100/hp2100_sys.c
View file

@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
09-May-12 JDB Quieted warnings for assignments in conditional expressions
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Added hp_setsc, hp_showsc functions to support SC modifier
15-Dec-11 JDB Added DA and dummy DC devices
@ -608,11 +609,11 @@ if (opcode[i]) { /* found opcode? */
case I_V_MRF: /* mem ref */
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
if (k = (strcmp (gbuf, "C") == 0)) { /* C specified? */
if ((k = (strcmp (gbuf, "C") == 0))) { /* C specified? */
val[0] = val[0] | I_CP;
cptr = get_glyph (cptr, gbuf, 0);
}
else if (k = (strcmp (gbuf, "Z") == 0)) { /* Z specified? */
else if ((k = (strcmp (gbuf, "Z") == 0))) { /* Z specified? */
cptr = get_glyph (cptr, gbuf, ',');
}
if ((d = get_addr (gbuf)) < 0) return SCPE_ARG;

92
HP2100/hp_disclib.c
View file

@ -24,7 +24,8 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the authors.
28-Mar-12 JDB First release
07-May-12 JDB Corrected end-of-track delay time logic
02-May-12 JDB First release
09-Nov-11 JDB Created disc controller common library from DS simulator
References:
@ -1817,28 +1818,61 @@ return SCPE_OK; /* the read was successf
On entry, the end-of-data flag is checked. If it is set, the current read is
completed. Otherwise, the command phase is reset to start the next sector,
and the disc service is scheduled to allow for the intersector delay.
and the disc service is set to allow for the intersector delay.
Implementation notes:
1. The intersector time is required to allow the ICD interface to set the
end-of-data flag before the next sector begins. The CPU must have enough
time to receive the last byte of the current sector and then unaddress
the disc controller before the first byte of the next sector is sent. If
the time is not long enough, the sector address will be incremented twice
(e.g., a 128-word read of sector 0 will terminate with sector 2 as the
next sector instead of sector 1).
1. The CPU indicates the end of a read data transfer to an ICD controller by
untalking the drive. The untalk is done by the driver as soon as the
DCPC completion interrupt is processed. However, the time from the final
DCPC transfer through driver entry to the point where the untalk is
asserted on the bus varies from 80 instructions (RTE-6/VM with OS
microcode and the buffer in the system map) to 152 instructions (RTE-IVB
with the buffer in the user map). The untalk must occur before the start
of the next sector, or the drive will begin the data transfer.
Normally, this is not a problem, as the driver clears the FIFO of any
received data after DCPC completion. However, if the read terminates
after the last sector of a track, and accessing the next sector would
require an intervening seek, and the file mask disables auto-seeking or
an enabled seek would move the positioner beyond the drive limits, then
the controller will indicate an End of Cylinder error if the untalk does
not arrive before the seek is initiated.
The RTE driver (DVA32) and various utilities that manage the disc
directly (e.g., SWTCH) do not appear to account for these bogus errors,
so the ICD controller hardware must avoid them in some unknown manner.
We work around the issue by extending the intersector delay to allow time
for a potential untalk whenever the next access would otherwise fail.
Note that this issue does not occur with writes because DCPC completion
asserts EOI concurrently with the final data byte to terminate the
command.
*/
static void end_read (CVPTR cvptr, UNIT *uptr)
{
uint32 limit;
if (cvptr->eod == SET) /* is the end of data indicated? */
dl_end_command (cvptr, normal_completion); /* complete the command */
else { /* reading continues */
uptr->PHASE = start_phase; /* reset to the start phase */
uptr->wait = cvptr->sector_time; /* delay for the intersector time */
if (cvptr->eoc == SET && cvptr->type == ICD) { /* seek will be required and controller is ICD? */
if (!(cvptr->file_mask & DL_FAUTSK)) /* if auto-seek is disabled */
limit = cvptr->cylinder; /* then the limit is the current cylinder */
else if (cvptr->file_mask & DL_FDECR) /* else if enabled and decremental seek */
limit = 0; /* then the limit is cylinder 0 */
else /* else the enabled limit is the last cylinder */
limit = drive_props [GET_MODEL (uptr->flags)].cylinders;
if (cvptr->cylinder == limit) /* is positioner at the limit? */
uptr->wait = cvptr->eot_time; /* seek will fail; delay to allow CPU to untalk */
}
}
return;
@ -1964,12 +1998,12 @@ return SCPE_OK;
/* Position the disc image file at the current sector.
The image file is positioned at the byte address corresponding to the
controller's current cylinder, head, and sector address. Positioning may
involve an auto-seek if a prior read or write addressed the final sector in a
cylinder. If a seek is initiated or an error is detected, the routine
returns FALSE to indicate that the positioning was not performed. If the
file was positioned, the routine returns TRUE.
The image file is positioned at the byte address corresponding to the drive's
current cylinder and the controller's current head and sector addresses.
Positioning may involve an auto-seek if a prior read or write addressed the
final sector of a cylinder. If a seek is initiated or an error is detected,
the routine returns FALSE to indicate that the positioning was not performed.
If the file was positioned, the routine returns TRUE.
On entry, if the controller's end-of-cylinder flag is set, a prior read or
write addressed the final sector in the current cylinder. If the file mask
@ -1983,21 +2017,23 @@ return SCPE_OK;
seek completion and the command state unchanged. When the service is
reentered, the read or write will continue on the new cylinder.
If the EOC flag was not set, the drive position is checked against the
controller position. If they are different (as may occur with an Address
Record command that specified a different location than the last Seek
command), a seek is started to the correct cylinder, and the routine returns
with the disc service scheduled for seek completion as above.
If the EOC flag was not set, the drive's position is checked against the
controller's position if address verification is requested. If they are
different (as may occur with an Address Record command that specified a
different location than the last Seek command), a seek is started to the
correct cylinder, and the routine returns with the disc service scheduled for
seek completion as above.
If the drive and controller positions agree, the controller CHS address is
validated against the drive limits. If they are invalid, Seek Check status
is set, and the command is terminated with an error.
If the drive and controller positions agree or verification is not requested,
the CHS addresses are validated against the drive limits. If they are
invalid, Seek Check status is set, and the command is terminated with an
error.
If the address is valid, the drive is checked to ensure that it is ready for
positioning. If it is, the the byte offset in the image file is calculated
from the CHS address, and the file is positioned. The disc service is
scheduled to begin the data transfer, and the routine returns TRUE to
indicate that the file position was set.
If the addresses are valid, the drive is checked to ensure that it is ready
for positioning. If it is, the the byte offset in the image file is
calculated from the CHS address, and the file is positioned. The disc
service is scheduled to begin the data transfer, and the routine returns TRUE
to indicate that the file position was set.
Implementation notes:

7
HP2100/hp_disclib.h
View file

@ -24,7 +24,8 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the authors.
30-Mar-12 JDB First release
07-May-12 JDB Added end-of-track delay time as a controller variable
02-May-12 JDB First release
09-Nov-11 JDB Created disc controller common library from DS simulator
@ -53,6 +54,7 @@
/* Default controller times */
#define DL_EOT_TIME 160 /* end-of-track delay time */
#define DL_SEEK_TIME 100 /* seek delay time (per cylinder) */
#define DL_SECTOR_TIME 27 /* intersector delay time */
#define DL_CMD_TIME 3 /* command start delay time */
@ -330,6 +332,7 @@ typedef struct {
uint32 index; /* data buffer current index */
uint32 length; /* data buffer valid length */
UNIT *aux; /* MAC auxiliary units (controller and timer) */
int32 eot_time; /* end-of-track read delay time */
int32 seek_time; /* per-cylinder seek delay time */
int32 sector_time; /* intersector delay time */
int32 cmd_time; /* command response time */
@ -354,7 +357,7 @@ typedef CNTLR_VARS *CVPTR; /* pointer to controller
CLEAR, CLEAR, \
0, 0, 0, 0, 0, 0, 0, 0, \
(bufptr), 0, 0, (auxptr), \
DL_SEEK_TIME, DL_SECTOR_TIME, \
DL_EOT_TIME, DL_SEEK_TIME, DL_SECTOR_TIME, \
DL_CMD_TIME, DL_DATA_TIME, DL_WAIT_TIME

2
I1401/i1401_cd.c
View file

@ -184,7 +184,7 @@ t_stat r;
if (sim_is_active (&cdr_unit)) { /* busy? */
sim_cancel (&cdr_unit); /* cancel */
if (r = cdr_svc (&cdr_unit)) /* process */
if ((r = cdr_svc (&cdr_unit))) /* process */
return r;
}
if ((cdr_unit.flags & UNIT_ATT) == 0) /* attached? */

24
I1401/i1401_cpu.c
View file

@ -547,7 +547,7 @@ while (reason == 0) { /* loop until halted */
saved_IS = IS; /* commit prev instr */
if (sim_interval <= 0) { /* check clock queue */
if (reason = sim_process_event ())
if ((reason = sim_process_event ()))
break;
}
@ -1039,7 +1039,7 @@ CHECK_LENGTH:
*/
case OP_R: /* read */
if (reason = iomod (ilnt, D, r_mod)) /* valid modifier? */
if ((reason = iomod (ilnt, D, r_mod))) /* valid modifier? */
break;
reason = read_card (ilnt, D); /* read card */
BS = CDR_BUF + CDR_WIDTH;
@ -1049,7 +1049,7 @@ CHECK_LENGTH:
break;
case OP_W: /* write */
if (reason = iomod (ilnt, D, w_mod)) /* valid modifier? */
if ((reason = iomod (ilnt, D, w_mod))) /* valid modifier? */
break;
reason = write_line (ilnt, D); /* print line */
BS = LPT_BUF + LPT_WIDTH;
@ -1059,7 +1059,7 @@ CHECK_LENGTH:
break;
case OP_P: /* punch */
if (reason = iomod (ilnt, D, p_mod)) /* valid modifier? */
if ((reason = iomod (ilnt, D, p_mod))) /* valid modifier? */
break;
reason = punch_card (ilnt, D); /* punch card */
BS = CDP_BUF + CDP_WIDTH;
@ -1069,7 +1069,7 @@ CHECK_LENGTH:
break;
case OP_WR: /* write and read */
if (reason = iomod (ilnt, D, w_mod)) /* valid modifier? */
if ((reason = iomod (ilnt, D, w_mod))) /* valid modifier? */
break;
reason = write_line (ilnt, D); /* print line */
r1 = read_card (ilnt, D); /* read card */
@ -1082,7 +1082,7 @@ CHECK_LENGTH:
break;
case OP_WP: /* write and punch */
if (reason = iomod (ilnt, D, w_mod)) /* valid modifier? */
if ((reason = iomod (ilnt, D, w_mod))) /* valid modifier? */
break;
reason = write_line (ilnt, D); /* print line */
r1 = punch_card (ilnt, D); /* punch card */
@ -1095,7 +1095,7 @@ CHECK_LENGTH:
break;
case OP_RP: /* read and punch */
if (reason = iomod (ilnt, D, NULL)) /* valid modifier? */
if ((reason = iomod (ilnt, D, NULL))) /* valid modifier? */
break;
reason = read_card (ilnt, D); /* read card */
r1 = punch_card (ilnt, D); /* punch card */
@ -1108,7 +1108,7 @@ CHECK_LENGTH:
break;
case OP_WRP: /* write, read, punch */
if (reason = iomod (ilnt, D, w_mod)) /* valid modifier? */
if ((reason = iomod (ilnt, D, w_mod))) /* valid modifier? */
break;
reason = write_line (ilnt, D); /* print line */
r1 = read_card (ilnt, D); /* read card */
@ -1122,9 +1122,9 @@ CHECK_LENGTH:
break;
case OP_SS: /* select stacker */
if (reason = iomod (ilnt, D, ss_mod)) /* valid modifier? */
if ((reason = iomod (ilnt, D, ss_mod))) /* valid modifier? */
break;
if (reason = select_stack (D)) /* sel stack, error? */
if ((reason = select_stack (D))) /* sel stack, error? */
break;
if ((ilnt == 4) || (ilnt == 5)) { /* check for branch */
BRANCH;
@ -1132,7 +1132,7 @@ CHECK_LENGTH:
break;
case OP_CC: /* carriage control */
if (reason = carriage_control (D)) /* car ctrl, error? */
if ((reason = carriage_control (D))) /* car ctrl, error? */
break;
if ((ilnt == 4) || (ilnt == 5)) { /* check for branch */
BRANCH;
@ -1154,7 +1154,7 @@ CHECK_LENGTH:
reason = STOP_INVL;
else if (ioind != BCD_PERCNT) /* valid dev addr? */
reason = STOP_INVA;
else if (reason = iomod (ilnt, D, mtf_mod)) /* valid modifier? */
else if ((reason = iomod (ilnt, D, mtf_mod))) /* valid modifier? */
break;
if (dev == IO_MT) /* BCD? */
reason = mt_func (unit, 0, D);

16
I1401/i1401_dp.c
View file

@ -269,7 +269,7 @@ switch (fnc) { /* case on function */
for (;;) { /* loop */
qzr = (--cnt == 0); /* set zero latch */
dp_cvt_bin (dcf + DCF_CNT, DCF_CNT_LEN, cnt, MD_WM); /* redo count */
if (r = dp_rdsec (uptr, psec, flg, qwc)) /* read sector */
if ((r = dp_rdsec (uptr, psec, flg, qwc))) /* read sector */
break;
cnt = dp_get_cnt (dcf); /* get new count */
if (cnt < 0) /* bad count? */
@ -278,7 +278,7 @@ switch (fnc) { /* case on function */
break;
sec++; psec++; /* next sector */
dp_cvt_bin (dcf + DCF_SEC, DCF_SEC_LEN, sec, flg); /* rewr sec */
if (r = dp_nexsec (uptr, psec, dcf)) /* find next */
if ((r = dp_nexsec (uptr, psec, dcf))) /* find next */
break;
}
break; /* done, clean up */
@ -289,9 +289,9 @@ switch (fnc) { /* case on function */
for (;;) { /* loop */
qzr = (--cnt == 0); /* set zero latch */
dp_cvt_bin (dcf + DCF_CNT, DCF_CNT_LEN, cnt, MD_WM); /* redo count */
if (r = dp_rdadr (uptr, psec, flg, qwc)) /* read addr */
if ((r = dp_rdadr (uptr, psec, flg, qwc))) /* read addr */
break; /* error? */
if (r = dp_rdsec (uptr, psec, flg, qwc)) /* read data */
if ((r = dp_rdsec (uptr, psec, flg, qwc))) /* read data */
break; /* error? */
cnt = dp_get_cnt (dcf); /* get new count */
if (cnt < 0) /* bad count? */
@ -312,13 +312,13 @@ switch (fnc) { /* case on function */
for (;;) { /* loop */
qzr = (--cnt == 0); /* set zero latch */
dp_cvt_bin (dcf + DCF_CNT, DCF_CNT_LEN, cnt, MD_WM); /* rewr cnt */
if (r = dp_wrsec (uptr, psec, flg)) /* write data */
if ((r = dp_wrsec (uptr, psec, flg))) /* write data */
break;
if (qzr) /* zero latch? done */
break;
sec++; psec++; /* next sector */
dp_cvt_bin (dcf + DCF_SEC, DCF_SEC_LEN, sec, flg); /* rewr sec */
if (r = dp_nexsec (uptr, psec, dcf)) /* find next */
if ((r = dp_nexsec (uptr, psec, dcf))) /* find next */
break;
}
break; /* done, clean up */
@ -331,9 +331,9 @@ switch (fnc) { /* case on function */
for (;;) { /* loop */
qzr = (--cnt == 0); /* set zero latch */
dp_cvt_bin (dcf + DCF_CNT, DCF_CNT_LEN, cnt, MD_WM); /* redo count */
if (r = dp_wradr (uptr, psec, flg)) /* write addr */
if ((r = dp_wradr (uptr, psec, flg))) /* write addr */
break;
if (r = dp_wrsec (uptr, psec, flg)) /* write data */
if ((r = dp_wrsec (uptr, psec, flg))) /* write data */
break;
if (qzr) /* zero latch? done */
break;

4
I1401/i1401_iq.c
View file

@ -93,8 +93,8 @@ ind[IN_INC] = 0; /* clear inq clear */
switch (mod) { /* case on mod */
case BCD_R: /* input */
/* if (ind[IN_INR] == 0)
/* return SCPE_OK; /* return if no req */
/* if (ind[IN_INR] == 0) */
/* return SCPE_OK; *//* return if no req */
ind[IN_INR] = 0; /* clear req */
puts_tty ("[Enter]\r\n"); /* prompt */
for (i = 0; M[BS] != (BCD_GRPMRK + WM); i++) { /* until GM + WM */

2
I1401/i1401_mt.c
View file

@ -451,7 +451,7 @@ int32 i;
UNIT *uptr;
for (i = 0; i < MT_NUMDR; i++) { /* per drive resets */
if (uptr = mt_sel_unit (i)) {
if ((uptr = mt_sel_unit (i))) {
MT_CLR_PNU (uptr); /* clear pos flag */
}
}

2
I1401/i1401_sys.c
View file

@ -402,7 +402,7 @@ if (op >= 64) /* successful? */
return SCPE_ARG;
val[0] = op | WM; /* store opcode */
cptr = get_glyph (cptr, gbuf, 0); /* get addr or d */
if (((op_table[op] && IO) && (get_io (gbuf, &val[1]) == SCPE_OK)) ||
if (((op_table[op] & IO) && (get_io (gbuf, &val[1]) == SCPE_OK)) ||
(get_addr (gbuf, &val[1]) == SCPE_OK)) {
cptr = get_glyph (cptr, gbuf, 0); /* get addr or d */
if (get_addr (gbuf, &val[4]) == SCPE_OK) {

2
I1620/i1620_cd.c
View file

@ -109,7 +109,7 @@ DEVICE cdp_dev = {
- Can punch both 11 (-) and 11-0 (uses ]).
On input, the nul and nl generated by C are converted to
spaces; tabs and line feeds are also converted to spaces.
*/
/* Card reader (ASCII) to numeric (one digit) */
const char cdr_to_num[128] = {

2
I1620/i1620_cpu.c
View file

@ -476,7 +476,7 @@ while (reason == 0) { /* loop until halted */
saved_PC = PC; /* commit prev instr */
if (sim_interval <= 0) { /* check clock queue */
if (reason = sim_process_event ())
if ((reason = sim_process_event ()))
break;
}

16
I1620/i1620_dp.c
View file

@ -206,7 +206,7 @@ switch (f1 & ~(FNC_WCH | FNC_NRL)) { /* case on function */
if (psec < 0) /* error? */
CRETIOE (dp_stop, STOP_DACERR);
do { /* loop on count */
if (r = dp_rdsec (uptr, psec, qnr, qwc)) /* read sector */
if ((r = dp_rdsec (uptr, psec, qnr, qwc))) /* read sector */
break;
sec++; psec++; /* next sector */
} while ((--cnt > 0) &&
@ -216,9 +216,9 @@ switch (f1 & ~(FNC_WCH | FNC_NRL)) { /* case on function */
case FNC_TRK: /* read track */
psec = dp_trkop (drv, sec); /* start of track */
for (cnt = 0; cnt < DP_NUMSC; cnt++) { /* full track */
if (r = dp_rdadr (uptr, psec, qnr, qwc)) /* read addr */
if ((r = dp_rdadr (uptr, psec, qnr, qwc))) /* read addr */
break; /* error? */
if (r = dp_rdsec (uptr, psec, qnr, qwc)) /* read data */
if ((r = dp_rdsec (uptr, psec, qnr, qwc))) /* read data */
break; /* error? */
psec = dp_trkop (drv, sec) + ((psec + 1) % DP_NUMSC);
}
@ -231,9 +231,9 @@ switch (f1 & ~(FNC_WCH | FNC_NRL)) { /* case on function */
if (psec < 0) /* error? */
CRETIOE (dp_stop, STOP_DACERR);
do { /* loop on count */
if (r = dp_tstgm (M[dp_ba], qnr)) /* start with gm? */
if ((r = dp_tstgm (M[dp_ba], qnr))) /* start with gm? */
break;
if (r = dp_wrsec (uptr, psec, qnr)) /* write data */
if ((r = dp_wrsec (uptr, psec, qnr))) /* write data */
break;
sec++; psec++; /* next sector */
} while ((--cnt > 0) &&
@ -245,11 +245,11 @@ switch (f1 & ~(FNC_WCH | FNC_NRL)) { /* case on function */
return STOP_WRADIS;
psec = dp_trkop (drv, sec); /* start of track */
for (cnt = 0; cnt < DP_NUMSC; cnt++) { /* full track */
if (r = dp_tstgm (M[dp_ba], qnr)) /* start with gm? */
if ((r = dp_tstgm (M[dp_ba], qnr))) /* start with gm? */
break;
if (r = dp_wradr (uptr, psec, qnr)) /* write addr */
if ((r = dp_wradr (uptr, psec, qnr))) /* write addr */
break;
if (r = dp_wrsec (uptr, psec, qnr)) /* write data */
if ((r = dp_wrsec (uptr, psec, qnr))) /* write data */
break;
psec = dp_trkop (drv, sec) + ((psec + 1) % DP_NUMSC);
}

2
I1620/i1620_sys.c
View file

@ -552,7 +552,7 @@ if (I_GETQP (opfl) != I_M_QNP) { /* Q field allowed? */
cptr = get_glyph (cptr, fptr = gbuf, ' '); /* get flag field */
last = -1; /* none yet */
while (t = *fptr++) { /* loop through */
while ((t = *fptr++)) { /* loop through */
if ((t < '0') || (t > '9')) /* must be digit */
return SCPE_ARG;
t = t - '0'; /* convert */

2
I1620/i1620_tty.c
View file

@ -260,7 +260,7 @@ do {
*c = 0x7F;
else if ((raw == '~') || (raw == '`')) /* flag? mark */
flg = FLAG;
else if (cp = strchr (tti_to_num, raw)) /* legal? */
else if ((cp = strchr (tti_to_num, raw))) /* legal? */
*c = ((int8) (cp - tti_to_num)) | flg; /* assemble char */
else raw = 007; /* beep! */
tto_write (raw); /* echo */

2
I7094/i7094_com.c
View file

@ -1175,7 +1175,7 @@ char name[20];
ln = uptr - coml_dev.units;
sprintf (name, val? "Output queue %d": "Input queue %d", ln);
lh = val? &com_outq[ln]: &com_inpq[ln];
if (entc = com_show_qsumm (st, lh, name)) {
if ((entc = com_show_qsumm (st, lh, name))) {
for (i = 0, next = lh->head; next != 0;
i++, next = com_pkt[next].next) {
if ((i % 8) == 0)

10
I7094/i7094_cpu.c
View file

@ -664,14 +664,14 @@ while (reason == SCPE_OK) { /* loop until error */
}
if (sim_interval <= 0) { /* intv cnt expired? */
if (reason = sim_process_event ()) /* process events */
if ((reason = sim_process_event ())) /* process events */
break;
chtr_pend = chtr_eval (NULL); /* eval chan traps */
}
for (i = 0; ch_req && (i < NUM_CHAN); i++) { /* loop thru channels */
if (ch_req & REQ_CH (i)) { /* channel request? */
if (reason = ch_proc (i))
if ((reason = ch_proc (i)))
break;
}
chtr_pend = chtr_eval (NULL);
@ -1973,13 +1973,13 @@ while (reason == SCPE_OK) { /* loop until error */
t_stat r;
for (i = 0; (i < HALT_IO_LIMIT) && !ch_qidle (); i++) {
sim_interval = 0;
if (r = sim_process_event ()) /* process events */
if ((r = sim_process_event ())) /* process events */
return r;
chtr_pend = chtr_eval (NULL); /* eval chan traps */
while (ch_req) { /* until no ch req */
for (j = 0; j < NUM_CHAN; j++) { /* loop thru channels */
if (ch_req & REQ_CH (j)) { /* channel request? */
if (r = ch_proc (j))
if ((r = ch_proc (j)))
return r;
}
chtr_pend = chtr_eval (NULL);
@ -2438,7 +2438,7 @@ if (pc & HIST_PC) { /* instruction? */
}
fputc ('\n', st); /* end line */
} /* end if instruction */
else if (ch = HIST_CH (pc)) { /* channel? */
else if ((ch = HIST_CH (pc))) { /* channel? */
fprintf (st, "CH%c ", 'A' + ch - 1);
fprintf (st, "%05o ", pc & AMASK);
fputs (" ", st);

12
I7094/i7094_dsk.c
View file

@ -693,14 +693,14 @@ trk = uaptr->TRK; /* get access track */
switch (dsk_sta) { /* case on state */
case CHSL_RDS: /* read start */
if (r = dsk_init_trk (udptr, trk)) { /* read track, err? */
if ((r = dsk_init_trk (udptr, trk))) { /* read track, err? */
return ((r == ERR_NRCF)? SCPE_OK: r); /* rec not fnd ok */
}
dsk_sta = CHSL_RDS|CHSL_2ND; /* next state */
break;
case CHSL_RDS|CHSL_2ND: /* read data transmit */
if (r = dsk_xfer_done (uaptr, dtyp)) { /* transfer done? */
if ((r = dsk_xfer_done (uaptr, dtyp))) { /* transfer done? */
if (r != ERR_ENDRC) /* error? */
return r;
dsk_sta = CHSL_RDS|CHSL_3RD; /* next state */
@ -721,7 +721,7 @@ switch (dsk_sta) { /* case on state */
break;
case CHSL_WRS: /* write start */
if (r = dsk_init_trk (udptr, trk)) { /* read track, err? */
if ((r = dsk_init_trk (udptr, trk))) { /* read track, err? */
return ((r == ERR_NRCF)? SCPE_OK: r); /* rec not fnd ok */
}
ch_req |= REQ_CH (dsk_ch); /* first request */
@ -742,7 +742,7 @@ switch (dsk_sta) { /* case on state */
else dsk_buf[dsk_rptr++] = dsk_chob; /* write, store word */
if (dsk_rptr == T1STREC) /* if THA, skip after HA */
dsk_rptr++;
if (r = dsk_xfer_done (uaptr, dtyp)) { /* transfer done? */
if ((r = dsk_xfer_done (uaptr, dtyp))) { /* transfer done? */
if (r != ERR_ENDRC) /* error? */
return r;
dsk_sta = CHSL_WRS|CHSL_3RD; /* next state */
@ -755,7 +755,7 @@ switch (dsk_sta) { /* case on state */
case CHSL_WRS|CHSL_3RD: /* write done */
if (!dsk_wchk) { /* if write */
if (r = dsk_wr_trk (udptr, trk)) /* write track; err? */
if ((r = dsk_wr_trk (udptr, trk))) /* write track; err? */
return r;
}
if (dsk_qdone (dsk_ch)) /* done? exit */
@ -846,7 +846,7 @@ switch (dsk_sta) { /* case on state */
if (!dsk_wchk) { /* actual write? */
trk = trk - (trk % dsk_tab[dtyp].trkpc); /* cyl start */
for (i = 0; i < dsk_tab[dtyp].trkpc; i++) { /* do all tracks */
if (r = dsk_wr_trk (udptr, trk + i)) /* wr track; err? */
if ((r = dsk_wr_trk (udptr, trk + i))) /* wr track; err? */
return r;
}
}

22
I7094/i7094_io.c
View file

@ -795,7 +795,7 @@ switch (ch_sta[ch]) { /* case on chan state */
if (ch_dev[ch].flags & DEV_7289) { /* drum channel? */
ir = ReadP (clc); /* read addr */
ch_clc[ch] = CHAINC (clc); /* incr chan pc */
if (r = ch9_wr (ch, ir, 0)) /* write to dev */
if ((r = ch9_wr (ch, ir, 0))) /* write to dev */
return r;
}
else ch_clc[ch] = clc; /* set clc */
@ -1003,7 +1003,7 @@ if (ch_dev[ch].flags & DEV_7909) { /* 7909 */
return SCPE_OK;
case CH9_SNS: /* sense */
if (r = ch9_sel (ch, CHSL_SNS)) /* send sense to dev */
if ((r = ch9_sel (ch, CHSL_SNS))) /* send sense to dev */
return r;
ch_flags[ch] |= CHF_PRD; /* prepare to read */
break; /* next command */
@ -1019,13 +1019,13 @@ if (ch_dev[ch].flags & DEV_7909) { /* 7909 */
}
ch_flags[ch] &= ~CHF_EOR; /* clear end */
if (ch_op[ch] == CH9_CTLR) { /* CTLR? */
if (r = ch9_sel (ch, CHSL_RDS)) /* send read sel */
if ((r = ch9_sel (ch, CHSL_RDS))) /* send read sel */
return r;
ch_flags[ch] |= CHF_PRD; /* prep to read */
ch_idf[ch] = 0;
}
else if (ch_op[ch] == CH9_CTLW) { /* CTLW? */
if (r = ch9_sel (ch, CHSL_WRS)) /* end write sel */
if ((r = ch9_sel (ch, CHSL_WRS))) /* end write sel */
return r;
ch_flags[ch] |= CHF_PWR; /* prep to write */
}
@ -1035,7 +1035,7 @@ if (ch_dev[ch].flags & DEV_7909) { /* 7909 */
if ((ch_wc[ch] == 0) || (ch_flags[ch] & CHF_EOR)) { /* wc == 0 or EOR? */
if (ch_flags[ch] & (CHF_PRD|CHF_PWR|CHF_RDS|CHF_WRS)) {
ch_flags[ch] &= ~(CHF_PRD|CHF_PWR|CHF_RDS|CHF_WRS);
if (r = ch9_wr (ch, 0, CH9DF_STOP)) /* send stop */
if ((r = ch9_wr (ch, 0, CH9DF_STOP))) /* send stop */
return r;
}
if (ch_flags[ch] & CHF_EOR) { /* EOR? */
@ -1055,7 +1055,7 @@ if (ch_dev[ch].flags & DEV_7909) { /* 7909 */
ch_flags[ch] &= ~CHF_EOR; /* ignore */
else if (ch_flags[ch] & CHF_RDS) /* read? */
ch9_rd_putw (ch);
else if (r = ch9_wr_getw (ch)) /* no, write */
else if ((r = ch9_wr_getw (ch))) /* no, write */
return r;
if (ch_wc[ch] == 0) /* done? get next */
break;
@ -1164,7 +1164,7 @@ else { /* 7607 write */
case CH6_IOCD: /* IOCD */
if (ch_wc[ch]) { /* wc > 0? */
if (r = ch6_wr_getw (ch, TRUE)) /* send wd to dev; err? */
if ((r = ch6_wr_getw (ch, TRUE))) /* send wd to dev; err? */
return r;
if (ch_wc[ch]) /* more to do? */
return SCPE_OK;
@ -1174,7 +1174,7 @@ else { /* 7607 write */
case CH6_IOCP: /* IOCP */
case CH6_IOSP: /* IOSP */
if (ch_wc[ch]) { /* wc > 0? */
if (r = ch6_wr_getw (ch, FALSE)) /* send wd to dev; err? */
if ((r = ch6_wr_getw (ch, FALSE))) /* send wd to dev; err? */
return r;
if (ch_wc[ch]) /* more to do? */
return SCPE_OK;
@ -1184,7 +1184,7 @@ else { /* 7607 write */
case CH6_IOCT: /* IOCT */
case CH6_IOST: /* IOST */
if (ch_wc[ch]) { /* wc > 0? */
if (r = ch6_wr_getw (ch, FALSE)) /* send wd to dev; err? */
if ((r = ch6_wr_getw (ch, FALSE))) /* send wd to dev; err? */
return r;
if (ch_wc[ch]) /* more to do? */
return SCPE_OK;
@ -1193,7 +1193,7 @@ else { /* 7607 write */
case CH6_IORP: /* IORP */
if (!(ch_flags[ch] & CHF_EOR) && ch_wc[ch]) { /* not EOR? (cdp, lpt) */
if (r = ch6_wr_getw (ch, TRUE)) /* send wd to dev; err? */
if ((r = ch6_wr_getw (ch, TRUE))) /* send wd to dev; err? */
return r;
if (ch_wc[ch]) /* more to do? */
return SCPE_OK;
@ -1203,7 +1203,7 @@ else { /* 7607 write */
case CH6_IORT: /* IORT */
if (!(ch_flags[ch] & CHF_EOR) && ch_wc[ch]) { /* not EOR? (cdp, lpt) */
if (r = ch6_wr_getw (ch, TRUE)) /* send wd to dev; err? */
if ((r = ch6_wr_getw (ch, TRUE))) /* send wd to dev; err? */
return r;
if (ch_wc[ch]) /* more to do? */
return SCPE_OK;

4
I7094/i7094_mt.c
View file

@ -564,7 +564,7 @@ switch (uptr->UST) { /* case on state */
bc = chrono_rd (xb, MT_MAXFR); /* read clock */
else { /* real tape */
r = sim_tape_rdrecf (uptr, xb, &bc, MT_MAXFR); /* read record */
if (r = mt_map_err (uptr, r)) /* map status */
if ((r = mt_map_err (uptr, r))) /* map status */
return r;
if (mt_unit[ch] == 0) /* disconnected? */
return SCPE_OK;
@ -736,7 +736,7 @@ if (mt_bptr[ch]) { /* any data? */
if (xb == NULL)
return SCPE_IERR;
r = sim_tape_wrrecf (uptr, xb, mt_bptr[ch]); /* write record */
if (r = mt_map_err (uptr, r)) /* map error */
if ((r = mt_map_err (uptr, r))) /* map error */
return r;
}
uptr->UST = CHSL_WRS|CHSL_3RD; /* next state */

3
Ibm1130/ibm1130_cr.c
View file

@ -2580,7 +2580,8 @@ static t_stat pcr_svc (UNIT *uptr)
break;
case OP_READING:
if (pcr_nready >= 2) { /* if there is a whole column buffered, simulate column interrupt/* pcr_trigger_interrupt_0 - simulate a read response interrupt so OS will read queued column data */
if (pcr_nready >= 2) { /* if there is a whole column buffered, simulate column interrupt*/
/* pcr_trigger_interrupt_0 - simulate a read response interrupt so OS will read queued column data */
pcr_trigger_interrupt_0();
sim_activate(&cr_unit, cr_wait); /* keep checking frequently */

114
Ibm1130/ibm1130_sca.c
View file

@ -85,9 +85,6 @@
#include "ibm1130_defs.h"
#include "sim_sock.h" /* include path must include main simh directory */
#include <ctype.h>
#ifndef INADDR_NONE
#define INADDR_NONE ((unsigned long)-1)
#endif
#define DEBUG_SCA_FLUSH 0x0001 /* debugging options */
#define DEBUG_SCA_TRANSMIT 0x0002
@ -106,7 +103,7 @@
/* #define DEBUG_SCA (DEBUG_SCA_TIMERS|DEBUG_SCA_FLUSH|DEBUG_SCA_TRANSMIT|DEBUG_SCA_CHECK_INDATA|DEBUG_SCA_RECEIVE_SYNC|DEBUG_SCA_RECEIVE_DATA|DEBUG_SCA_XIO_INITR|DEBUG_SCA_XIO_INITW) */
#define DEBUG_SCA (DEBUG_SCA_TIMERS|DEBUG_SCA_FLUSH|DEBUG_SCA_CHECK_INDATA|DEBUG_SCA_XIO_INITR|DEBUG_SCA_XIO_INITW)
#define SCA_DEFAULT_PORT 2703 /* default socket, This is the number of the IBM 360's BSC device */
#define SCA_DEFAULT_PORT "2703" /* default socket, This is the number of the IBM 360's BSC device */
#define MAX_SYNS 100 /* number of consecutive syn's after which we stop buffering them */
@ -164,7 +161,7 @@ static uint32 sca_state = SCA_STATE_IDLE;
static uint8 sichar = 0; /* sync/idle character */
static uint8 rcvd_char = 0; /* most recently received character */
static uint8 sca_frame = 8;
static uint16 sca_port = SCA_DEFAULT_PORT; /* listening port number */
static char sca_port[CBUFSIZE]; /* listening port */
static int32 sca_keepalive = 0; /* keepalive SYN packet period in msec, default = 0 (disabled) */
static SCA_TIMER_STATE sca_timer_state[3]; /* current timer state */
static int sca_timer_endtime[3]; /* clocktime when timeout is to occur if state is RUNNING */
@ -217,11 +214,11 @@ REG sca_reg[] = { /* DEVICE STATE/SETTABLE PARAMETERS: */
{ HRDATA (SCADSW, sca_dsw, 16) }, /* device status word */
{ DRDATA (SICHAR, sichar, 8), PV_LEFT }, /* sync/idle character */
{ DRDATA (RCVDCHAR, rcvd_char, 8), PV_LEFT }, /* most recently received character */
{ DRDATA (FRAME, sca_frame, 8), PV_LEFT }, /* frame bits (6, 7 or 8)
{ DRDATA (FRAME, sca_frame, 8), PV_LEFT }, /* frame bits (6, 7 or 8) */
{ DRDATA (SCASTATE, sca_state, 32), PV_LEFT }, /* current state */
{ DRDATA (CTIME, sca_cwait, 32), PV_LEFT }, /* inter-character wait */
{ DRDATA (ITIME, sca_iwait, 32), PV_LEFT }, /* idle wait (polling interval for socket connects) */
{ DRDATA (SCASOCKET, sca_port, 16), PV_LEFT }, /* listening port number */
{ BRDATA (SCASOCKET, sca_port, 8, 8, sizeof(sca_port)) }, /* listening port number */
{ DRDATA (KEEPALIVE, sca_keepalive, 32), PV_LEFT }, /* keepalive packet period in msec */
{ NULL } };
@ -317,7 +314,7 @@ static void sca_socket_error (void)
free(sca_unit.filename);
if (sca_unit.flags & UNIT_LISTEN) {
sprintf(name, "(Listening on port %d)", sca_port);
sprintf(name, "(Listening on port %s)", sca_port);
sca_unit.filename = mstring(name);
printf("%s\n", name);
}
@ -454,39 +451,39 @@ static t_stat sca_reset (DEVICE *dptr)
static t_stat sca_attach (UNIT *uptr, char *cptr)
{
char host[CBUFSIZE], port[CBUFSIZE];
t_bool do_listen;
char *colon;
uint32 ipaddr;
int32 port;
struct hostent *he;
char name[256];
static SOCKET sdummy = INVALID_SOCKET;
fd_set wr_set, err_set;
char name[CBUFSIZE];
t_stat r;
do_listen = sim_switches & SWMASK('L'); /* -l means listen mode */
if (sca_unit.flags & UNIT_ATT) /* if already attached, detach */
detach_unit(&sca_unit);
if (do_listen) { /* if listen mode, string specifies socket number (only; otherwise it's a dummy argument) */
if (isdigit(*cptr)) { /* if digits specified, extract port number */
port = atoi(cptr);
if (port <= 0 || port > 65535)
return SCPE_ARG;
else
sca_port = port;
}
if (do_listen) { /* if listen mode, string specifies port number (only; otherwise it's a dummy argument) */
r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), SCA_DEFAULT_PORT);
if (r != SCPE_OK)
return r;
if ((0 == strcmp(port, cptr)) && (0 == strcmp(port, "dummy")))
strcpy(port, SCA_DEFAULT_PORT);
sprintf(sca_port, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port);
/* else if nondigits specified, ignore... but the command has to have something there otherwise the core scp */
/* attach_cmd() routine complains "too few arguments". */
if ((sca_lsock = sim_master_sock(sca_port)) == INVALID_SOCKET)
sca_lsock = sim_master_sock(sca_port, &r);
if (r != SCPE_OK)
return r;
if (sca_lsock == INVALID_SOCKET)
return SCPE_OPENERR;
SETBIT(sca_unit.flags, UNIT_LISTEN); /* note that we are listening, not yet connected */
sprintf(name, "(Listening on port %d)", sca_port);
sprintf(name, "(Listening on port %s)", sca_port);
sca_unit.filename = mstring(name);
printf("%s\n", name);
printf("%s\n", sca_unit.filename);
}
else {
@ -496,57 +493,33 @@ static t_stat sca_attach (UNIT *uptr, char *cptr)
if (! *cptr)
return SCPE_2FARG;
if ((colon = strchr(cptr, ':')) != NULL) {
*colon++ = '\0'; /* clip hostname at colon */
port = atoi(colon); /* extract port number that follows it */
if (port <= 0 || port > 65535)
return SCPE_ARG;
else
sca_port = port;
r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), SCA_DEFAULT_PORT);
if (r != SCPE_OK)
return r;
if ((0 == strcmp(cptr, port)) && (0 == strcmp(host, ""))) {
strcpy(host, port);
strcpy(port, SCA_DEFAULT_PORT);
}
if (sdummy == INVALID_SOCKET)
if ((sdummy = sim_create_sock()) == INVALID_SOCKET) /* create and keep a socket, to force initialization */
return SCPE_IERR; /* of socket library (e.g on Win32 call WSAStartup), else gethostbyname fails */
sprintf(sca_port, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port);
if (get_ipaddr(cptr, &ipaddr, NULL) != SCPE_OK) { /* try to parse hostname as dotted decimal nnn.nnn.nnn.nnn */
if ((he = gethostbyname(cptr)) == NULL) /* if not decimal, look up name through DNS */
return SCPE_OPENERR;
if ((ipaddr = * (unsigned long *) he->h_addr_list[0]) == INADDR_NONE)
return SCPE_OPENERR;
ipaddr = ntohl(ipaddr); /* convert to host byte order; gethostbyname() gives us network order */
}
if ((sca_sock = sim_connect_sock(ipaddr, sca_port)) == INVALID_SOCKET)
if ((sca_sock = sim_connect_sock(sca_port, NULL, NULL)) == INVALID_SOCKET)
return SCPE_OPENERR;
/* sim_connect_sock() sets socket to nonblocking before initiating the connect, so
* the connect is pending when it returns. For outgoing connections, the attach command should wait
* until the connection succeeds or fails. We use "accept" to wait and find out which way it goes...
* until the connection succeeds or fails. We use "sim_check_conn" to wait and find out which way it goes...
*/
FD_ZERO(&wr_set); /* we are only interested in info for sca_sock */
FD_ZERO(&err_set);
FD_SET(sca_sock, &wr_set);
FD_SET(sca_sock, &err_set);
while (0 == sim_check_conn(sca_sock, 0))/* wait for connection to complete or fail */
sim_os_ms_sleep(1000);
select(3, NULL, &wr_set, &err_set, NULL); /* wait for connection to complete or fail */
if (FD_ISSET(sca_sock, &wr_set)) { /* sca_sock appears in "writable" set -- connect completed */
sprintf(name, "%s:%d", cptr, sca_port);
if (1 == sim_check_conn(sca_sock, 0)) { /* sca_sock appears in "writable" set -- connect completed */
sprintf(name, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port);
sca_unit.filename = mstring(name);
SETBIT(sca_dsw, SCA_DSW_READY);
}
else if (FD_ISSET(sca_sock, &err_set)) { /* sca_sock appears in "error" set -- connect failed */
sim_close_sock(sca_sock, TRUE);
sca_sock = INVALID_SOCKET;
return SCPE_OPENERR;
}
else { /* if we get here my assumption about how select works is wrong */
printf("SCA_SOCK NOT FOUND IN WR_SET -OR- ERR_SET, CODING IN IBM1130_SCA IS WRONG\n");
else { /* sca_sock appears in "error" set -- connect failed */
sim_close_sock(sca_sock, TRUE);
sca_sock = INVALID_SOCKET;
return SCPE_OPENERR;
@ -610,22 +583,17 @@ static t_stat sca_detach (UNIT *uptr)
static void sca_check_connect (void)
{
uint32 ipaddr;
char name[100];
char *connectaddress;
if ((sca_sock = sim_accept_conn(sca_lsock, &ipaddr)) == INVALID_SOCKET)
if ((sca_sock = sim_accept_conn(sca_lsock, &connectaddress)) == INVALID_SOCKET)
return;
ipaddr = htonl(ipaddr); /* convert to network order so we can print it */
sprintf(name, "%d.%d.%d.%d", ipaddr & 0xFF, (ipaddr >> 8) & 0xFF, (ipaddr >> 16) & 0xFF, (ipaddr >> 24) & 0xFF);
printf("(SCA connection from %s)\n", name);
printf("(SCA connection from %s)\n", connectaddress);
if (sca_unit.filename != NULL)
free(sca_unit.filename);
sca_unit.filename = mstring(name);
sca_unit.filename = connectaddress;
SETBIT(sca_dsw, SCA_DSW_READY); /* indicate active connection */

2
Interdata/id16_cpu.c
View file

@ -604,7 +604,7 @@ while (reason == 0) { /* loop until halted */
int32 sr, st;
if (sim_interval <= 0) { /* check clock queue */
if (reason = sim_process_event ())
if ((reason = sim_process_event ()))
break;
int_eval ();
}

2
Interdata/id32_cpu.c
View file

@ -664,7 +664,7 @@ while (reason == 0) { /* loop until halted */
int32 sr, st;
if (sim_interval <= 0) { /* check clock queue */
if (reason = sim_process_event ())
if ((reason = sim_process_event ()))
break;
int_eval ();
}

4
Interdata/id_dp.c
View file

@ -419,7 +419,7 @@ switch (dp_cmd & 0x7) { /* case on func */
if (sch_actv (dp_dib.sch, dp_dib.dno)) { /* sch transfer? */
if (dp_dter (uptr, dp_1st)) /* check xfr err */
return SCPE_OK;
if (r = dp_rds (uptr)) /* read sec, err? */
if ((r = dp_rds (uptr))) /* read sec, err? */
return r;
dp_1st = 0;
t = sch_wrmem (dp_dib.sch, dpxb, DP_NUMBY); /* write to memory */
@ -438,7 +438,7 @@ switch (dp_cmd & 0x7) { /* case on func */
return SCPE_OK;
dp_bptr = sch_rdmem (dp_dib.sch, dpxb, DP_NUMBY); /* read from mem */
dp_db = dpxb[dp_bptr - 1]; /* last byte */
if (r = dp_wds (uptr)) /* write sec, err? */
if ((r = dp_wds (uptr))) /* write sec, err? */
return r;
dp_1st = 0;
if (sch_actv (dp_dib.sch, dp_dib.dno)) { /* more to do? */

6
Interdata/id_idc.c
View file

@ -96,7 +96,7 @@
/* Drive status, ^ = dynamic, * = in unit status */
#define STD_WRP 0x80 /* ^write prot */
/* 0x40 /* unused */
/* 0x40 *//* unused */
#define STD_ACH 0x20 /* alt chan busy NI */
#define STD_UNS 0x10 /* *unsafe */
#define STD_NRDY 0x08 /* ^not ready */
@ -576,7 +576,7 @@ switch (uptr->FNC & CMC_MASK) { /* case on func */
if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* sch transfer? */
if (idc_dter (uptr, idc_1st)) /* dte? done */
return SCPE_OK;
if (r = idc_rds (uptr)) /* read sec, err? */
if ((r = idc_rds (uptr))) /* read sec, err? */
return r;
idc_1st = 0;
t = sch_wrmem (idc_dib.sch, idcxb, IDC_NUMBY); /* write mem */
@ -595,7 +595,7 @@ switch (uptr->FNC & CMC_MASK) { /* case on func */
return SCPE_OK;
idc_bptr = sch_rdmem (idc_dib.sch, idcxb, IDC_NUMBY); /* read mem */
idc_db = idcxb[idc_bptr - 1]; /* last byte */
if (r = idc_wds (uptr)) /* write sec, err? */
if ((r = idc_wds (uptr))) /* write sec, err? */
return r;
idc_1st = 0;
if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* more to do? */

6
Interdata/id_io.c
View file

@ -358,7 +358,7 @@ if ((r != SCPE_OK) || (newmax == sch_max)) /* err or no chg? */
if (newmax == 0) /* must be > 0 */
return SCPE_ARG;
if (newmax < sch_max) { /* reducing? */
for (i = 0; dptr = sim_devices[i]; i++) { /* loop thru dev */
for (i = 0; (dptr = sim_devices[i]); i++) { /* loop thru dev */
dibp = (DIB *) dptr->ctxt; /* get DIB */
if (dibp && (dibp->sch >= (int32) newmax)) { /* dev using chan? */
printf ("Device %02X uses channel %d\n",
@ -439,7 +439,7 @@ int32 i, j, t;
uint32 r;
for (i = t = 0; i < INTSZ; i++) { /* loop thru array */
if (r = int_req[i] & int_enb[i]) { /* find nz int wd */
if ((r = int_req[i] & int_enb[i])) { /* find nz int wd */
for (j = 0; j < 32; t++, j++) {
if (r & (1u << j)) {
int_req[i] = int_req[i] & ~(1u << j); /* clr request */
@ -630,7 +630,7 @@ for (i = 0; i < (DEVNO / 32); i++)
/* Test each device for conflict; add to map; init tables */
for (i = 0; dptr = sim_devices[i]; i++) { /* loop thru devices */
for (i = 0; (dptr = sim_devices[i]); i++) { /* loop thru devices */
dibp = (DIB *) dptr->ctxt; /* get DIB */
if ((dibp == NULL) || (dptr->flags & DEV_DIS)) /* exist, enabled? */
continue;

6
Interdata/id_mt.c
View file

@ -368,13 +368,13 @@ switch (uptr->UCMD) { /* case on function */
}
if (mt_bptr) { /* any chars? */
if (st = sim_tape_wrrecf (uptr, mtxb, mt_bptr)) /* write, err? */
if ((st = sim_tape_wrrecf (uptr, mtxb, mt_bptr)))/* write, err? */
r = mt_map_err (uptr, st); /* map error */
}
break; /* record done */
case MTC_WEOF: /* write eof */
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
r = mt_map_err (uptr, st); /* map error */
mt_sta = mt_sta | STA_EOF; /* set eof */
if (mt_arm[u]) /* set intr */
@ -402,7 +402,7 @@ switch (uptr->UCMD) { /* case on function */
break;
case MTC_SPCR: /* backspace */
if (st = sim_tape_sprecr (uptr, &tbc)) /* skip rec rev, err? */
if ((st = sim_tape_sprecr (uptr, &tbc))) /* skip rec rev, err? */
r = mt_map_err (uptr, st); /* map error */
break;
} /* end case */

2
Interdata/id_pas.c
View file

@ -334,7 +334,7 @@ if (ln >= 0) { /* got one? */
tmxr_poll_rx (&pas_desc); /* poll for input */
for (ln = 0; ln < PAS_ENAB; ln++) { /* loop thru lines */
if (pas_ldsc[ln].conn) { /* connected? */
if (c = tmxr_getc_ln (&pas_ldsc[ln])) { /* any char? */
if ((c = tmxr_getc_ln (&pas_ldsc[ln]))) { /* any char? */
pas_sta[ln] = pas_sta[ln] & ~(STA_FR | STA_PF);
if (pas_rchp[ln])
pas_sta[ln] = pas_sta[ln] | STA_OVR;

6
LGP/lgp_cpu.c
View file

@ -288,7 +288,7 @@ if (lgp21_sov) { /* stop sense pending? *
do {
if (sim_interval <= 0) { /* check clock queue */
if (r = sim_process_event ())
if ((r = sim_process_event ()))
break;
}
@ -308,7 +308,7 @@ do {
PC = (PC + 1) & AMASK; /* increment PC */
sim_interval = sim_interval - 1;
if (r = cpu_one_inst (oPC, IR)) { /* one instr; error? */
if ((r = cpu_one_inst (oPC, IR))) { /* one instr; error? */
if (r == STOP_STALL) { /* stall? */
PC = oPC; /* back up PC */
delay = r = 0; /* no delay */
@ -744,7 +744,7 @@ if (cptr) {
else inst = IR;
while ((r = cpu_one_inst (PC, inst)) == STOP_STALL) {
sim_interval = 0;
if (r = sim_process_event ())
if ((r = sim_process_event ()))
return r;
}
return r;

6
LGP/lgp_stddev.c
View file

@ -394,7 +394,7 @@ t_stat ttr_svc (UNIT *uptr)
{
t_stat r;
if (r = read_reader (uptr, ttr_stopioe, (int32 *) &tti_buf))
if ((r = read_reader (uptr, ttr_stopioe, (int32 *) &tti_buf)))
return r;
if (!(uptr->flags & UNIT_NOCS) && /* cstop enable? */
(tti_buf == FLEX_CSTOP)) /* cond stop? */
@ -415,7 +415,7 @@ t_stat ptr_svc (UNIT *uptr)
{
t_stat r;
if (r = read_reader (uptr, ptr_stopioe, &uptr->buf))
if ((r = read_reader (uptr, ptr_stopioe, &uptr->buf)))
return r;
if (uptr->buf == FLEX_CSTOP) /* cond stop? */
inp_done = 1;
@ -548,7 +548,7 @@ else {
ch = '\b';
else ch = flex_to_ascii[flex | (tto_uc << 6)]; /* cvt flex to ascii */
if (ch > 0) { /* legit? */
if (r = sim_putchar_s (ch)) /* write char */
if ((r = sim_putchar_s (ch))) /* write char */
return r;
tto_unit[0].pos = tto_unit[0].pos + 1;
if (flex == FLEX_CR) { /* cr? */

4
LGP/lgp_sys.c
View file

@ -363,7 +363,7 @@ if ((sw & SWMASK ('L')) || /* LGP hex? */
return SCPE_OK;
if (islower (c))
c = toupper (c);
if (tptr = strchr (hex_decode, c))
if ((tptr = strchr (hex_decode, c)))
val[0] = (val[0] << 4) | (tptr - hex_decode);
else return SCPE_ARG;
}
@ -388,7 +388,7 @@ else sgn = 0;
cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
if (gbuf[1] != 0)
return SCPE_ARG;
if (tptr = strchr (opcode, gbuf[0]))
if ((tptr = strchr (opcode, gbuf[0])))
val[0] = ((tptr - opcode) << I_V_OP) | sgn; /* merge opcode */
else return SCPE_ARG;
cptr = get_glyph (cptr, gbuf, 0); /* get address */

2
NOVA/eclipse_cpu.c
View file

@ -744,7 +744,7 @@ if (MapInit == 0) {
while (reason == 0) { /* loop until halted */
if (sim_interval <= 0) { /* check clock queue */
if (reason = sim_process_event ())
if ((reason = sim_process_event ()))
break;
}

9
NOVA/nova_dkp.c
View file

@ -25,6 +25,7 @@
dkp moving head disk
27-Apr-12 RMS Changed ??? string digraphs to ?, per C rules
04-Jul-04 BKR device name changed to DG's DKP from DEC's DP,
DEV_SET/CLR/INTR macro use started,
fixed 'P' pulse code and secret quirks,
@ -706,7 +707,7 @@ if ( DKP_TRACE(1) )
"write"
: ((uptr->FUNC == FCCY_SEEK) ?
"seek"
: "<???>"
: "<?>"
)
)
),
@ -871,7 +872,7 @@ do {
"read"
: ((uptr->FUNC == FCCY_WRITE) ?
"write"
: "<???>")
: "<?>")
),
(unsigned) (uptr->CYL),
(unsigned) (GET_SURF(dkp_ussc, dtype)),
@ -908,7 +909,7 @@ do {
if (uptr->FUNC == FCCY_READ) { /* read? */
awc = fxread (tbuf, sizeof(uint16), DKP_NUMWD, uptr->fileref);
for ( ; awc < DKP_NUMWD; awc++) tbuf[awc] = 0;
if (err = ferror (uptr->fileref))
if ((err = ferror (uptr->fileref)))
break;
for (dx = 0; dx < DKP_NUMWD; dx++) { /* loop thru buffer */
pa = MapAddr (dkp_map, (dkp_ma & AMASK));
@ -924,7 +925,7 @@ do {
dkp_ma = (dkp_ma + 1) & AMASK;
}
fxwrite (tbuf, sizeof(int16), DKP_NUMWD, uptr->fileref);
if (err = ferror (uptr->fileref))
if ((err = ferror (uptr->fileref)))
break;
}

16
NOVA/nova_mta.c
View file

@ -412,7 +412,7 @@ else switch (c) { /* case on command */
mtxb[p++] = M[pa] & 0377;
mta_ma = (mta_ma + 1) & AMASK;
}
if (st = sim_tape_wrrecf (uptr, mtxb, tbc)) { /* write rec, err? */
if ((st = sim_tape_wrrecf (uptr, mtxb, tbc))) { /* write rec, err? */
r = mta_map_err (uptr, st); /* map error */
mta_ma = (mta_ma - wc) & AMASK; /* restore wc */
}
@ -421,7 +421,7 @@ else switch (c) { /* case on command */
break;
case CU_WREOF: /* write eof */
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
r = mta_map_err (uptr, st); /* map error */
else mta_upddsta (uptr, uptr->USTAT | STA_EOF | STA_RDY);
break;
@ -435,7 +435,7 @@ else switch (c) { /* case on command */
case CU_SPACEF: /* space forward */
do {
mta_wc = (mta_wc + 1) & DMASK; /* incr wc */
if (st = sim_tape_sprecf (uptr, &tbc)) { /* space rec fwd, err? */
if ((st = sim_tape_sprecf (uptr, &tbc))) { /* space rec fwd, err? */
r = mta_map_err (uptr, st); /* map error */
break;
}
@ -447,7 +447,7 @@ else switch (c) { /* case on command */
case CU_SPACER: /* space reverse */
do {
mta_wc = (mta_wc + 1) & DMASK; /* incr wc */
if (st = sim_tape_sprecr (uptr, &tbc)) { /* space rec rev, err? */
if ((st = sim_tape_sprecr (uptr, &tbc))) { /* space rec rev, err? */
r = mta_map_err (uptr, st); /* map error */
break;
}
@ -493,10 +493,10 @@ if ((uptr->flags & UNIT_ATT) == 0) /* offline? */
change = (uptr->USTAT ^ newsta) & STA_MON; /* changes? */
uptr->USTAT = newsta & STA_DYN; /* update status */
if (change) {
/* if (mta_ep) { /* if polling */
/* u = uptr - mta_dev.units; /* unit num */
/* mta_sta = (mta_sta & ~STA_UNIT) | (u << STA_V_UNIT);
/* set polling interupt...
/* if (mta_ep) { *//* if polling */
/* u = uptr - mta_dev.units; *//* unit num */
/* mta_sta = (mta_sta & ~STA_UNIT) | (u << STA_V_UNIT); */
/* set polling interupt... */
/* } */
mta_sta = mta_sta | STA_CHG; /* flag change */
}

2
NOVA/nova_tt1.c
View file

@ -184,7 +184,7 @@ int32 temp, newln;
if (tt1_ldsc.conn) { /* connected? */
tmxr_poll_rx (&tt_desc); /* poll for input */
if (temp = tmxr_getc_ln (&tt1_ldsc)) { /* get char */
if ((temp = tmxr_getc_ln (&tt1_ldsc))) { /* get char */
uptr->buf = temp & 0177;
if ((uptr->flags & UNIT_DASHER) &&
(uptr->buf == '\r'))

96
PDP1/pdp1_cpu.c
View file

@ -546,7 +546,7 @@ reason = 0;
while (reason == 0) { /* loop until halted */
if (sim_interval <= 0) { /* check clock queue */
if (reason = sim_process_event ())
if ((reason = sim_process_event ()))
break;
sbs_lvl = sbs_eval (); /* eval sbs system */
}
@ -610,25 +610,25 @@ while (reason == 0) { /* loop until halted */
/* Logical, load, store instructions */
case 001: /* AND */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
AC = AC & MB;
break;
case 002: /* IOR */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
AC = AC | MB;
break;
case 003: /* XOR */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
AC = AC ^ MB;
break;
@ -638,9 +638,9 @@ while (reason == 0) { /* loop until halted */
reason = STOP_XCT;
break;
}
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
xct_count = xct_count + 1; /* count XCT's */
IR = MB; /* get instruction */
@ -648,9 +648,9 @@ while (reason == 0) { /* loop until halted */
case 005: /* LCH */
if (cpu_unit.flags & UNIT_1D) { /* PDP-1D? */
if (reason = Ea_ch (IR, &byno)) /* MA <- eff addr */
if ((reason = Ea_ch (IR, &byno))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
AC = (MB << byt_shf[byno]) & 0770000; /* extract byte */
}
@ -659,9 +659,9 @@ while (reason == 0) { /* loop until halted */
case 006: /* DCH */
if (cpu_unit.flags & UNIT_1D) { /* PDP-1D? */
if (reason = Ea_ch (IR, &byno)) /* MA <- eff addr */
if ((reason = Ea_ch (IR, &byno))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
MB = (MB & ~(0770000 >> byt_shf[byno])) | /* insert byte */
((AC & 0770000) >> byt_shf[byno]);
@ -683,55 +683,55 @@ while (reason == 0) { /* loop until halted */
break;
case 010: /* LAC */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
AC = MB;
break;
case 011: /* LIO */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
IO = MB;
break;
case 012: /* DAC */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
MB = AC;
reason = Write ();
break;
case 013: /* DAP */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
MB = (AC & DAMASK) | (MB & ~DAMASK);
reason = Write ();
break;
case 014: /* DIP */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
MB = (AC & ~DAMASK) | (MB & DAMASK);
reason = Write ();
break;
case 015: /* DIO */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
MB = IO;
reason = Write ();
break;
case 016: /* DZM */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
MB = 0;
reason = Write ();
@ -755,9 +755,9 @@ while (reason == 0) { /* loop until halted */
case 017: /* TAD */
if (cpu_unit.flags & UNIT_1D) { /* PDP-1D? */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
AC = AC + MB + ((PF & PF_L)? 1: 0); /* AC + opnd + L */
if (AC > DMASK) /* carry? set L */
@ -769,9 +769,9 @@ while (reason == 0) { /* loop until halted */
break;
case 020: /* ADD */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
t = AC;
AC = AC + MB;
@ -784,9 +784,9 @@ while (reason == 0) { /* loop until halted */
break;
case 021: /* SUB */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
t = AC ^ DMASK; /* complement AC */
AC = t + MB; /* -AC + MB */
@ -798,9 +798,9 @@ while (reason == 0) { /* loop until halted */
break;
case 022: /* IDX */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
AC = MB + 1;
if (AC >= DMASK)
@ -810,9 +810,9 @@ while (reason == 0) { /* loop until halted */
break;
case 023: /* ISP */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
AC = MB + 1;
if (AC >= DMASK)
@ -824,18 +824,18 @@ while (reason == 0) { /* loop until halted */
break;
case 024: /* SAD */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
if (AC != MB)
PC = INCR_ADDR (PC);
break;
case 025: /* SAS */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
if (AC == MB)
PC = INCR_ADDR (PC);
@ -863,7 +863,7 @@ while (reason == 0) { /* loop until halted */
hst[hst_p].ea = PC;
}
else { /* normal JMP */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
PCQ_ENTRY;
PC = MA;
@ -871,7 +871,7 @@ while (reason == 0) { /* loop until halted */
break;
case 031: /* JSP */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
AC = EPC_WORD;
PCQ_ENTRY;
@ -889,9 +889,9 @@ while (reason == 0) { /* loop until halted */
*/
case 026: /* MUL */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
if (cpu_unit.flags & UNIT_MDV) { /* hardware? */
sign = AC ^ MB; /* result sign */
@ -919,9 +919,9 @@ while (reason == 0) { /* loop until halted */
break;
case 027: /* DIV */
if (reason = Ea (IR)) /* MA <- eff addr */
if ((reason = Ea (IR))) /* MA <- eff addr */
break;
if (reason = Read ()) /* MB <- data */
if ((reason = Read ())) /* MB <- data */
break;
if (cpu_unit.flags & UNIT_MDV) { /* hardware */
sign = AC ^ MB; /* result sign */
@ -1362,13 +1362,13 @@ t_stat r;
MA = (PC & EPCMASK) | (IR & DAMASK); /* direct address */
if (IR & IA) { /* indirect addr? */
if (extm) { /* extend? */
if (r = Read ()) /* read; err? */
if ((r = Read ())) /* read; err? */
return r;
MA = MB & AMASK; /* one level */
}
else { /* multi-level */
for (i = 0; i < ind_max; i++) { /* count indirects */
if (r = Read ()) /* get ind word */
if ((r = Read ())) /* get ind word */
return r;
MA = (PC & EPCMASK) | (MB & DAMASK);
if ((MB & IA) == 0)
@ -1392,12 +1392,12 @@ t_stat r;
MA = (PC & EPCMASK) | (IR & DAMASK); /* direct address */
if (extm) { /* extend? */
if (r = Read ()) /* read; err? */
if ((r = Read ())) /* read; err? */
return r;
}
else { /* multi-level */
for (i = 0; i < ind_max; i++) { /* count indirects */
if (r = Read ()) /* get ind word */
if ((r = Read ())) /* get ind word */
return r;
if ((MB & IA) == 0)
break;

2
PDP1/pdp1_dcs.c
View file

@ -251,7 +251,7 @@ if (ln >= 0) { /* got one? */
tmxr_poll_rx (&dcs_desc); /* poll for input */
for (ln = 0; ln < DCS_NUMLIN; ln++) { /* loop thru lines */
if (dcs_ldsc[ln].conn) { /* connected? */
if (c = tmxr_getc_ln (&dcs_ldsc[ln])) { /* get char */
if ((c = tmxr_getc_ln (&dcs_ldsc[ln]))) { /* get char */
if (c & SCPE_BREAK) /* break? */
c = 0;
else c = sim_tt_inpcvt (c, TT_GET_MODE (dcsl_unit[ln].flags)|TTUF_KSR);

30
PDP10/pdp10_cpu.c
View file

@ -705,7 +705,7 @@ pager_tc = FALSE; /* not in trap cycle */
pflgs = 0; /* not in PXCT */
xct_cnt = 0; /* count XCT's */
if (sim_interval <= 0) { /* check clock queue */
if (i = sim_process_event ()) /* error? stop sim */
if ((i = sim_process_event ())) /* error? stop sim */
ABORT (i);
pi_eval (); /* eval pi system */
}
@ -719,7 +719,7 @@ if (sim_interval <= 0) { /* check clock queue */
if (qintr) {
int32 vec, uba;
pager_pi = TRUE; /* flag in pi seq */
if (vec = pi_ub_vec (qintr, &uba)) { /* Unibus interrupt? */
if ((vec = pi_ub_vec (qintr, &uba))) { /* Unibus interrupt? */
mb = ReadP (epta + EPT_UBIT + uba); /* get dispatch table */
if (mb == 0) /* invalid? stop */
ABORT (STOP_ZERINT);
@ -865,8 +865,8 @@ case 0037: Write (040, UUOWORD, MM_CUR); /* store op, ac, ea */
/* Floating point, bytes, multiple precision (0100 - 0177) */
/* case 0100: MUUO /* UJEN */
/* case 0101: MUUO /* unassigned */
/* case 0100: MUUO *//* UJEN */
/* case 0101: MUUO *//* unassigned */
case 0102: if (Q_ITS && !TSTF (F_USR)) { /* GFAD (KL), XCTRI (ITS) */
inst = Read (ea, MM_OPND);
pflgs = pflgs | ac;
@ -879,10 +879,10 @@ case 0103: if (Q_ITS && !TSTF (F_USR)) { /* GFSB (KL), XCTR (ITS)
goto XCT;
}
goto MUUO;
/* case 0104: MUUO /* JSYS (T20) */
/* case 0104: MUUO *//* JSYS (T20) */
case 0105: AC(ac) = adjsp (AC(ac), ea); break; /* ADJSP */
/* case 0106: MUUO /* GFMP (KL)*/
/* case 0107: MUUO /* GFDV (KL) */
/* case 0106: MUUO *//* GFMP (KL)*/
/* case 0107: MUUO *//* GFDV (KL) */
case 0110: RD2; dfad (ac, rs, 0); break; /* DFAD */
case 0111: RD2; dfad (ac, rs, 1); break; /* DFSB */
case 0112: RD2; dfmp (ac, rs); break; /* DFMP */
@ -909,8 +909,8 @@ case 0124: G2AC; WR2; break; /* DMOVEM */
case 0125: G2AC; DMOVN (rs); WR2; DMOVNF; break; /* DMOVNM */
case 0126: RD; fix (ac, mb, 1); break; /* FIXR */
case 0127: RD; AC(ac) = fltr (mb); break; /* FLTR */
/* case 0130: MUUO /* UFA */
/* case 0131: MUUO /* DFN */
/* case 0130: MUUO *//* UFA */
/* case 0131: MUUO *//* DFN */
case 0132: AC(ac) = fsc (AC(ac), ea); break; /* FSC */
case 0133: if (!ac) /* IBP */
ibp (ea, pflgs);
@ -920,7 +920,7 @@ case 0135: LDB; break; /* LDB */
case 0136: CIBP; DPB; CLRF (F_FPD); break; /* IDBP */
case 0137: DPB; break; /* DPB */
case 0140: RD; AC(ac) = FAD (mb); break; /* FAD */
/* case 0141: MUUO /* FADL */
/* case 0141: MUUO *//* FADL */
case 0142: RM; mb = FAD (mb); WR; break; /* FADM */
case 0143: RM; AC(ac) = FAD (mb); WRAC; break; /* FADB */
case 0144: RD; AC(ac) = FADR (mb); break; /* FADR */
@ -928,7 +928,7 @@ case 0145: AC(ac) = FADR (IMS); break; /* FADRI */
case 0146: RM; mb = FADR (mb); WR; break; /* FADRM */
case 0147: RM; AC(ac) = FADR (mb); WRAC; break; /* FADRB */
case 0150: RD; AC(ac) = FSB (mb); break; /* FSB */
/* case 0151: MUUO /* FSBL */
/* case 0151: MUUO *//* FSBL */
case 0152: RM; mb = FSB (mb); WR; break; /* FSBM */
case 0153: RM; AC(ac) = FSB (mb); WRAC; break; /* FSBB */
case 0154: RD; AC(ac) = FSBR (mb); break; /* FSBR */
@ -936,7 +936,7 @@ case 0155: AC(ac) = FSBR (IMS); break; /* FSBRI */
case 0156: RM; mb = FSBR (mb); WR; break; /* FSBRM */
case 0157: RM; AC(ac) = FSBR (mb); WRAC; break; /* FSBRB */
case 0160: RD; AC(ac) = FMP (mb); break; /* FMP */
/* case 0161: MUUO /* FMPL */
/* case 0161: MUUO *//* FMPL */
case 0162: RM; mb = FMP (mb); WR; break; /* FMPM */
case 0163: RM; AC(ac) = FMP (mb); WRAC; break; /* FMPB */
case 0164: RD; AC(ac) = FMPR (mb); break; /* FMPR */
@ -944,7 +944,7 @@ case 0165: AC(ac) = FMPR (IMS); break; /* FMPRI */
case 0166: RM; mb = FMPR (mb); WR; break; /* FMPRM */
case 0167: RM; AC(ac) = FMPR (mb); WRAC; break; /* FMPRB */
case 0170: RD; if (FDV (mb)) S1AC; break; /* FDV */
/* case 0171: MUUO /* FDVL */
/* case 0171: MUUO *//* FDVL */
case 0172: RM; if (FDV (mb)) WR1; break; /* FDVM */
case 0173: RM; if (FDV (mb)) { S1AC; WRAC; } break; /* FDVB */
case 0174: RD; if (FDVR (mb)) S1AC; break; /* FDVR */
@ -1008,7 +1008,7 @@ case 0250: RM; WRAC; AC(ac) = mb; break; /* EXCH */
case 0251: blt (ac, ea, pflgs); break; /* BLT */
case 0252: AOBAC; if (TGE (AC(ac))) JUMP (ea); break; /* AOBJP */
case 0253: AOBAC; if (TL (AC(ac))) JUMP (ea); break; /* AOBJN */
/* case 0254: /* shown later /* JRST */
/* case 0254: *//* shown later *//* JRST */
case 0255: if (flags & (ac << 14)) { /* JFCL */
JUMP (ea);
CLRF (ac << 14);
@ -2019,7 +2019,7 @@ int32 test_int (void)
int32 t;
if (sim_interval <= 0) { /* check queue */
if (t = sim_process_event ()) /* IO event? */
if ((t = sim_process_event ())) /* IO event? */
return t;
if (pi_eval ()) /* interrupt? */
return (INTERRUPT);

4
PDP10/pdp10_defs.h
View file

@ -587,9 +587,9 @@ typedef t_int64 d10; /* PDP-10 data (36b) */
/* Unibus I/O constants */
#define READ 0 /* PDP11 compatible */
/* #define READC 1 /* console read */
/* #define READC 1 *//* console read */
#define WRITE 2
/* #define WRITEC 3 /* console write */
/* #define WRITEC 3 *//* console write */
#define WRITEB 4
#define IO_V_UBA 18 /* UBA in I/O addr */
#define IO_N_UBA 16 /* max num of UBA's */

4
PDP10/pdp10_ksio.c
View file

@ -401,7 +401,7 @@ uint32 pa = (uint32) ea;
int32 i, n, val;
DIB *dibp;
for (i = 0; dibp = dib_tab[i]; i++ ) {
for (i = 0; (dibp = dib_tab[i]); i++ ) {
if ((pa >= dibp->ba) &&
(pa < (dibp->ba + dibp->lnt))) {
dibp->rd (&val, pa, READ);
@ -418,7 +418,7 @@ uint32 pa = (uint32) ea;
int32 i, n;
DIB *dibp;
for (i = 0; dibp = dib_tab[i]; i++ ) {
for (i = 0; (dibp = dib_tab[i]); i++ ) {
if ((pa >= dibp->ba) &&
(pa < (dibp->ba + dibp->lnt))) {
dibp->wr ((int32) val, pa, mode);

10
PDP10/pdp10_lp20.c
View file

@ -58,10 +58,10 @@
#define TX_DMASK 07777
#define TX_V_FL 8 /* flags */
#define TX_M_FL 017
/* define TX_INTR 04000 /* interrupt */
/* define TX_INTR 04000 *//* interrupt */
#define TX_DELH 02000 /* delimiter */
/* define TX_XLAT 01000 /* translate */
/* define TX_DVFU 00400 /* DAVFU */
/* define TX_XLAT 01000 *//* translate */
/* define TX_DVFU 00400 *//* DAVFU */
#define TX_SLEW 00020 /* chan vs slew */
#define TX_VMASK 00017 /* spacing mask */
#define TX_CHR 0 /* states: pr char */
@ -563,7 +563,7 @@ lp20_unit.pos = ftell (lp20_unit.fileref); /* print 'n' newlines */
if (dvuadv) /* update DAVFU ptr */
dvptr = (dvptr + cnt) % dvlnt;
if (davfu[dvptr] & (1 << DV_TOF)) { /* at top of form? */
if (lppagc = (lppagc - 1) & PAGC_MASK) { /* decr page cntr */
if ((lppagc = (lppagc - 1) & PAGC_MASK)) { /* decr page cntr */
lpcsa = lpcsa & ~CSA_PZRO; /* update status */
return TRUE;
}
@ -592,7 +592,7 @@ for (i = 0; i < dvlnt; i++) { /* search DAVFU */
lp20_adv (1, FALSE);
fputc ('\f', lp20_unit.fileref); /* print form feed */
lp20_unit.pos = ftell (lp20_unit.fileref);
if (lppagc = (lppagc - 1) & PAGC_MASK) { /* decr page cntr */
if ((lppagc = (lppagc - 1) & PAGC_MASK)) { /* decr page cntr */
lpcsa = lpcsa & ~CSA_PZRO; /* update status */
return TRUE;
}

2
PDP10/pdp10_mdfp.c
View file

@ -493,7 +493,7 @@ if (a.fhi >= 2 * b.fhi) { /* will divide work? */
SETF (F_AOV | F_DCK | F_FOV | F_T1);
return FALSE;
}
if (savhi = a.fhi) { /* dvd = 0? quo = 0 */
if ((savhi = a.fhi)) { /* dvd = 0? quo = 0 */
a.sign = a.sign ^ b.sign; /* result sign */
a.exp = a.exp - b.exp + FP_BIAS + 1; /* result exponent */
a.fhi = a.fhi / (b.fhi >> (FP_N_FHI + 1)); /* do divide */

2
PDP10/pdp10_rp.c
View file

@ -951,7 +951,7 @@ switch (uptr->FUNC) { /* case on function */
if ((rpcs2 & CS2_UAI) == 0)
ba = ba + 4;
}
if (fc10 = twc10 & (RP_NUMWD - 1)) { /* fill? */
if ((fc10 = twc10 & (RP_NUMWD - 1))) { /* fill? */
fc10 = RP_NUMWD - fc10;
for (i = 0; i < fc10; i++)
dbuf[twc10 + i] = 0;

2
PDP10/pdp10_sys.c
View file

@ -118,7 +118,7 @@ const char *sim_stop_messages[] = {
#define EXE_DIR 01776 /* EXE directory */
#define EXE_VEC 01775 /* EXE entry vec */
#define EXE_PDV 01774 /* EXE ignored */
#define EXE_END 01777 /* EXE end
#define EXE_END 01777 /* EXE end */
/* RIM10 loader

12
PDP10/pdp10_tu.c
View file

@ -833,7 +833,7 @@ switch (fnc) { /* case on function */
case FNC_SPACEF: /* space forward */
do {
tufc = (tufc + 1) & 0177777; /* incr fc */
if (st = sim_tape_sprecf (uptr, &tbc)) { /* space rec fwd, err? */
if ((st = sim_tape_sprecf (uptr, &tbc))) { /* space rec fwd, err? */
r = tu_map_err (uptr, st, 0); /* map error */
break;
}
@ -847,7 +847,7 @@ switch (fnc) { /* case on function */
case FNC_SPACER: /* space reverse */
do {
tufc = (tufc + 1) & 0177777; /* incr wc */
if (st = sim_tape_sprecr (uptr, &tbc)) { /* space rec rev, err? */
if ((st = sim_tape_sprecr (uptr, &tbc))) { /* space rec rev, err? */
r = tu_map_err (uptr, st, 0); /* map error */
break;
}
@ -859,7 +859,7 @@ switch (fnc) { /* case on function */
break;
case FNC_WREOF: /* write end of file */
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
r = tu_map_err (uptr, st, 0); /* map error */
tufs = tufs | FS_ATA;
break;
@ -889,7 +889,7 @@ switch (fnc) { /* case on function */
if ((uptr->UDENS == TC_1600) && sim_tape_bot (uptr))
tufs = tufs | FS_ID; /* PE BOT? ID burst */
TXFR (ba, wc, 0); /* validate transfer */
if (st = sim_tape_rdrecf (uptr, xbuf, &tbc, MT_MAXFR)) { /* read fwd */
if ((st = sim_tape_rdrecf (uptr, xbuf, &tbc, MT_MAXFR))) {/* read fwd */
if (st == MTSE_TMK) /* TMK also sets FCE */
set_tuer (ER_FCE);
r = tu_map_err (uptr, st, 1); /* map error */
@ -936,7 +936,7 @@ switch (fnc) { /* case on function */
} /* end for */
if (j < fc) /* short record? */
fc = j;
if (st = sim_tape_wrrecf (uptr, xbuf, fc)) /* write rec, err? */
if ((st = sim_tape_wrrecf (uptr, xbuf, fc))) /* write rec, err? */
r = tu_map_err (uptr, st, 1); /* map error */
else {
tufc = (tufc + fc) & 0177777;
@ -951,7 +951,7 @@ switch (fnc) { /* case on function */
case FNC_WCHKR: /* wcheck = read */
tufc = 0; /* clear frame count */
TXFR (ba, wc, 1); /* validate xfer rev */
if (st = sim_tape_rdrecr (uptr, xbuf + 4, &tbc, MT_MAXFR)) { /* read rev */
if ((st = sim_tape_rdrecr (uptr, xbuf + 4, &tbc, MT_MAXFR))) {/* read rev */
if (st == MTSE_TMK) /* TMK also sets FCE */
set_tuer (ER_FCE);
r = tu_map_err (uptr, st, 1); /* map error */

8
PDP11/pdp11_cis.c
View file

@ -1134,7 +1134,7 @@ switch (op) { /* case on opcode */
result = (A2ADR << 16) | A2LNT; /* op in VAX format */
CVTLx:
dst = Dstr0; /* clear result */
if (dst.sign = GET_SIGN_L (result))
if ((dst.sign = GET_SIGN_L (result)))
result = (~result + 1) & 0xFFFFFFFF;
for (i = 1; (i < (DSTRLNT * 8)) && result; i++) {
digit = result % 10;
@ -1267,7 +1267,7 @@ for (i = 0; i < DSTRLNT; i++) { /* loop thru value */
mask = 0xFFFFFFFF;
if (dst->val[i] & mask) /* test for ovflo */
V = 1;
if (dst->val[i] = dst->val[i] & ~mask) /* test nz */
if ((dst->val[i] = dst->val[i] & ~mask)) /* test nz */
Z = 0;
}
dst->sign = dst->sign & ~unsignedtab[type] & ~(Z & ~V);
@ -1523,7 +1523,7 @@ uint32 NibbleRshift (DSTR *dsrc, int32 sc, uint32 cin)
{
int32 i, s, nc;
if (s = sc * 4) {
if ((s = sc * 4)) {
for (i = DSTRMAX; i >= 0; i--) {
nc = (dsrc->val[i] << (32 - s)) & 0xFFFFFFFF;
dsrc->val[i] = ((dsrc->val[i] >> s) |
@ -1548,7 +1548,7 @@ int32 i, s;
uint32 nc, cin;
cin = 0;
if (s = sc * 4) {
if ((s = sc * 4)) {
for (i = 0; i < DSTRLNT; i++) {
nc = dsrc->val[i] >> (32 - s);
dsrc->val[i] = ((dsrc->val[i] << s) | cin) & 0xFFFFFFFF;

5
PDP11/pdp11_cpu.c
View file

@ -25,6 +25,7 @@
cpu PDP-11 CPU
29-Apr-12 RMS Fixed compiler warning (Mark Pizzolato)
19-Mar-12 RMS Fixed declaration of sim_switches (Mark Pizzolato)
29-Dec-08 RMS Fixed failure to clear cpu_bme on RESET (Walter Mueller)
22-Apr-08 RMS Fixed MMR0 treatment in RESET (Walter Mueller)
@ -731,7 +732,7 @@ while (reason == 0) {
if (trap_req) { /* check traps, ints */
trapea = 0; /* assume srch fails */
if (t = trap_req & TRAP_ALL) { /* if a trap */
if ((t = trap_req & TRAP_ALL)) { /* if a trap */
for (trapnum = 0; trapnum < TRAP_V_MAX; trapnum++) {
if ((t >> trapnum) & 1) { /* trap set? */
trapea = trap_vec[trapnum]; /* get vec, clr */
@ -1292,7 +1293,7 @@ while (reason == 0) {
break;
case 070: /* CSM */
if (CPUT (HAS_CSM) && (MMR3 & MMR3_CSM) || (cm != MD_KER)) {
if ((CPUT (HAS_CSM) && (MMR3 & MMR3_CSM)) || (cm != MD_KER)) {
dst = dstreg? R[dstspec]: ReadW (GeteaW (dstspec));
PSW = get_PSW () & ~PSW_CC; /* PSW, cc = 0 */
STACKFILE[cm] = SP;

2
PDP11/pdp11_cpumod.c
View file

@ -1075,7 +1075,7 @@ t_stat r;
for (i = 0; cnf_tab[i].dib != NULL; i++) { /* loop thru config tab */
if (((cnf_tab[i].cpum == 0) || (cpu_type & cnf_tab[i].cpum)) &&
((cnf_tab[i].optm == 0) || (cpu_opt & cnf_tab[i].optm))) {
if (r = build_ubus_tab (&cpu_dev, cnf_tab[i].dib)) /* add to dispatch tab */
if ((r = build_ubus_tab (&cpu_dev, cnf_tab[i].dib)))/* add to dispatch tab */
return r;
}
}

2
PDP11/pdp11_dl.c
View file

@ -346,7 +346,7 @@ if (ln >= 0) { /* got one? rcv enb */
tmxr_poll_rx (&dlx_desc); /* poll for input */
for (ln = 0; ln < DLX_LINES; ln++) { /* loop thru lines */
if (dlx_ldsc[ln].conn) { /* connected? */
if (temp = tmxr_getc_ln (&dlx_ldsc[ln])) { /* get char */
if ((temp = tmxr_getc_ln (&dlx_ldsc[ln]))) { /* get char */
if (temp & SCPE_BREAK) /* break? */
c = DLIBUF_ERR|DLIBUF_RBRK;
else c = sim_tt_inpcvt (temp, TT_GET_MODE (dlo_unit[ln].flags));

2273
PDP11/pdp11_dmc.c Normal file
View file

File diff suppressed because it is too large Load diff

132
PDP11/pdp11_dmc.h Normal file
View file

@ -0,0 +1,132 @@
/* pdp11_dmc.h: DMC11 Emulation
------------------------------------------------------------------------------
Copyright (c) 2011, Robert M. A. Jarratt
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of the author shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the author.
------------------------------------------------------------------------------*/
// Notes
// Base address needs to be 760060 according to DMC11 manual, but SYSGEN seems to think CSR is 0760100. However if I use
// 0760100 I get a conflict with the DZ because the first 13 bits are still 00100. If I use 760060 VMS sees the XM device, but
// if I remove the DZ to prevent the conflict VMS does not see an XM device, but I do get lots of reads and writes, possibly
// because it thinks it is a different device. What worries me more though is that there seems to be overlap in the 13-bit base
// addresses of the DZ and DMC.
#ifndef _PDP11_DMC_H
#define _PDP11_DMC_H
#if defined (VM_VAX) /* VAX version */
#include "vax_defs.h"
extern int32 int_req[IPL_HLVL];
#else /* PDP-11 version */
#include "pdp11_defs.h"
extern int32 int_req[IPL_HLVL];
#endif
#include "sim_sock.h"
#define DMC_NUMDEVICE 4 /* # DMC-11 devices */
#define DMC_UNITSPERDEVICE 1 /* # units per DMC-11 */
#define DMP_NUMDEVICE 1 /* # DMP-11 devices */
#define DMP_UNITSPERDEVICE 1 /* # units per DMP-11 */
#define DMC_RDX 8
/* debugging bitmaps */
#define DBG_TRC 0x0001 /* trace routine calls */
#define DBG_REG 0x0002 /* trace read/write registers */
#define DBG_WRN 0x0004 /* display warnings */
#define DBG_INF 0x0008 /* display informational messages (high level trace) */
#define DBG_DAT 0x0010 /* display data buffer contents */
#define DBG_DTS 0x0020 /* display data summary */
#define DBG_SOK 0x0040 /* display socket open/close */
#define DBG_CON 0x0080 /* display socket connection establishment */
#define TYPE_BACCI 0
#define TYPE_CNTLI 1
#define TYPE_BASEI 03
#define TYPE_BACCO 0
#define TYPE_CNTLO 1
#define TYPE_DMP_MODE 2
#define TYPE_DMP_CONTROL 1
#define TYPE_DMP_RECEIVE 0
#define TYPE_DMP_TRANSMIT 4
/* SEL0 */
#define DMC_TYPE_INPUT_MASK 0x0003
#define DMC_IN_IO_MASK 0x0004
#define DMP_IEO_MASK 0x0010
#define DMC_RQI_MASK 0x0020
#define DMP_RQI_MASK 0x0080
#define DMC_RDYI_MASK 0x0080
#define DMC_IEI_MASK 0x0040
#define DMP_IEI_MASK 0x0001
#define LU_LOOP_MASK 0x0800
#define MASTER_CLEAR_MASK 0x4000
#define RUN_MASK 0x8000
/* SEL2 */
#define DMP_IN_IO_MASK 0x0004
#define DMP_TYPE_INPUT_MASK 0x0007
#define TYPE_OUTPUT_MASK 0x0003
#define OUT_IO_MASK 0x0004
#define DMC_RDYO_MASK 0x0080
#define DMC_IEO_MASK 0x0040
#define DMP_RDYI_MASK 0x0010
/* BSEL6 */
#define LOST_DATA_MASK 0x0010
#define DISCONNECT_MASK 0x0040
#define SEL0_RUN_BIT 15
#define SEL0_MCLR_BIT 14
#define SEL0_LU_LOOP_BIT 11
#define SEL0_RDI_BIT 7
#define SEL0_DMC_IEI_BIT 6
#define SEL0_DMP_IEI_BIT 0
#define SEL0_DMP_IEO_BIT 4
#define SEL0_DMC_RQI_BIT 5
#define SEL0_DMP_RQI_BIT 7
#define SEL0_IN_IO_BIT 2
#define SEL0_TYPEI_BIT 0
#define SEL2_TYPEO_BIT 0
#define SEL2_RDO_BIT 7
#define SEL2_IEO_BIT 6
#define SEL2_OUT_IO_BIT 2
#define SEL2_LINE_BIT 8
#define SEL2_LINE_BIT_LENGTH 6
#define SEL2_PRIO_BIT 14
#define SEL2_PRIO_BIT_LENGTH 2
#define SEL6_LOST_DATA_BIT 4
#define SEL6_DISCONNECT_BIT 6
#define BUFFER_QUEUE_SIZE 7
#endif /* _VAX_DMC_H */

2
PDP11/pdp11_fp.c
View file

@ -438,7 +438,7 @@ switch ((IR >> 8) & 017) { /* decode IR<11:8> */
else fac.l = ReadI (GeteaFP (dstspec, leni), dstspec, leni);
fac.h = 0;
if (fac.l) {
if (sign = GET_SIGN_L (fac.l))
if ((sign = GET_SIGN_L (fac.l)))
fac.l = (fac.l ^ 0xFFFFFFFF) + 1;
for (i = 0; GET_SIGN_L (fac.l) == 0; i++)
fac.l = fac.l << 1;

8
PDP11/pdp11_hk.c
View file

@ -887,7 +887,7 @@ switch (fnc) { /* case on function */
err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
if (uptr->FNC == FNC_WRITE) { /* write? */
if (hkcs2 & CS2_UAI) { /* no addr inc? */
if (t = Map_ReadW (ba, 2, &comp)) { /* get 1st wd */
if ((t = Map_ReadW (ba, 2, &comp))) { /* get 1st wd */
wc = 0; /* NXM, no xfr */
hkcs2 = hkcs2 | CS2_NEM; /* set nxm err */
}
@ -895,7 +895,7 @@ switch (fnc) { /* case on function */
hkxb[i] = comp;
}
else { /* normal */
if (t = Map_ReadW (ba, wc << 1, hkxb)) { /* get buf */
if ((t = Map_ReadW (ba, wc << 1, hkxb))) {/* get buf */
wc = wc - (t >> 1); /* NXM, adj wc */
hkcs2 = hkcs2 | CS2_NEM; /* set nxm err */
}
@ -915,13 +915,13 @@ switch (fnc) { /* case on function */
for ( ; i < wc; i++) /* fill buf */
hkxb[i] = 0;
if (hkcs2 & CS2_UAI) { /* no addr inc? */
if (t = Map_WriteW (ba, 2, &hkxb[wc - 1])) {
if ((t = Map_WriteW (ba, 2, &hkxb[wc - 1]))) {
wc = 0; /* NXM, no xfr */
hkcs2 = hkcs2 | CS2_NEM; /* set nxm err */
}
}
else { /* normal */
if (t = Map_WriteW (ba, wc << 1, hkxb)) { /* put buf */
if ((t = Map_WriteW (ba, wc << 1, hkxb))) {/* put buf */
wc = wc - (t >> 1); /* NXM, adj wc */
hkcs2 = hkcs2 | CS2_NEM; /* set nxm err */
}

11
PDP11/pdp11_io.c
View file

@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
27-Mar-12 RMS Fixed order of int_internal (Jordi Guillaumes i Pons)
19-Mar-12 RMS Fixed declaration of cpu_opt (Mark Pizzolato)
12-Dec-11 RMS Fixed Qbus interrupts to treat all IO devices as BR4
19-Nov-08 RMS Moved I/O support routines to I/O library
@ -83,8 +84,8 @@ static const int32 pirq_bit[7] = {
};
static const int32 int_internal[IPL_HLVL] = {
INT_INTERNAL7, INT_INTERNAL6, INT_INTERNAL5, INT_INTERNAL4,
INT_INTERNAL3, INT_INTERNAL2, INT_INTERNAL1, 0
0, INT_INTERNAL1, INT_INTERNAL2, INT_INTERNAL3,
INT_INTERNAL4, INT_INTERNAL5, INT_INTERNAL6, INT_INTERNAL7
};
/* I/O page lookup and linkage routines
@ -372,17 +373,17 @@ init_ubus_tab (); /* init Unibus tables */
init_mbus_tab (); /* init Massbus tables */
for (i = 0; i < 7; i++) /* seed PIRQ intr */
int_vec[i + 1][pirq_bit[i]] = VEC_PIRQ;
if (r = cpu_build_dib ()) /* build CPU entries */
if ((r = cpu_build_dib ())) /* build CPU entries */
return r;
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
dibp = (DIB *) dptr->ctxt; /* get DIB */
if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */
if (dptr->flags & DEV_MBUS) { /* Massbus? */
if (r = build_mbus_tab (dptr, dibp)) /* add to Mbus tab */
if ((r = build_mbus_tab (dptr, dibp))) /* add to Mbus tab */
return r;
}
else { /* no, Unibus */
if (r = build_ubus_tab (dptr, dibp)) /* add to Unibus tab */
if ((r = build_ubus_tab (dptr, dibp))) /* add to Unibus tab */
return r;
}
} /* end if enabled */

4
PDP11/pdp11_ke.c
View file

@ -252,7 +252,7 @@ switch (PA & 017) { /* decode PA<3:0> */
data = data & 077; /* 6b shift count */
if (data != 0) {
t32 = (ke_AC << 16) | ke_MQ; /* 32b operand */
if (sign = GET_SIGN_W (ke_AC)) /* sext operand */
if ((sign = GET_SIGN_W (ke_AC))) /* sext operand */
t32 = t32 | ~017777777777;
if (data < 32) { /* [1,31] - left */
sout = (t32 >> (32 - data)) | (-sign << data);
@ -282,7 +282,7 @@ switch (PA & 017) { /* decode PA<3:0> */
data = data & 077; /* 6b shift count */
if (data != 0) {
t32 = (ke_AC << 16) | ke_MQ; /* 32b operand */
if (sign = GET_SIGN_W (ke_AC)) /* sext operand */
if ((sign = GET_SIGN_W (ke_AC))) /* sext operand */
t32 = t32 | ~017777777777;
if (data < 32) { /* [1,31] - left */
sout = (t32 >> (31 - data)) | (-sign << data);

10
PDP11/pdp11_mscp.h
View file

@ -211,7 +211,7 @@
#define CMD_REFL 2 /* ref # */
#define CMD_REFH 3
#define CMD_UN 4 /* unit # */
/* 5 /* reserved */
/* 5 *//* reserved */
#define CMD_OPC 6 /* opcode */
#define CMD_MOD 7 /* modifier */
@ -256,14 +256,14 @@
/* Flush - 10 W status (8 undefined) */
#define FLU_LNT 32
/* 8 - 15 /* reserved */
/* 8 - 15 *//* reserved */
#define FLU_POSL 16 /* position */
#define FLU_POSH 17
/* Write tape mark - 10W status (8 undefined) */
#define WTM_LNT 32
/* 8 - 15 /* reserved */
/* 8 - 15 *//* reserved */
#define WTM_POSL 16 /* position */
#define WTM_POSH 17
@ -399,8 +399,8 @@
#define RW_BAH 11
#define RW_MAPL 12 /* map table */
#define RW_MAPH 13
/* 14 /* reserved */
/* 15 /* reserved */
/* 14 *//* reserved */
/* 15 *//* reserved */
/* Disk specific parameters */

10
PDP11/pdp11_rk.c
View file

@ -545,13 +545,13 @@ if (wc && (err == 0)) { /* seek ok? */
rkxb[i] = 0;
}
if (rkcs & RKCS_INH) { /* incr inhibit? */
if (t = Map_WriteW (ma, 2, &rkxb[wc - 1])) { /* store last */
if ((t = Map_WriteW (ma, 2, &rkxb[wc - 1]))) {/* store last */
rker = rker | RKER_NXM; /* NXM? set flag */
wc = 0; /* no transfer */
}
}
else { /* normal store */
if (t = Map_WriteW (ma, wc << 1, rkxb)) { /* store buf */
if ((t = Map_WriteW (ma, wc << 1, rkxb))) { /* store buf */
rker = rker | RKER_NXM; /* NXM? set flag */
wc = wc - t; /* adj wd cnt */
}
@ -560,7 +560,7 @@ if (wc && (err == 0)) { /* seek ok? */
case RKCS_WRITE: /* write */
if (rkcs & RKCS_INH) { /* incr inhibit? */
if (t = Map_ReadW (ma, 2, &comp)) { /* get 1st word */
if ((t = Map_ReadW (ma, 2, &comp))) { /* get 1st word */
rker = rker | RKER_NXM; /* NXM? set flag */
wc = 0; /* no transfer */
}
@ -568,7 +568,7 @@ if (wc && (err == 0)) { /* seek ok? */
rkxb[i] = comp;
}
else { /* normal fetch */
if (t = Map_ReadW (ma, wc << 1, rkxb)) { /* get buf */
if ((t = Map_ReadW (ma, wc << 1, rkxb))) { /* get buf */
rker = rker | RKER_NXM; /* NXM? set flg */
wc = wc - t; /* adj wd cnt */
}
@ -584,7 +584,7 @@ if (wc && (err == 0)) { /* seek ok? */
case RKCS_WCHK: /* write check */
i = fxread (rkxb, sizeof (int16), wc, uptr->fileref);
if (err = ferror (uptr->fileref)) { /* read error? */
if ((err = ferror (uptr->fileref))) { /* read error? */
wc = 0; /* no transfer */
break;
}

42
PDP11/pdp11_rq.c
View file

@ -894,7 +894,7 @@ UNIT rqb_unit[] = {
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
{ UDATA (&rq_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
{ UDATA (&rq_tmrsvc, UNIT_DIS, 0) },
{ UDATA (&rq_tmrsvc, UNIT_IDLE|UNIT_DIS, 0) },
{ UDATA (&rq_quesvc, UNIT_DIS, 0) }
};
@ -966,7 +966,7 @@ UNIT rqc_unit[] = {
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
{ UDATA (&rq_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
{ UDATA (&rq_tmrsvc, UNIT_DIS, 0) },
{ UDATA (&rq_tmrsvc, UNIT_IDLE|UNIT_DIS, 0) },
{ UDATA (&rq_quesvc, UNIT_DIS, 0) }
};
@ -1038,7 +1038,7 @@ UNIT rqd_unit[] = {
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
{ UDATA (&rq_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
{ UDATA (&rq_tmrsvc, UNIT_DIS, 0) },
{ UDATA (&rq_tmrsvc, UNIT_IDLE|UNIT_DIS, 0) },
{ UDATA (&rq_quesvc, UNIT_DIS, 0) }
};
@ -1442,7 +1442,7 @@ DEVICE *dptr = rq_devmap[cp->cnum];
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_abo\n");
tpkt = 0; /* set no mtch */
if (uptr = rq_getucb (cp, lu)) { /* get unit */
if ((uptr = rq_getucb (cp, lu))) { /* get unit */
if (uptr->cpkt && /* curr pkt? */
(GETP32 (uptr->cpkt, CMD_REFL) == ref)) { /* match ref? */
tpkt = uptr->cpkt; /* save match */
@ -1455,8 +1455,8 @@ if (uptr = rq_getucb (cp, lu)) { /* get unit */
tpkt = uptr->pktq; /* save match */
uptr->pktq = cp->pak[tpkt].link; /* unlink */
}
else if (prv = uptr->pktq) { /* srch pkt q */
while (tpkt = cp->pak[prv].link) { /* walk list */
else if ((prv = uptr->pktq)) { /* srch pkt q */
while ((tpkt = cp->pak[prv].link)) { /* walk list */
if (GETP32 (tpkt, RSP_REFL) == ref) { /* match? unlink */
cp->pak[prv].link = cp->pak[tpkt].link;
break;
@ -1486,7 +1486,7 @@ UNIT *uptr;
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_avl\n");
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
if (q && uptr->cpkt) { /* need to queue? */
rq_enqt (cp, &uptr->pktq, pkt); /* do later */
return OK;
@ -1546,7 +1546,7 @@ if (cp->pak[pkt].d[CMD_MOD] & MD_NXU) { /* next unit? */
cp->pak[pkt].d[RSP_UN] = lu;
}
}
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
if ((uptr->flags & UNIT_ATT) == 0) /* not attached? */
sts = ST_OFL | SB_OFL_NV; /* offl no vol */
else if (uptr->flags & UNIT_ONL) /* online */
@ -1583,7 +1583,7 @@ UNIT *uptr;
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_onl\n");
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
if (q && uptr->cpkt) { /* need to queue? */
rq_enqt (cp, &uptr->pktq, pkt); /* do later */
return OK;
@ -1626,7 +1626,7 @@ else {
cmd = GETP (pkt, CMD_OPC, OPC); /* get opcode */
cp->cflgs = (cp->cflgs & CF_RPL) | /* hack ctrl flgs */
cp->pak[pkt].d[SCC_CFL];
if (cp->htmo = cp->pak[pkt].d[SCC_TMO]) /* set timeout */
if ((cp->htmo = cp->pak[pkt].d[SCC_TMO])) /* set timeout */
cp->htmo = cp->htmo + 2; /* if nz, round up */
cp->pak[pkt].d[SCC_CFL] = cp->cflgs; /* return flags */
cp->pak[pkt].d[SCC_TMO] = RQ_DCTMO; /* ctrl timeout */
@ -1655,7 +1655,7 @@ UNIT *uptr;
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_suc\n");
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
if (q && uptr->cpkt) { /* need to queue? */
rq_enqt (cp, &uptr->pktq, pkt); /* do later */
return OK;
@ -1686,7 +1686,7 @@ UNIT *uptr;
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_fmt\n");
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
if (q && uptr->cpkt) { /* need to queue? */
rq_enqt (cp, &uptr->pktq, pkt); /* do later */
return OK;
@ -1722,7 +1722,7 @@ UNIT *uptr;
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_rw(lu=%d, pkt=%d, queue=%s)\n", lu, pkt, q?"yes" : "no");
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
if (q && uptr->cpkt) { /* need to queue? */
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_rw - queued\n");
rq_enqt (cp, &uptr->pktq, pkt); /* do later */
@ -1769,7 +1769,7 @@ if (bc & 1) /* odd byte cnt? */
return (ST_HST | SB_HST_OC);
if (bc & 0xF0000000) /* 'reasonable' bc? */
return (ST_CMD | I_BCNT);
/* if (lbn & 0xF0000000) return (ST_CMD | I_LBN); /* 'reasonable' lbn? */
/* if (lbn & 0xF0000000) return (ST_CMD | I_LBN); *//* 'reasonable' lbn? */
if (lbn >= maxlbn) { /* accessing RCT? */
if (lbn >= (maxlbn + drv_tab[dtyp].rcts)) /* beyond copy 1? */
return (ST_CMD | I_LBN); /* lbn err */
@ -1854,7 +1854,7 @@ if (!uptr->io_complete) { /* Top End (I/O Initiation) Processing */
else if (cmd == OP_WR) { /* write? */
t = Map_ReadW (ba, tbc, uptr->rqxb); /* fetch buffer */
if (abc = tbc - t) { /* any xfer? */
if ((abc = tbc - t)) { /* any xfer? */
wwc = ((abc + (RQ_NUMBY - 1)) & ~(RQ_NUMBY - 1)) >> 1;
for (i = (abc >> 1); i < wwc; i++)
((uint16 *)(uptr->rqxb))[i] = 0;
@ -1889,7 +1889,7 @@ else { /* Bottom End (After I/O processing) */
else {
sim_disk_data_trace(uptr, uptr->rqxb, bl, tbc, "sim_disk_rdsect", DBG_DAT & rq_devmap[cp->cnum]->dctrl, DBG_REQ);
if ((cmd == OP_RD) && !err) { /* read? */
if (t = Map_WriteW (ba, tbc, uptr->rqxb)) { /* store, nxm? */
if ((t = Map_WriteW (ba, tbc, uptr->rqxb))) {/* store, nxm? */
PUTP32 (pkt, RW_WBCL, bc - (tbc - t)); /* adj bc */
PUTP32 (pkt, RW_WBAL, ba + (tbc - t)); /* adj ba */
if (rq_hbe (cp, uptr)) /* post err log */
@ -2746,11 +2746,11 @@ if ((uptr->flags & UNIT_ONL) == 0) {
if (uptr->cpkt) {
fprintf (st, "Unit %d current ", u);
rq_show_pkt (st, cp, uptr->cpkt);
if (pkt = uptr->pktq) {
if ((pkt = uptr->pktq)) {
do {
fprintf (st, "Unit %d queued ", u);
rq_show_pkt (st, cp, pkt);
} while (pkt = cp->pak[pkt].link);
} while ((pkt = cp->pak[pkt].link));
}
}
else fprintf (st, "Unit %d queues are empty\n", u);
@ -2777,7 +2777,7 @@ if (val & RQ_SH_RI) {
rq_show_ring (st, &cp->rq);
}
if (val & RQ_SH_FR) {
if (pkt = cp->freq) {
if ((pkt = cp->freq)) {
for (i = 0; pkt != 0; i++, pkt = cp->pak[pkt].link) {
if (i == 0)
fprintf (st, "Free queue = %d", pkt);
@ -2790,11 +2790,11 @@ if (val & RQ_SH_FR) {
else fprintf (st, "Free queue is empty\n");
}
if (val & RQ_SH_RS) {
if (pkt = cp->rspq) {
if ((pkt = cp->rspq)) {
do {
fprintf (st, "Response ");
rq_show_pkt (st, cp, pkt);
} while (pkt = cp->pak[pkt].link);
} while ((pkt = cp->pak[pkt].link));
}
else fprintf (st, "Response queue is empty\n");
}

5
PDP11/pdp11_sys.c
View file

@ -1,6 +1,6 @@
/* pdp11_sys.c: PDP-11 simulator interface
Copyright (c) 1993-2008, Robert M Supnik
Copyright (c) 1993-2012, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
29-Apr-12 RMS Fixed compiler warning (Mark Pizzolato)
19-Nov-08 RMS Moved I/O support routines to I/O library
15-May-08 RMS Added KE11-A, DC11 support
Renamed DL11
@ -992,7 +993,7 @@ switch (j) { /* case on class */
disp = (disp - addr) & 0177777;
else return SCPE_ARG;
}
if ((disp & 1) || (disp > 0400) && (disp < 0177402))
if ((disp & 1) || ((disp > 0400) && (disp < 0177402)))
return SCPE_ARG;
val[0] = val[0] | (((disp - 2) >> 1) & 0377);
break;

8
PDP11/pdp11_ta.c
View file

@ -397,13 +397,13 @@ switch (uptr->FNC) { /* case on function */
case TACS_WRITE|TACS_3RD: /* write CRC */
if (ta_bptr) { /* anything to write? */
if (st = sim_tape_wrrecf (uptr, ta_xb, ta_bptr)) /* write, err? */
if ((st = sim_tape_wrrecf (uptr, ta_xb, ta_bptr)))/* write, err? */
r = ta_map_err (uptr, st); /* map error */
}
break; /* op done */
case TACS_WFG: /* write file gap */
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
r = ta_map_err (uptr, st); /* map error */
break;
@ -413,7 +413,7 @@ switch (uptr->FNC) { /* case on function */
break;
case TACS_SRB: /* space rev blk */
if (st = sim_tape_sprecr (uptr, &tbc)) /* space rev, err? */
if ((st = sim_tape_sprecr (uptr, &tbc))) /* space rev, err? */
r = ta_map_err (uptr, st); /* map error */
break;
@ -425,7 +425,7 @@ switch (uptr->FNC) { /* case on function */
break;
case TACS_SFB: /* space fwd blk */
if (st = sim_tape_sprecf (uptr, &tbc)) /* space rev, err? */
if ((st = sim_tape_sprecf (uptr, &tbc))) /* space rev, err? */
r = ta_map_err (uptr, st); /* map error */
ta_cs |= TACS_CRC; /* CRC sets, no err */
break;

2
PDP11/pdp11_tc.c
View file

@ -992,7 +992,7 @@ switch (fnc) { /* at speed, check fnc *
if (ba >= uptr->hwmark)
uptr->hwmark = ba + 1;
}
/* else /* ignore hdr */
/* else *//* ignore hdr */
sim_activate (uptr, DT_WSIZE * dt_ltime);
DT_SETDONE; /* set done */
break;

14
PDP11/pdp11_tm.c
View file

@ -377,7 +377,7 @@ if (f == MTC_UNLOAD) { /* unload? */
}
else if (f == MTC_REWIND) /* rewind */
uptr->USTAT = uptr->USTAT | STA_REW; /* rewinding */
/* else /* uncomment this else if rewind/unload don't set done */
/* else *//* uncomment this else if rewind/unload don't set done */
tm_cmd = tm_cmd & ~MTC_DONE; /* clear done */
CLR_INT (TM); /* clear int */
sim_activate (uptr, tm_time); /* start io */
@ -439,7 +439,7 @@ switch (f) { /* case on function */
tm_sta = tm_sta | STA_RLE;
if (tbc < cbc) /* use smaller */
cbc = tbc;
if (t = Map_WriteB (xma, cbc, tmxb)) { /* copy buf to mem */
if ((t = Map_WriteB (xma, cbc, tmxb))) { /* copy buf to mem */
tm_sta = tm_sta | STA_NXM; /* NXM, set err */
cbc = cbc - t; /* adj byte cnt */
}
@ -449,13 +449,13 @@ switch (f) { /* case on function */
case MTC_WRITE: /* write */
case MTC_WREXT: /* write ext gap */
if (t = Map_ReadB (xma, cbc, tmxb)) { /* copy mem to buf */
if ((t = Map_ReadB (xma, cbc, tmxb))) { /* copy mem to buf */
tm_sta = tm_sta | STA_NXM; /* NXM, set err */
cbc = cbc - t; /* adj byte cnt */
if (cbc == 0) /* no xfr? done */
break;
}
if (st = sim_tape_wrrecf (uptr, tmxb, cbc)) /* write rec, err? */
if ((st = sim_tape_wrrecf (uptr, tmxb, cbc))) /* write rec, err? */
r = tm_map_err (uptr, st); /* map error */
else {
xma = (xma + cbc) & 0777777; /* inc bus addr */
@ -464,14 +464,14 @@ switch (f) { /* case on function */
break;
case MTC_WREOF: /* write eof */
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
r = tm_map_err (uptr, st); /* map error */
break;
case MTC_SPACEF: /* space forward */
do {
tm_bc = (tm_bc + 1) & 0177777; /* incr wc */
if (st = sim_tape_sprecf (uptr, &tbc)) { /* spc rec fwd, err? */
if ((st = sim_tape_sprecf (uptr, &tbc))) { /* spc rec fwd, err? */
r = tm_map_err (uptr, st); /* map error */
break;
}
@ -481,7 +481,7 @@ switch (f) { /* case on function */
case MTC_SPACER: /* space reverse */
do {
tm_bc = (tm_bc + 1) & 0177777; /* incr wc */
if (st = sim_tape_sprecr (uptr, &tbc)) { /* spc rec rev, err? */
if ((st = sim_tape_sprecr (uptr, &tbc))) { /* spc rec rev, err? */
r = tm_map_err (uptr, st); /* map error */
break;
}

44
PDP11/pdp11_tq.c
View file

@ -828,13 +828,13 @@ else if (mdf & ~tq_cmf[cmd]) { /* invalid mod? */
sts = ST_CMD | I_MODF; /* ill mods */
}
else { /* valid cmd */
if (uptr = tq_getucb (lu)) { /* valid unit? */
if ((uptr = tq_getucb (lu))) { /* valid unit? */
if (q && (tq_cmf[cmd] & CMF_SEQ) && /* queueing, seq, */
(uptr->cpkt || uptr->pktq)) { /* and active? */
tq_enqt (&uptr->pktq, pkt); /* do later */
return OK;
}
/* if (tq_cmf[cmd] & MD_CDL) /* clr cch lost? */
/* if (tq_cmf[cmd] & MD_CDL) *//* clr cch lost? */
/* uptr->flags = uptr->flags & ~UNIT_CDL; */
if ((mdf & MD_CSE) && (uptr->flags & UNIT_SXC)) /* clr ser exc? */
uptr->flags = uptr->flags & ~UNIT_SXC;
@ -909,7 +909,7 @@ UNIT *uptr;
sim_debug(DBG_TRC, &tq_dev, "tq_abo\n");
tpkt = 0; /* set no mtch */
if (uptr = tq_getucb (lu)) { /* get unit */
if ((uptr = tq_getucb (lu))) { /* get unit */
if (uptr->cpkt && /* curr pkt? */
(GETP32 (uptr->cpkt, CMD_REFL) == ref)) { /* match ref? */
tpkt = uptr->cpkt; /* save match */
@ -922,8 +922,8 @@ if (uptr = tq_getucb (lu)) { /* get unit */
tpkt = uptr->pktq; /* save match */
uptr->pktq = tq_pkt[tpkt].link; /* unlink */
}
else if (prv = uptr->pktq) { /* srch pkt q */
while (tpkt = tq_pkt[prv].link) { /* walk list */
else if ((prv = uptr->pktq)) { /* srch pkt q */
while ((tpkt = tq_pkt[prv].link)) { /* walk list */
if (GETP32 (tpkt, RSP_REFL) == ref) { /* match ref? */
tq_pkt[prv].link = tq_pkt[tpkt].link; /* unlink */
break;
@ -953,7 +953,7 @@ UNIT *uptr;
sim_debug(DBG_TRC, &tq_dev, "tq_avl\n");
if (uptr = tq_getucb (lu)) { /* unit exist? */
if ((uptr = tq_getucb (lu))) { /* unit exist? */
if (uptr->flags & UNIT_SXC) /* ser exc pending? */
sts = ST_SXC;
else {
@ -1012,7 +1012,7 @@ if (tq_pkt[pkt].d[CMD_MOD] & MD_NXU) { /* next unit? */
tq_pkt[pkt].d[RSP_UN] = lu;
}
}
if (uptr = tq_getucb (lu)) { /* unit exist? */
if ((uptr = tq_getucb (lu))) { /* unit exist? */
if ((uptr->flags & UNIT_ATT) == 0) /* not attached? */
sts = ST_OFL | SB_OFL_NV; /* offl no vol */
else if (uptr->flags & UNIT_ONL) /* online */
@ -1039,7 +1039,7 @@ UNIT *uptr;
sim_debug(DBG_TRC, &tq_dev, "tq_onl\n");
if (uptr = tq_getucb (lu)) { /* unit exist? */
if ((uptr = tq_getucb (lu))) { /* unit exist? */
if ((uptr->flags & UNIT_ATT) == 0) /* not attached? */
sts = ST_OFL | SB_OFL_NV; /* offl no vol */
else if (uptr->flags & UNIT_ONL) /* already online? */
@ -1070,7 +1070,7 @@ if (tq_pkt[pkt].d[SCC_MSV]) /* MSCP ver = 0? */
else {
tq_cflgs = (tq_cflgs & CF_RPL) | /* hack ctrl flgs */
tq_pkt[pkt].d[SCC_CFL];
if (tq_htmo = tq_pkt[pkt].d[SCC_TMO]) /* set timeout */
if ((tq_htmo = tq_pkt[pkt].d[SCC_TMO])) /* set timeout */
tq_htmo = tq_htmo + 2; /* if nz, round up */
tq_pkt[pkt].d[SCC_CFL] = tq_cflgs; /* return flags */
tq_pkt[pkt].d[SCC_TMO] = TQ_DCTMO; /* ctrl timeout */
@ -1096,7 +1096,7 @@ UNIT *uptr;
sim_debug(DBG_TRC, &tq_dev, "tq_suc\n");
if (uptr = tq_getucb (lu)) { /* unit exist? */
if ((uptr = tq_getucb (lu))) { /* unit exist? */
if ((uptr->flags & UNIT_ATT) == 0) /* not attached? */
sts = ST_OFL | SB_OFL_NV; /* offl no vol */
else {
@ -1120,7 +1120,7 @@ UNIT *uptr;
sim_debug(DBG_TRC, &tq_dev, "tq_flu\n");
if (uptr = tq_getucb (lu)) /* unit exist? */
if ((uptr = tq_getucb (lu))) /* unit exist? */
sts = tq_mot_valid (uptr, OP_FLU); /* validate req */
else sts = ST_OFL; /* offline */
tq_putr (pkt, OP_FLU | OP_END, tq_efl (uptr), sts, FLU_LNT, UQ_TYP_SEQ);
@ -1138,7 +1138,7 @@ UNIT *uptr;
sim_debug(DBG_TRC, &tq_dev, "tq_erase\n");
if (uptr = tq_getucb (lu)) { /* unit exist? */
if ((uptr = tq_getucb (lu))) { /* unit exist? */
sts = tq_mot_valid (uptr, cmd); /* validity checks */
if (sts == ST_SUC) { /* ok? */
uptr->cpkt = pkt; /* op in progress */
@ -1162,7 +1162,7 @@ UNIT *uptr;
sim_debug(DBG_TRC, &tq_dev, "tq_wtm\n");
if (uptr = tq_getucb (lu)) { /* unit exist? */
if ((uptr = tq_getucb (lu))) { /* unit exist? */
objp = uptr->objp; /* position op */
sts = tq_mot_valid (uptr, OP_WTM); /* validity checks */
if (sts == ST_SUC) { /* ok? */
@ -1188,7 +1188,7 @@ UNIT *uptr;
sim_debug(DBG_TRC, &tq_dev, "tq_pos\n");
if (uptr = tq_getucb (lu)) { /* unit exist? */
if ((uptr = tq_getucb (lu))) { /* unit exist? */
objp = uptr->objp; /* position op */
sts = tq_mot_valid (uptr, OP_POS); /* validity checks */
if (sts == ST_SUC) { /* ok? */
@ -1224,7 +1224,7 @@ UNIT *uptr;
sim_debug(DBG_TRC, &tq_dev, "tq_rw\n");
if (uptr = tq_getucb (lu)) { /* unit exist? */
if ((uptr = tq_getucb (lu))) { /* unit exist? */
objp = uptr->objp; /* position op */
sts = tq_mot_valid (uptr, cmd); /* validity checks */
if (sts == ST_SUC) { /* ok? */
@ -1363,7 +1363,7 @@ switch (cmd) { /* case on command */
}
else wbc = res->tbc;
if (cmd == OP_RD) { /* read? */
if (t = Map_WriteB (ba, wbc, res->tqxb)) { /* store, nxm? */
if ((t = Map_WriteB (ba, wbc, res->tqxb))) {/* store, nxm? */
PUTP32 (pkt, RW_BCL, wbc - t); /* adj bc */
if (tq_hbe (uptr, ba + wbc - t)) /* post err log */
tq_mot_end (uptr, EF_LOG, ST_HST | SB_HST_NXM, res->tbc);
@ -1402,7 +1402,7 @@ switch (cmd) { /* case on command */
case OP_WR: /* write */
if (!io_complete) { /* Top half processing */
if (t = Map_ReadB (ba, bc, res->tqxb)) { /* fetch buf, nxm? */
if ((t = Map_ReadB (ba, bc, res->tqxb))) { /* fetch buf, nxm? */
PUTP32 (pkt, RW_BCL, 0); /* no bytes xfer'd */
if (tq_hbe (uptr, ba + bc - t)) /* post err log */
tq_mot_end (uptr, EF_LOG, ST_HST | SB_HST_NXM, bc);
@ -2291,11 +2291,11 @@ if ((uptr->flags & UNIT_ONL) == 0) {
if (uptr->cpkt) {
fprintf (st, "Unit %d current ", u);
tq_show_pkt (st, uptr->cpkt);
if (pkt = uptr->pktq) {
if ((pkt = uptr->pktq)) {
do {
fprintf (st, "Unit %d queued ", u);
tq_show_pkt (st, pkt);
} while (pkt = tq_pkt[pkt].link);
} while ((pkt = tq_pkt[pkt].link));
}
}
else fprintf (st, "Unit %d queues are empty\n", u);
@ -2320,7 +2320,7 @@ if (val & TQ_SH_RI) {
tq_show_ring (st, &tq_rq);
}
if (val & TQ_SH_FR) {
if (pkt = tq_freq) {
if ((pkt = tq_freq)) {
for (i = 0; pkt != 0; i++, pkt = tq_pkt[pkt].link) {
if (i == 0)
fprintf (st, "Free queue = %d", pkt);
@ -2333,11 +2333,11 @@ if (val & TQ_SH_FR) {
else fprintf (st, "Free queue is empty\n");
}
if (val & TQ_SH_RS) {
if (pkt = tq_rspq) {
if ((pkt = tq_rspq)) {
do {
fprintf (st, "Response ");
tq_show_pkt (st, pkt);
} while (pkt = tq_pkt[pkt].link);
} while ((pkt = tq_pkt[pkt].link));
}
else fprintf (st, "Response queue is empty\n");
}

8
PDP11/pdp11_ts.c
View file

@ -490,7 +490,7 @@ do {
fc = (fc - 1) & DMASK; /* decr wc */
if (upd)
msgrfc = fc;
if (st = sim_tape_sprecf (uptr, &tbc)) /* space rec fwd, err? */
if ((st = sim_tape_sprecf (uptr, &tbc))) /* space rec fwd, err? */
return ts_map_status (st); /* map status */
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
} while (fc != 0);
@ -533,7 +533,7 @@ do {
fc = (fc - 1) & DMASK; /* decr wc */
if (upd)
msgrfc = fc;
if (st = sim_tape_sprecr (uptr, &tbc)) /* space rec rev, err? */
if ((st = sim_tape_sprecr (uptr, &tbc))) /* space rec rev, err? */
return ts_map_status (st); /* map status */
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
} while (fc != 0);
@ -666,7 +666,7 @@ else {
return TC5;
}
}
if (st = sim_tape_wrrecf (uptr, tsxb, fc)) /* write rec, err? */
if ((st = sim_tape_wrrecf (uptr, tsxb, fc))) /* write rec, err? */
return ts_map_status (st); /* return status */
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
msgrfc = 0;
@ -679,7 +679,7 @@ int32 ts_wtmk (UNIT *uptr)
{
t_stat st;
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
return ts_map_status (st); /* return status */
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
if (sim_tape_eot (&ts_unit)) /* EOT on write? */

12
PDP11/pdp11_tu.c
View file

@ -647,7 +647,7 @@ switch (fnc) { /* case on function */
case FNC_SPACEF: /* space forward */
do {
tufc = (tufc + 1) & 0177777; /* incr fc */
if (st = sim_tape_sprecf (uptr, &tbc)) { /* space rec fwd, err? */
if ((st = sim_tape_sprecf (uptr, &tbc))) { /* space rec fwd, err? */
r = tu_map_err (drv, st, 0); /* map error */
break;
}
@ -660,7 +660,7 @@ switch (fnc) { /* case on function */
case FNC_SPACER: /* space reverse */
do {
tufc = (tufc + 1) & 0177777; /* incr wc */
if (st = sim_tape_sprecr (uptr, &tbc)) { /* space rec rev, err? */
if ((st = sim_tape_sprecr (uptr, &tbc))) { /* space rec rev, err? */
r = tu_map_err (drv, st, 0); /* map error */
break;
}
@ -671,7 +671,7 @@ switch (fnc) { /* case on function */
break;
case FNC_WREOF: /* write end of file */
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
r = tu_map_err (drv, st, 0); /* map error */
break;
@ -687,7 +687,7 @@ switch (fnc) { /* case on function */
tufc = 0; /* clear frame count */
if ((uptr->UDENS == TC_1600) && sim_tape_bot (uptr))
tufs = tufs | FS_ID; /* PE BOT? ID burst */
if (st = sim_tape_rdrecf (uptr, xbuf, &tbc, MT_MAXFR)) { /* read fwd */
if ((st = sim_tape_rdrecf (uptr, xbuf, &tbc, MT_MAXFR))) {/* read fwd */
if (st == MTSE_TMK) /* tmk also sets FCE */
tu_set_er (ER_FCE);
r = tu_map_err (drv, st, 1); /* map error */
@ -739,7 +739,7 @@ switch (fnc) { /* case on function */
}
tbc = xbc;
}
if (st = sim_tape_wrrecf (uptr, xbuf, tbc)) /* write rec, err? */
if ((st = sim_tape_wrrecf (uptr, xbuf, tbc))) /* write rec, err? */
r = tu_map_err (drv, st, 1); /* map error */
else {
tufc = (tufc + tbc) & 0177777;
@ -751,7 +751,7 @@ switch (fnc) { /* case on function */
case FNC_READR: /* read reverse */
case FNC_WCHKR: /* wcheck = read */
tufc = 0; /* clear frame count */
if (st = sim_tape_rdrecr (uptr, xbuf + 4, &tbc, MT_MAXFR)) { /* read rev */
if ((st = sim_tape_rdrecr (uptr, xbuf + 4, &tbc, MT_MAXFR))) {/* read rev */
if (st == MTSE_TMK) /* tmk also sets FCE */
tu_set_er (ER_FCE);
r = tu_map_err (drv, st, 1); /* map error */

7
PDP11/pdp11_xq.c
View file

@ -702,7 +702,7 @@ t_stat xq_show_filters (FILE* st, UNIT* uptr, int32 val, void* desc)
fprintf(st, "Filters:\n");
for (i=0; i<XQ_FILTER_MAX; i++) {
eth_mac_fmt((ETH_MAC*)xq->var->setup.macs[i], buffer);
fprintf(st, " [%2d]: %s\n", i, buffer);
fprintf(st, " [%2d]: %s\n", (int)i, buffer);
}
if (xq->var->setup.multicast)
fprintf(st, "All Multicast Receive Mode\n");
@ -1187,7 +1187,7 @@ t_stat xq_process_setup(CTLR* xq)
xq->var->setup.multicast = (0 != (len & XQ_SETUP_MC));
xq->var->setup.promiscuous = (0 != (len & XQ_SETUP_PM));
if (led = (len & XQ_SETUP_LD) >> 2) {
if ((led = (len & XQ_SETUP_LD) >> 2)) {
switch (led) {
case 1: xq->var->setup.l1 = 0; break;
case 2: xq->var->setup.l2 = 0; break;
@ -2073,6 +2073,9 @@ t_stat xq_process_bootrom (CTLR* xq)
/* set to next bdl (implicit chain) */
xq->var->rbdl_ba += 12;
break;
default:
break;
} /* switch */
/* --------------------------- Done, finish up -----------------------------*/

4
PDP11/pdp11_xu.c
View file

@ -1041,7 +1041,7 @@ void xu_process_receive(CTLR* xu)
sim_debug(DBG_TRC, xu->dev, "xu_process_receive(), buffers: %d\n", xu->var->rrlen);
/* xu_dump_rxring(xu); /* debug receive ring */
/* xu_dump_rxring(xu); *//* debug receive ring */
/* process only when in the running state, and host buffers are available */
if ((state != STATE_RUNNING) || no_buffers)
@ -1213,7 +1213,7 @@ void xu_process_transmit(CTLR* xu)
t_stat rstatus, wstatus;
sim_debug(DBG_TRC, xu->dev, "xu_process_transmit()\n");
/* xu_dump_txring(xu); /* debug receive ring */
/* xu_dump_txring(xu); *//* debug receive ring */
for (;;) {

2
PDP18B/pdp18b_cpu.c
View file

@ -604,7 +604,7 @@ while (reason == 0) { /* loop until halted */
int32 link_init, fill;
if (sim_interval <= 0) { /* check clock queue */
if (reason = sim_process_event ())
if ((reason = sim_process_event ()))
break;
api_int = api_eval (&int_pend); /* eval API */
}

2
PDP18B/pdp18b_dt.c
View file

@ -1147,7 +1147,7 @@ switch (fnc) { /* at speed, check fnc *
if (ba >= uptr->hwmark)
uptr->hwmark = ba + 1;
}
/* /* ignore hdr */
/* ignore hdr */
sim_activate (uptr, DT_WSIZE * dt_ltime);
if (M[DT_WC] == 0)
dt_substate = DTO_WCO;

26
PDP18B/pdp18b_fpp.c
View file

@ -253,7 +253,7 @@ switch (fop) { /* case on subop */
break;
case FOP_SUB: /* subtract */
if (sta = fp15_opnd (fir, ar, &fmb)) /* fetch op to FMB */
if ((sta = fp15_opnd (fir, ar, &fmb))) /* fetch op to FMB */
break;
if (fir & FI_FP) /* fp? */
sta = fp15_fadd (fir, &fma, &fmb, 1); /* yes, fp sub */
@ -262,7 +262,7 @@ switch (fop) { /* case on subop */
case FOP_RSUB: /* reverse sub */
fmb = fma; /* FMB <- FMA */
if (sta = fp15_opnd (fir, ar, &fma)) /* fetch op to FMA */
if ((sta = fp15_opnd (fir, ar, &fma))) /* fetch op to FMA */
break;
if (fir & FI_FP) /* fp? */
sta = fp15_fadd (fir, &fma, &fmb, 1); /* yes, fp sub */
@ -270,7 +270,7 @@ switch (fop) { /* case on subop */
break;
case FOP_MUL: /* multiply */
if (sta = fp15_opnd (fir, ar, &fmb)) /* fetch op to FMB */
if ((sta = fp15_opnd (fir, ar, &fmb))) /* fetch op to FMB */
break;
if (fir & FI_FP) /* fp? */
sta = fp15_fmul (fir, &fma, &fmb); /* yes, fp mul */
@ -278,9 +278,9 @@ switch (fop) { /* case on subop */
break;
case FOP_DIV: /* divide */
if (sta = fp15_opnd (fir, ar, &fmb)) /* fetch op to FMB */
if ((sta = fp15_opnd (fir, ar, &fmb))) /* fetch op to FMB */
break;
if (sta = fp15_opnd (fir, ar, &fmb)) break; /* fetch op to FMB */
if ((sta = fp15_opnd (fir, ar, &fmb)))break; /* fetch op to FMB */
if (fir & FI_FP) /* fp? */
sta = fp15_fdiv (fir, &fma, &fmb); /* yes, fp div */
else sta = fp15_idiv (fir, &fma, &fmb); /* no, int div */
@ -288,7 +288,7 @@ switch (fop) { /* case on subop */
case FOP_RDIV: /* reverse divide */
fmb = fma; /* FMB <- FMA */
if (sta = fp15_opnd (fir, ar, &fma)) /* fetch op to FMA */
if ((sta = fp15_opnd (fir, ar, &fma))) /* fetch op to FMA */
break;
if (fir & FI_FP) /* fp? */
sta = fp15_fdiv (fir, &fma, &fmb); /* yes, fp div */
@ -296,7 +296,7 @@ switch (fop) { /* case on subop */
break;
case FOP_LD: /* load */
if (sta = fp15_opnd (fir, ar, &fma)) /* fetch op to FMA */
if ((sta = fp15_opnd (fir, ar, &fma))) /* fetch op to FMA */
break;
fp15_asign (fir, &fma); /* modify A sign */
if (fir & FI_FP) /* fp? */
@ -309,7 +309,7 @@ switch (fop) { /* case on subop */
break;
case FOP_FLT: /* float */
if (sta = fp15_opnd (fir, ar, &fma)) /* fetch op to FMA */
if ((sta = fp15_opnd (fir, ar, &fma))) /* fetch op to FMA */
break;
fma.exp = 35;
fp15_asign (fir, &fma); /* adjust A sign */
@ -317,13 +317,13 @@ switch (fop) { /* case on subop */
break;
case FOP_FIX: /* fix */
if (sta = fp15_opnd (fir, ar, &fma)) /* fetch op to FMA */
if ((sta = fp15_opnd (fir, ar, &fma))) /* fetch op to FMA */
break;
sta = fp15_fix (fir, &fma); /* fix */
break;
case FOP_LFMQ: /* load FMQ */
if (sta = fp15_opnd (fir, ar, &fma)) /* fetch op to FMA */
if ((sta = fp15_opnd (fir, ar, &fma))) /* fetch op to FMA */
break;
dp_swap (&fma, &fmq); /* swap FMA, FMQ */
fp15_asign (fir, &fma); /* adjust A sign */
@ -337,7 +337,7 @@ switch (fop) { /* case on subop */
sta = Write (ar, dat, WR);
}
else { /* no, load */
if (sta = Read (ar, &dat, RD))
if ((sta = Read (ar, &dat, RD)))
break;
fguard = (dat >> JEA_V_GUARD) & 1;
jea = dat & JEA_EAMASK;
@ -345,7 +345,7 @@ switch (fop) { /* case on subop */
break;
case FOP_ADD: /* add */
if (sta = fp15_opnd (fir, ar, &fmb)) /* fetch op to FMB */
if ((sta = fp15_opnd (fir, ar, &fmb))) /* fetch op to FMB */
break;
if (fir & FI_FP) /* fp? */
sta = fp15_fadd (fir, &fma, &fmb, 0); /* yes, fp add */
@ -429,7 +429,7 @@ t_stat sta;
fguard = 0; /* clear guard */
if (ir & FI_FP) { /* fp? */
if (sta = fp15_norm (ir, a, NULL, 0)) /* normalize */
if ((sta = fp15_norm (ir, a, NULL, 0))) /* normalize */
return sta;
if (ir & FI_DP) { /* dp? */
wd[0] = a->exp & DMASK; /* exponent */

8
PDP18B/pdp18b_mt.c
View file

@ -353,7 +353,7 @@ switch (f) { /* case on function */
mtxb[p++] = M[xma] & 0377;
}
} /* end for */
if (st = sim_tape_wrrecf (uptr, mtxb, tbc)) /* write rec, err? */
if ((st = sim_tape_wrrecf (uptr, mtxb, tbc))) /* write rec, err? */
r = mt_map_err (uptr, st); /* map error */
else {
M[MT_CA] = (M[MT_CA] + wc) & DMASK; /* advance mem addr */
@ -363,7 +363,7 @@ switch (f) { /* case on function */
break;
case FN_WREOF:
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
r = mt_map_err (uptr, st); /* map error */
else uptr->USTAT = STA_EOF;
mt_cu = mt_cu & ~CU_ERASE; /* clear erase flag */
@ -372,7 +372,7 @@ switch (f) { /* case on function */
case FN_SPACEF: /* space forward */
do {
M[MT_WC] = (M[MT_WC] + 1) & DMASK; /* inc WC */
if (st = sim_tape_sprecf (uptr, &tbc)) { /* space rec fwd, err? */
if ((st = sim_tape_sprecf (uptr, &tbc))) { /* space rec fwd, err? */
r = mt_map_err (uptr, st); /* map error */
break;
}
@ -382,7 +382,7 @@ switch (f) { /* case on function */
case FN_SPACER: /* space reverse */
do {
M[MT_WC] = (M[MT_WC] + 1) & DMASK; /* inc WC */
if (st = sim_tape_sprecr (uptr, &tbc)) { /* space rec rev, err? */
if ((st = sim_tape_sprecr (uptr, &tbc))) { /* space rec rev, err? */
r = mt_map_err (uptr, st); /* map error */
break;
}

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