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Revised all VAX simulator devices to have proper help information defined to make "HELP dev SHOW" and "HELP dev SET" most useful.

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This commit is contained in:
Mark Pizzolato 2013-02-02 16:29:38 -08:00
parent 7db15faf76
commit 28b90552b7
44 changed files with 583 additions and 494 deletions
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26
PDP11/pdp11_cr.c
View file

@ -378,31 +378,35 @@ static const REG cr_reg[] = {
static const MTAB cr_mod[] = {
#if defined (VM_PDP11)
{ UNIT_CR11, UNIT_CR11, "CR11", "CR11", &cr_set_type },
{ UNIT_CR11, 0, "CD11", "CD11", &cr_set_type },
{ UNIT_CR11, UNIT_CR11, "CR11", "CR11",
&cr_set_type, NULL, NULL, "Set device type to CR11" },
{ UNIT_CR11, 0, "CD11", "CD11",
&cr_set_type, NULL, NULL, "Set device type to CD11" },
#else
{ UNIT_CR11, UNIT_CR11, "CR11", NULL },
{ UNIT_CR11, 0, "CD11", NULL },
#endif
{ UNIT_AUTOEOF, UNIT_AUTOEOF, "auto EOF", "AUTOEOF", NULL },
{ UNIT_AUTOEOF, 0, "no auto EOF", "NOAUTOEOF", NULL },
{ UNIT_AUTOEOF, UNIT_AUTOEOF, "auto EOF", "AUTOEOF",
NULL, NULL, NULL, "Enable auto EOF mode" },
{ UNIT_AUTOEOF, 0, "no auto EOF", "NOAUTOEOF",
NULL, NULL, NULL, "Disable auto EOF mode" },
/* card reader RESET switch */
{ MTAB_XTD|MTAB_VDV, 0, NULL, "RESET",
&cr_set_reset, NULL, NULL },
&cr_set_reset, NULL, NULL, "Pulse reader reset switch" },
/* card reader STOP switch */
{ MTAB_XTD|MTAB_VDV, 0, NULL, "STOP",
&cr_set_stop, NULL, NULL },
&cr_set_stop, NULL, NULL, "Pulse reader Stop button" },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", NULL,
NULL, &cr_show_format, NULL },
NULL, &cr_show_format, NULL, "Set reader input format" },
{ MTAB_XTD|MTAB_VDV, 006, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL },
&set_vec, &show_vec, NULL, "Interrupt vector" },
{ MTAB_XTD|MTAB_VDV, 0, "RATE", "RATE={DEFAULT|200..1200}",
&cr_set_rate, &cr_show_rate, NULL },
&cr_set_rate, &cr_show_rate, NULL, "Display input rate" },
{ MTAB_XTD|MTAB_VDV, 0, "TRANSLATION",
"TRANSLATION={DEFAULT|026|026FTN|029|EBCDIC}",
&cr_set_trans, &cr_show_trans, NULL },
&cr_set_trans, &cr_show_trans, NULL, "Display translation mode" },
{ 0 } };
DEVICE cr_dev = {

23
PDP11/pdp11_dmc.c
View file

@ -425,16 +425,23 @@ REG dmp_reg[] = {
{ NULL } };
MTAB dmc_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, "PEER", "PEER=address:port" ,&dmc_setpeer, &dmc_showpeer, NULL },
{ MTAB_XTD | MTAB_VDV, 0, "SPEED", "SPEED=bits/sec (0=unrestricted)" ,&dmc_setspeed, &dmc_showspeed, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "PEER", "PEER=address:port",
&dmc_setpeer, &dmc_showpeer, NULL, "Set/Display destination" },
{ MTAB_XTD|MTAB_VDV, 0, "SPEED", "SPEED=bits/sec (0=unrestricted)" ,
&dmc_setspeed, &dmc_showspeed, NULL, "Display rate limit" },
#ifdef DMP
{ MTAB_XTD | MTAB_VDV, 0, "TYPE", "TYPE" ,&dmc_settype, &dmc_showtype, NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR,0, "TYPE", "TYPE" ,&dmc_settype, &dmc_showtype, NULL, "Set/Display device type" },
#endif
{ MTAB_XTD | MTAB_VDV, 0, "LINEMODE", "LINEMODE={PRIMARY|SECONDARY}" ,&dmc_setlinemode, &dmc_showlinemode, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATS", "STATS" ,&dmc_setstats, &dmc_showstats, NULL },
{ MTAB_XTD | MTAB_VDV, 0, "CONNECTPOLL", "CONNECTPOLL=seconds" ,&dmc_setconnectpoll, &dmc_showconnectpoll, NULL },
{ MTAB_XTD | MTAB_VDV, 006, "ADDRESS", "ADDRESS", &set_addr, &show_addr, NULL },
{ MTAB_XTD |MTAB_VDV, 0, "VECTOR", "VECTOR", &set_vec, &show_vec, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "LINEMODE", "LINEMODE={PRIMARY|SECONDARY}",
&dmc_setlinemode, &dmc_showlinemode, NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "STATS", "STATS",
&dmc_setstats, &dmc_showstats, NULL, "Display statistics" },
{ MTAB_XTD|MTAB_VDV, 0, "CONNECTPOLL", "CONNECTPOLL=seconds",
&dmc_setconnectpoll, &dmc_showconnectpoll, NULL, "Display connection poll interval" },
{ MTAB_XTD|MTAB_VDV, 006, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL, "Interrupt vector" },
{ 0 },
};

46
PDP11/pdp11_dz.c
View file

@ -313,33 +313,33 @@ REG dz_reg[] = {
};
MTAB dz_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dz_desc },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "8 bit mode" },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "7 bit mode - non printing suppressed" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dz_desc, "Disconnect a specific line" },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &dz_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &dz_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &tmxr_show_cstat, (void *) &dz_desc },
{ MTAB_XTD|MTAB_VDV, 010, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, DZ_LINES, "VECTOR", "VECTOR",
&set_vec, &show_vec_mux, (void *) &dz_desc },
NULL, &tmxr_show_summ, (void *) &dz_desc, "Display a summary of line states" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &dz_desc, "Display current connections" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &tmxr_show_cstat, (void *) &dz_desc, "Display multiplexer statistics" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 020, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec_mux, (void *) &dz_desc, "Interrupt vector" },
#if !defined (VM_PDP10)
{ MTAB_XTD | MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
&set_addr_flt, NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
&set_addr_flt, NULL, NULL, "Enable autoconfiguration of address & vector" },
#endif
{ MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
&dz_setnl, &tmxr_show_lines, (void *) &dz_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NC, 0, NULL, "LOG",
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "LINES", "LINES=n",
&dz_setnl, &tmxr_show_lines, (void *) &dz_desc, "Display number of lines" },
{ MTAB_XTD|MTAB_VDV|MTAB_NC, 0, NULL, "LOG=n=file",
&dz_set_log, NULL, &dz_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NC, 0, NULL, "NOLOG",
&dz_set_nolog, NULL, &dz_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "LOG", NULL,
NULL, &dz_show_log, &dz_desc },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, NULL, "NOLOG",
&dz_set_nolog, NULL, &dz_desc, "Disable logging on designated line" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "LOG", NULL,
NULL, &dz_show_log, &dz_desc, "Display logging for all lines" },
{ 0 }
};

26
PDP11/pdp11_hk.c
View file

@ -639,9 +639,12 @@ REG hk_reg[] = {
};
MTAB hk_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK", &hk_set_bad },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable disk drive" },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED",
NULL, NULL, NULL, "Write lock disk drive" },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK",
&hk_set_bad, NULL, NULL, "write bad block table on last track" },
{ (UNIT_DTYPE+UNIT_ATT), UNIT_RK06 + UNIT_ATT,
"RK06", NULL, NULL },
{ (UNIT_DTYPE+UNIT_ATT), UNIT_RK07 + UNIT_ATT,
@ -650,16 +653,17 @@ MTAB hk_mod[] = {
"RK06", NULL, NULL },
{ (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), UNIT_RK07,
"RK07", NULL, NULL },
{ (UNIT_AUTO+UNIT_ATT), UNIT_AUTO, "autosize", NULL, NULL },
{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE", NULL },
{ (UNIT_AUTO+UNIT_DTYPE), UNIT_RK06,
NULL, "RK06", &hk_set_size },
{ (UNIT_AUTO+UNIT_DTYPE), UNIT_RK07,
NULL, "RK07", &hk_set_size },
{ (UNIT_AUTO+UNIT_ATT), UNIT_AUTO, "autosize", NULL},
{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE",
NULL, NULL, NULL, "set type based on file size at ATTACH" },
{ (UNIT_AUTO+UNIT_DTYPE), UNIT_RK06, NULL, "RK06",
&hk_set_size, NULL, NULL, "Set type to RK06" },
{ (UNIT_AUTO+UNIT_DTYPE), UNIT_RK07, NULL, "RK07",
&hk_set_size, NULL, NULL, "Set type to RK07" },
{ MTAB_XTD|MTAB_VDV, 0040, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL },
&set_vec, &show_vec, NULL, "Interrupt vector" },
{ 0 }
};

4
PDP11/pdp11_lp.c
View file

@ -100,9 +100,9 @@ REG lpt_reg[] = {
MTAB lpt_mod[] = {
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL },
&set_vec, &show_vec, NULL, "Interrupt vector" },
{ 0 }
};

61
PDP11/pdp11_rl.c
View file

@ -311,35 +311,54 @@ static const REG rl_reg[] = {
static const MTAB rl_mod[] = {
#if defined (VM_PDP11)
{ MTAB_XTD|MTAB_VDV, (DEV_RLV11|DEV_Q18), "", "RLV11", &rl_set_ctrl, &rl_show_ctrl, NULL},
{ MTAB_XTD|MTAB_VDV, 0, NULL, "RLV12", &rl_set_ctrl, NULL, NULL},
{ MTAB_XTD|MTAB_VDV, (DEV_RLV11|DEV_Q18), "", "RLV11",
&rl_set_ctrl, &rl_show_ctrl, NULL, "Set controller type RLV11" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "RLV12",
&rl_set_ctrl, NULL, NULL, "Set controller type RLV12" },
#endif
{ UNIT_OFFL, 0, "on line", "ONLINE", NULL, NULL },
{ UNIT_OFFL, UNIT_OFFL, "off line", "OFFLINE", NULL, NULL },
{ UNIT_BRUSH, 0, NULL, "NOBRUSH", NULL, NULL },
{ UNIT_BRUSH, UNIT_BRUSH, "has brushes", "BRUSH", NULL, NULL },
{ UNIT_OFFL, 0, "on line", "ONLINE",
NULL, NULL, NULL, "Set unit online" },
{ UNIT_OFFL, UNIT_OFFL, "off line", "OFFLINE",
NULL, NULL, NULL, "Set unit offline" },
{ UNIT_BRUSH, 0, NULL, "NOBRUSH",
NULL, NULL, NULL, "Disable brushes" },
{ UNIT_BRUSH, UNIT_BRUSH, "has brushes", "BRUSH",
NULL, NULL, NULL, "Enable brushes" },
{ MTAB_XTD|MTAB_VUN|MTAB_NMO, RLDS_CVO, "open", "OPEN", &rl_set_cover, &rl_show_cover, NULL },
{ MTAB_XTD|MTAB_VUN, 0, NULL, "CLOSED", &rl_set_cover, NULL, NULL },
{ MTAB_XTD|MTAB_VUN|MTAB_NMO, 0, "load", "LOAD", &rl_set_load, &rl_show_load, NULL },
{ MTAB_XTD|MTAB_VUN, 1, NULL, "UNLOAD", &rl_set_load, NULL, NULL },
{ MTAB_XTD|MTAB_VUN|MTAB_NMO, 0, "DSTATE", NULL, NULL, &rl_show_dstate, NULL },
{ MTAB_XTD|MTAB_VUN|MTAB_NMO, RLDS_CVO, "open", "OPEN",
&rl_set_cover, &rl_show_cover, NULL, "Drive cover" },
{ MTAB_XTD|MTAB_VUN, 0, NULL, "CLOSED",
&rl_set_cover, NULL, NULL, "Close drive cover" },
{ MTAB_XTD|MTAB_VUN|MTAB_NMO, 0, "load", "LOAD",
&rl_set_load, &rl_show_load, NULL, "Load drive" },
{ MTAB_XTD|MTAB_VUN, 1, NULL, "UNLOAD",
&rl_set_load, NULL, NULL, "Unload drive" },
{ MTAB_XTD|MTAB_VUN|MTAB_NMO, 0, "DSTATE", NULL,
NULL, &rl_show_dstate, NULL, "Display drive state" },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK", &rl_set_bad },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable disk drive" },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED",
NULL, NULL, NULL, "Write lock disk drive" },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK",
&rl_set_bad, NULL, NULL, "Write bad block table on last track" },
{ (UNIT_RL02+UNIT_ATT), UNIT_ATT, "RL01", NULL, NULL },
{ (UNIT_RL02+UNIT_ATT), (UNIT_RL02+UNIT_ATT), "RL02", NULL, NULL },
{ (UNIT_AUTO+UNIT_RL02+UNIT_ATT), 0, "RL01", NULL, NULL },
{ (UNIT_AUTO+UNIT_RL02+UNIT_ATT), UNIT_RL02, "RL02", NULL, NULL },
{ (UNIT_AUTO+UNIT_RL02+UNIT_ATT), 0, "RL01", NULL,
NULL, NULL, NULL, "Set drive type RL01" },
{ (UNIT_AUTO+UNIT_RL02+UNIT_ATT), UNIT_RL02, "RL02", NULL,
NULL, NULL, NULL, "Set drive type RL02" },
{ (UNIT_AUTO+UNIT_ATT), UNIT_AUTO, "autosize", NULL, NULL },
{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE", NULL },
{ (UNIT_AUTO+UNIT_RL02), 0, NULL, "RL01", &rl_set_size },
{ (UNIT_AUTO+UNIT_RL02), UNIT_RL02, NULL, "RL02", &rl_set_size },
{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE",
NULL, NULL, NULL, "set type based on file size at ATTACH" },
{ (UNIT_AUTO+UNIT_RL02), 0, NULL, "RL01",
&rl_set_size, NULL, NULL, "Set drive type RL01" },
{ (UNIT_AUTO+UNIT_RL02), UNIT_RL02, NULL, "RL02",
&rl_set_size, NULL, NULL, "Set drive type RL02" },
{ MTAB_XTD|MTAB_VDV, 010, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL },
&set_vec, &show_vec, NULL, "Interrupt vector" },
{ 0 }
};

37
PDP11/pdp11_rp.c
View file

@ -638,10 +638,12 @@ REG rp_reg[] = {
};
MTAB rp_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "MASSBUS", "MASSBUS", NULL, &mba_show_num },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK", &rp_set_bad },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable disk drive" },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED",
NULL, NULL, NULL, "Write lock disk drive" },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK",
&rp_set_bad, NULL, NULL, "write bad block table on last track" },
{ (UNIT_DTYPE+UNIT_ATT), (RM03_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RM03", NULL, NULL },
{ (UNIT_DTYPE+UNIT_ATT), (RP04_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
@ -667,19 +669,20 @@ MTAB rp_mod[] = {
{ (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (RP07_DTYPE << UNIT_V_DTYPE),
"RP07", NULL, NULL },
{ (UNIT_AUTO+UNIT_ATT), UNIT_AUTO, "autosize", NULL, NULL },
{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE", NULL },
{ (UNIT_AUTO+UNIT_DTYPE), (RM03_DTYPE << UNIT_V_DTYPE),
NULL, "RM03", &rp_set_size },
{ (UNIT_AUTO+UNIT_DTYPE), (RP04_DTYPE << UNIT_V_DTYPE),
NULL, "RP04", &rp_set_size },
{ (UNIT_AUTO+UNIT_DTYPE), (RM80_DTYPE << UNIT_V_DTYPE),
NULL, "RM80", &rp_set_size },
{ (UNIT_AUTO+UNIT_DTYPE), (RP06_DTYPE << UNIT_V_DTYPE),
NULL, "RP06", &rp_set_size },
{ (UNIT_AUTO+UNIT_DTYPE), (RM05_DTYPE << UNIT_V_DTYPE),
NULL, "RM05", &rp_set_size },
{ (UNIT_AUTO+UNIT_DTYPE), (RP07_DTYPE << UNIT_V_DTYPE),
NULL, "RP07", &rp_set_size },
{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE",
NULL, NULL, NULL, "set type based on file size at ATTACH" },
{ (UNIT_AUTO+UNIT_DTYPE), (RM03_DTYPE << UNIT_V_DTYPE), NULL, "RM03",
&rp_set_size, NULL, NULL, "Set type to RM03" },
{ (UNIT_AUTO+UNIT_DTYPE), (RP04_DTYPE << UNIT_V_DTYPE), NULL, "RP04",
&rp_set_size, NULL, NULL, "Set type to RP04" },
{ (UNIT_AUTO+UNIT_DTYPE), (RM80_DTYPE << UNIT_V_DTYPE), NULL, "RM80",
&rp_set_size, NULL, NULL, "Set type to RM80" },
{ (UNIT_AUTO+UNIT_DTYPE), (RP06_DTYPE << UNIT_V_DTYPE), NULL, "RP06",
&rp_set_size, NULL, NULL, "Set type to RP06" },
{ (UNIT_AUTO+UNIT_DTYPE), (RM05_DTYPE << UNIT_V_DTYPE), NULL, "RM05",
&rp_set_size, NULL, NULL, "Set type to RM05" },
{ (UNIT_AUTO+UNIT_DTYPE), (RP07_DTYPE << UNIT_V_DTYPE), NULL, "RP07",
&rp_set_size, NULL, NULL, "Set type to RP07" },
{ 0 }
};

156
PDP11/pdp11_rq.c
View file

@ -916,91 +916,93 @@ REG rq_reg[] = {
};
MTAB rq_mod[] = {
{ UNIT_WLK, 0, NULL, "WRITEENABLED", &rq_set_wlk },
{ UNIT_WLK, UNIT_WLK, NULL, "LOCKED", &rq_set_wlk },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, RQ_SH_RI, "RINGS", NULL,
NULL, &rq_show_ctrl, 0 },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, RQ_SH_FR, "FREEQ", NULL,
NULL, &rq_show_ctrl, 0 },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, RQ_SH_RS, "RESPQ", NULL,
NULL, &rq_show_ctrl, 0 },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, RQ_SH_UN, "UNITQ", NULL,
NULL, &rq_show_ctrl, 0 },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, RQ_SH_ALL, "ALL", NULL,
NULL, &rq_show_ctrl, 0 },
{ MTAB_XTD | MTAB_VDV, KLESI_CTYPE, NULL, "KLESI",
&rq_set_ctype, NULL, NULL },
{ MTAB_XTD | MTAB_VDV, RUX50_CTYPE, NULL, "RUX50",
&rq_set_ctype, NULL, NULL },
{ MTAB_XTD | MTAB_VDV, UDA50_CTYPE, NULL, "UDA50",
&rq_set_ctype, NULL, NULL },
{ MTAB_XTD | MTAB_VDV, RQDX3_CTYPE, NULL, "RQDX3",
&rq_set_ctype, NULL, NULL },
{ MTAB_XTD | MTAB_VUN | MTAB_NMO, 0, "UNITQ", NULL,
NULL, &rq_show_unitq, 0 },
{ MTAB_XTD | MTAB_VUN, 0, "WRITE", NULL,
NULL, &rq_show_wlk, NULL },
{ MTAB_XTD | MTAB_VUN, RX50_DTYPE, NULL, "RX50",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RX33_DTYPE, NULL, "RX33",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RD31_DTYPE, NULL, "RD31",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RD32_DTYPE, NULL, "RD32",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RD51_DTYPE, NULL, "RD51",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RD52_DTYPE, NULL, "RD52",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RD53_DTYPE, NULL, "RD53",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RD54_DTYPE, NULL, "RD54",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RA60_DTYPE, NULL, "RA60",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RA81_DTYPE, NULL, "RA81",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RA82_DTYPE, NULL, "RA82",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RRD40_DTYPE, NULL, "RRD40",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RRD40_DTYPE, NULL, "CDROM",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RA71_DTYPE, NULL, "RA71",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RA72_DTYPE, NULL, "RA72",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RA90_DTYPE, NULL, "RA90",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RA92_DTYPE, NULL, "RA92",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RC25_DTYPE, NULL, "RC25",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RCF25_DTYPE, NULL, "RCF25",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RA80_DTYPE, NULL, "RA80",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, RA8U_DTYPE, NULL, "RAUSER",
&rq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VUN, 0, "TYPE", NULL,
NULL, &rq_show_type, NULL },
{ UNIT_NOAUTO, UNIT_NOAUTO, "noautosize", "NOAUTOSIZE", NULL },
{ UNIT_NOAUTO, 0, "autosize", "AUTOSIZE", NULL },
{ MTAB_XTD | MTAB_VUN, 0, "FORMAT", "FORMAT",
&sim_disk_set_fmt, &sim_disk_show_fmt, NULL },
{ UNIT_WLK, 0, NULL, "WRITEENABLED",
&rq_set_wlk, NULL, NULL, "Write enable disk drive" },
{ UNIT_WLK, UNIT_WLK, NULL, "LOCKED",
&rq_set_wlk, NULL, NULL, "Write lock disk drive" },
{ MTAB_XTD|MTAB_VUN, 0, "WRITE", NULL,
NULL, &rq_show_wlk, NULL, "Display drive writelock status" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, RQ_SH_RI, "RINGS", NULL,
NULL, &rq_show_ctrl, NULL, "Display command and response rings" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, RQ_SH_FR, "FREEQ", NULL,
NULL, &rq_show_ctrl, NULL, "Display free queue" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, RQ_SH_RS, "RESPQ", NULL,
NULL, &rq_show_ctrl, NULL, "Display response queue" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, RQ_SH_UN, "UNITQ", NULL,
NULL, &rq_show_ctrl, NULL, "Display all unit queues" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, RQ_SH_ALL, "ALL", NULL,
NULL, &rq_show_ctrl, NULL, "Display complete controller state" },
{ MTAB_XTD|MTAB_VDV, KLESI_CTYPE, NULL, "KLESI",
&rq_set_ctype, NULL, NULL, "Set KLESI Controller Type" },
{ MTAB_XTD|MTAB_VDV, RUX50_CTYPE, NULL, "RUX50",
&rq_set_ctype, NULL, NULL, "Set RUX50 Controller Type" },
{ MTAB_XTD|MTAB_VDV, UDA50_CTYPE, NULL, "UDA50",
&rq_set_ctype, NULL, NULL, "Set UDA50 Controller Type" },
{ MTAB_XTD|MTAB_VDV, RQDX3_CTYPE, NULL, "RQDX3",
&rq_set_ctype, NULL, NULL, "Set RQDX3 Controller Type" },
{ MTAB_XTD|MTAB_VUN|MTAB_NMO, 0, "UNITQ", NULL,
NULL, &rq_show_unitq, NULL, "Display unit queue" },
{ MTAB_XTD|MTAB_VUN, RX50_DTYPE, NULL, "RX50",
&rq_set_type, NULL, NULL, "Set RX50 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RX33_DTYPE, NULL, "RX33",
&rq_set_type, NULL, NULL, "Set RX33 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RD31_DTYPE, NULL, "RD31",
&rq_set_type, NULL, NULL, "Set RD31 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RD32_DTYPE, NULL, "RD32",
&rq_set_type, NULL, NULL, "Set RD32 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RD51_DTYPE, NULL, "RD51",
&rq_set_type, NULL, NULL, "Set RD51 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RD52_DTYPE, NULL, "RD52",
&rq_set_type, NULL, NULL, "Set RD52 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RD53_DTYPE, NULL, "RD53",
&rq_set_type, NULL, NULL, "Set RD53 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RD54_DTYPE, NULL, "RD54",
&rq_set_type, NULL, NULL, "Set RD54 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RA60_DTYPE, NULL, "RA60",
&rq_set_type, NULL, NULL, "Set RA60 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RA81_DTYPE, NULL, "RA81",
&rq_set_type, NULL, NULL, "Set RA81 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RA82_DTYPE, NULL, "RA82",
&rq_set_type, NULL, NULL, "Set RA82 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RRD40_DTYPE, NULL, "RRD40",
&rq_set_type, NULL, NULL, "Set RRD40 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RRD40_DTYPE, NULL, "CDROM",
&rq_set_type, NULL, NULL, "Set CDROM Disk Type" },
{ MTAB_XTD|MTAB_VUN, RA71_DTYPE, NULL, "RA71",
&rq_set_type, NULL, NULL, "Set RA71 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RA72_DTYPE, NULL, "RA72",
&rq_set_type, NULL, NULL, "Set RA72 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RA90_DTYPE, NULL, "RA90",
&rq_set_type, NULL, NULL, "Set RA90 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RA92_DTYPE, NULL, "RA92",
&rq_set_type, NULL, NULL, "Set RA92 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RC25_DTYPE, NULL, "RC25",
&rq_set_type, NULL, NULL, "Set RC25 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RCF25_DTYPE, NULL, "RCF25",
&rq_set_type, NULL, NULL, "Set RCF25 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RA80_DTYPE, NULL, "RA80",
&rq_set_type, NULL, NULL, "Set RA80 Disk Type" },
{ MTAB_XTD|MTAB_VUN, RA8U_DTYPE, NULL, "RAUSER",
&rq_set_type, NULL, NULL, "Set RAUSER=size Disk Type" },
{ MTAB_XTD|MTAB_VUN, 0, "TYPE", NULL,
NULL, &rq_show_type, NULL, "Display device type" },
{ UNIT_NOAUTO, UNIT_NOAUTO, "noautosize", "NOAUTOSIZE", NULL, NULL, NULL, "Disables disk autosize on attach" },
{ UNIT_NOAUTO, 0, "autosize", "AUTOSIZE", NULL, NULL, NULL, "Enables disk autosize on attach" },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
&sim_disk_set_fmt, &sim_disk_show_fmt, NULL, "Set/Display disk format (SIMH, VHD, RAW)" },
#if defined (VM_PDP11)
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD | MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
&set_addr_flt, NULL, NULL },
&set_addr_flt, NULL, NULL, "Enable autoconfiguration of address & vector" },
#else
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", NULL,
NULL, &show_addr, NULL },
NULL, &show_addr, NULL, "Bus address" },
#endif
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
NULL, &show_vec, NULL, "Interrupt vector" },
{ MTAB_XTD | MTAB_VDV, 0, "TYPE", NULL,
NULL, &rq_show_ctype, NULL },
NULL, &rq_show_ctype, NULL, "Display controller type" },
{ 0 }
};

25
PDP11/pdp11_ry.c
View file

@ -217,28 +217,33 @@ REG ry_reg[] = {
};
MTAB ry_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable disk drive" },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED",
NULL, NULL, NULL, "Write lock disk drive" },
{ (UNIT_DEN+UNIT_ATT), UNIT_ATT, "single density", NULL, NULL },
{ (UNIT_DEN+UNIT_ATT), (UNIT_DEN+UNIT_ATT), "double density", NULL, NULL },
{ (UNIT_AUTO+UNIT_DEN+UNIT_ATT), 0, "single density", NULL, NULL },
{ (UNIT_AUTO+UNIT_DEN+UNIT_ATT), UNIT_DEN, "double density", NULL, NULL },
{ (UNIT_AUTO+UNIT_ATT), UNIT_AUTO, "autosize", NULL, NULL },
{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE", NULL },
{ (UNIT_AUTO+UNIT_DEN), 0, NULL, "SINGLE", &ry_set_size },
{ (UNIT_AUTO+UNIT_DEN), UNIT_DEN, NULL, "DOUBLE", &ry_set_size },
{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE",
NULL },
{ (UNIT_AUTO+UNIT_DEN), 0, NULL, "SINGLE",
&ry_set_size },
{ (UNIT_AUTO+UNIT_DEN), UNIT_DEN, NULL, "DOUBLE",
&ry_set_size },
#if defined (VM_PDP11)
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
&set_addr, &show_addr, NULL, "Bus Address" },
{ MTAB_XTD | MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
&set_addr_flt, NULL, NULL },
&set_addr_flt, NULL, NULL, "Enable autoconfiguration of address & vector" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL },
&set_vec, &show_vec, NULL, "Interrupt vector" },
#else
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
NULL, &show_addr, NULL },
NULL, &show_addr, NULL, "Bus Address" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
NULL, &show_vec, NULL },
NULL, &show_vec, NULL, "Interrupt vector" },
#endif
{ 0 }
};

70
PDP11/pdp11_tq.c
View file

@ -474,45 +474,47 @@ REG tq_reg[] = {
};
MTAB tq_mod[] = {
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD | MTAB_VDV, TQ5_TYPE, NULL, "TK50",
&tq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VDV, TQ7_TYPE, NULL, "TK70",
&tq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VDV, TQ8_TYPE, NULL, "TU81",
&tq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VDV, TQU_TYPE, NULL, "TKUSER",
&tq_set_type, NULL, NULL },
{ MTAB_XTD | MTAB_VDV, 0, "TYPE", NULL,
NULL, &tq_show_type, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, TQ_SH_RI, "RINGS", NULL,
NULL, &tq_show_ctrl, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, TQ_SH_FR, "FREEQ", NULL,
NULL, &tq_show_ctrl, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, TQ_SH_RS, "RESPQ", NULL,
NULL, &tq_show_ctrl, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, TQ_SH_UN, "UNITQ", NULL,
NULL, &tq_show_ctrl, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, TQ_SH_ALL, "ALL", NULL,
NULL, &tq_show_ctrl, NULL },
{ MTAB_XTD | MTAB_VUN | MTAB_NMO, 0, "UNITQ", NULL,
NULL, &tq_show_unitq, NULL },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL },
{ MTAB_XTD|MTAB_VUN, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL },
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable tape drive" },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED",
NULL, NULL, NULL, "Write lock tape drive" },
{ MTAB_XTD|MTAB_VDV, TQ5_TYPE, NULL, "TK50",
&tq_set_type, NULL, NULL, "Set TK50 Device Type" },
{ MTAB_XTD|MTAB_VDV, TQ7_TYPE, NULL, "TK70",
&tq_set_type, NULL, NULL, "Set TK70 Device Type" },
{ MTAB_XTD|MTAB_VDV, TQ8_TYPE, NULL, "TU81",
&tq_set_type, NULL, NULL, "Set TU81 Device Type" },
{ MTAB_XTD|MTAB_VDV, TQU_TYPE, NULL, "TKUSER",
&tq_set_type, NULL, NULL, "Set TKUSER=size Device Type" },
{ MTAB_XTD|MTAB_VDV, 0, "TYPE", NULL,
NULL, &tq_show_type, NULL, "Display device type" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, TQ_SH_RI, "RINGS", NULL,
NULL, &tq_show_ctrl, NULL, "Display command and response rings" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, TQ_SH_FR, "FREEQ", NULL,
NULL, &tq_show_ctrl, NULL, "Display free queue" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, TQ_SH_RS, "RESPQ", NULL,
NULL, &tq_show_ctrl, NULL, "Display response queue" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, TQ_SH_UN, "UNITQ", NULL,
NULL, &tq_show_ctrl, NULL, "Display all unit queues" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, TQ_SH_ALL, "ALL", NULL,
NULL, &tq_show_ctrl, NULL, "Display complete controller state" },
{ MTAB_XTD|MTAB_VUN|MTAB_NMO, 0, "UNITQ", NULL,
NULL, &tq_show_unitq, NULL, "Display unit queue" },
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL, "Set/Display tape format (SIMH, E11, TPC, P7B)" },
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL, "Set/Display capacity" },
#if defined (VM_PDP11)
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
{ MTAB_XTD | MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
&set_addr_flt, NULL, NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 004, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, NULL, "AUTOCONFIGURE",
&set_addr_flt, NULL, NULL, "Enable autoconfiguration of address & vector" },
#else
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", NULL,
NULL, &show_addr, NULL },
NULL, &show_addr, NULL, "Bus address" },
#endif
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
NULL, &show_vec, NULL, "Interrupt vector" },
{ 0 }
};

22
PDP11/pdp11_ts.c
View file

@ -348,16 +348,18 @@ REG ts_reg[] = {
};
MTAB ts_mod[] = {
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL },
{ MTAB_XTD|MTAB_VUN, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL },
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL },
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable tape drive" },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED",
NULL, NULL, NULL, "Write lock tape drive" },
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL, "Set/Display tape format (SIMH, E11, TPC, P7B)" },
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL, "Set/Display capacity" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 004, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL, "Interrupt vector" },
{ 0 }
};

29
PDP11/pdp11_tu.c
View file

@ -297,22 +297,27 @@ MTAB tu_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "MASSBUS", "MASSBUS", NULL, &mba_show_num },
#if defined (VM_PDP11)
{ MTAB_XTD|MTAB_VDV, 0, "FORMATTER", "TM02",
&tu_set_fmtr, &tu_show_fmtr },
&tu_set_fmtr, &tu_show_fmtr, NULL, "Set controller type to TM02" },
{ MTAB_XTD|MTAB_VDV, 1, NULL, "TM03",
&tu_set_fmtr, NULL },
&tu_set_fmtr, NULL, NULL, "Set controller type to TM03" },
#else
{ MTAB_XTD|MTAB_VDV, 0, "FORMATTER", NULL,
NULL, &tu_show_fmtr },
NULL, &tu_show_fmtr, NULL, "Display controller type" },
#endif
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
{ UNIT_TYPE, UNIT_TE16, "TE16", "TE16", NULL },
{ UNIT_TYPE, UNIT_TU45, "TU45", "TU45", NULL },
{ UNIT_TYPE, UNIT_TU77, "TU77", "TU77", NULL },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL },
{ MTAB_XTD|MTAB_VUN, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL },
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable tape drive" },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED",
NULL, NULL, NULL, "Write lock tape drive" },
{ UNIT_TYPE, UNIT_TE16, "TE16", "TE16",
NULL, NULL, NULL, "Set drive type to TE16" },
{ UNIT_TYPE, UNIT_TU45, "TU45", "TU45",
NULL, NULL, NULL, "Set drive type to TU45" },
{ UNIT_TYPE, UNIT_TU77, "TU77", "TU77",
NULL, NULL, NULL, "Set drive type to TU77" },
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL, "Set/Display tape format (SIMH, E11, TPC, P7B)" },
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL, "Set/Display capacity" },
{ 0 }
};

78
PDP11/pdp11_vh.c
View file

@ -374,43 +374,51 @@ static const REG vh_reg[] = {
static const MTAB vh_mod[] = {
#if !UNIBUS
{ UNIT_MODEDHU, 0, "DHV mode", "DHV", &vh_setmode },
{ UNIT_MODEDHU, 0, "DHV mode", "DHV",
&vh_setmode, NULL, NULL, "Set DHV mode" },
#endif
{ UNIT_MODEDHU, UNIT_MODEDHU, "DHU mode", "DHU", &vh_setmode },
{ UNIT_FASTDMA, 0, NULL, "NORMAL", NULL },
{ UNIT_FASTDMA, UNIT_FASTDMA, "fast DMA", "FASTDMA", NULL },
{ UNIT_MODEM, 0, NULL, "NOMODEM", NULL },
{ UNIT_MODEM, UNIT_MODEM, "modem", "MODEM", NULL },
{ UNIT_HANGUP, 0, NULL, "NOHANGUP", NULL },
{ UNIT_HANGUP, UNIT_HANGUP, "hangup", "HANGUP", NULL },
{ MTAB_XTD|MTAB_VDV, 020, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &vh_show_vec, (void *) &vh_desc },
{ UNIT_MODEDHU, UNIT_MODEDHU, "DHU mode", "DHU",
&vh_setmode, NULL, NULL, "Set DHU mode" },
{ UNIT_FASTDMA, 0, NULL, "NORMAL",
NULL, NULL, NULL, "Set Normal DMA mode" },
{ UNIT_FASTDMA, UNIT_FASTDMA, "fast DMA", "FASTDMA",
NULL, NULL, NULL, "Enable Fast DMA mode" },
{ UNIT_MODEM, 0, NULL, "NOMODEM",
NULL, NULL, NULL, "Disable modem control" },
{ UNIT_MODEM, UNIT_MODEM, "Modem", "MODEM",
NULL, NULL, NULL, "Enable modem control" },
{ UNIT_HANGUP, 0, NULL, "NOHANGUP",
NULL, NULL, NULL, "Disable disconnect on DTR drop" },
{ UNIT_HANGUP, UNIT_HANGUP, "Hangup", "HANGUP",
NULL, NULL, NULL, "Enable disconnect on DTR drop" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 020, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "VECTOR", "VECTOR",
&set_vec, &vh_show_vec, (void *) &vh_desc, "Interrupt vector" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
&set_addr_flt, NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "LINES", "LINES",
&vh_setnl, &tmxr_show_lines, (void *) &vh_desc },
&set_addr_flt, NULL, NULL, "Enable autoconfiguration of address & vector" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "LINES", "LINES=n",
&vh_setnl, &tmxr_show_lines, (void *) &vh_desc, "Display number of lines" },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &vh_desc },
{ MTAB_XTD|MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &vh_desc },
{ MTAB_XTD|MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &tmxr_show_cstat, (void *) &vh_desc },
{ MTAB_XTD|MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &vh_desc },
{ MTAB_XTD|MTAB_VDV | MTAB_NMO, 0, "DETAIL", NULL,
NULL, &vh_show_detail, NULL },
{ MTAB_XTD|MTAB_VDV | MTAB_NMO, 0, "RBUF", NULL,
NULL, &vh_show_rbuf, NULL },
{ MTAB_XTD|MTAB_VDV | MTAB_NMO, 0, "TXQ", NULL,
NULL, &vh_show_txq, NULL },
{ MTAB_XTD|MTAB_VDV | MTAB_NC, 0, NULL, "LOG",
&vh_set_log, NULL, &vh_desc },
{ MTAB_XTD|MTAB_VDV | MTAB_NC, 0, NULL, "NOLOG",
&vh_set_nolog, NULL, &vh_desc },
{ MTAB_XTD|MTAB_VDV | MTAB_NMO, 0, "LOG", NULL,
NULL, &vh_show_log, &vh_desc },
NULL, &tmxr_show_summ, (void *) &vh_desc, "Display a summary of line states" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &vh_desc, "Display current connections" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &tmxr_show_cstat, (void *) &vh_desc, "Display multiplexer statistics" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &vh_desc, "Disconnect a specific line" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "DETAIL", NULL,
NULL, &vh_show_detail, NULL, "Display detailed multiplexer status" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "RBUF", NULL,
NULL, &vh_show_rbuf, NULL, "Display recieve buffer" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "TXQ", NULL,
NULL, &vh_show_txq, NULL, "Display transmit queue for each mux" },
{ MTAB_XTD|MTAB_VDV|MTAB_NC, 0, NULL, "LOG=n=file",
&vh_set_log, NULL, &vh_desc, "Display logging" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, NULL, "NOLOG",
&vh_set_nolog, NULL, &vh_desc, "Disable logging on designated line" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "LOG", NULL,
NULL, &vh_show_log, &vh_desc, "Display logging for all lines" },
{ 0 }
};
@ -1429,7 +1437,7 @@ static t_stat vh_show_txq ( FILE *st,
int32 i;
for (i = 0; i < txq_idx[0]; i++)
fprintf (st, "%02d: %06o\n\r", i, vh_txq[0][i]);
fprintf (st, "%02d: %06o\n", i, vh_txq[0][i]);
return (SCPE_OK);
}

24
PDP11/pdp11_xq.c
View file

@ -437,30 +437,30 @@ REG xqb_reg[] = {
};
MTAB xq_mod[] = {
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", NULL,
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, NULL, "Qbus address" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL, "Interrupt vector" },
{ MTAB_XTD | MTAB_VDV, 0, "MAC", "MAC=xx:xx:xx:xx:xx:xx",
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "MAC", "MAC=xx:xx:xx:xx:xx:xx",
&xq_setmac, &xq_showmac, NULL, "MAC address" },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "ETH", NULL,
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "ETH", NULL,
NULL, &eth_show, NULL, "Display attachable devices" },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "FILTERS", NULL,
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "FILTERS", NULL,
NULL, &xq_show_filters, NULL, "Display address filters" },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATS", "STATS",
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "STATS", "STATS",
&xq_set_stats, &xq_show_stats, NULL, "Display or reset statistics" },
{ MTAB_XTD | MTAB_VDV, 0, "TYPE", "TYPE={DEQNA|DELQA|DELQA-T}",
&xq_set_type, &xq_show_type, NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "TYPE", "TYPE={DEQNA|DELQA|DELQA-T}",
&xq_set_type, &xq_show_type, NULL, "Display current device type being simulated" },
#ifdef USE_READER_THREAD
{ MTAB_XTD | MTAB_VDV, 0, "POLL", "POLL={DEFAULT|DISABLED|4..2500|DELAY=nnn}",
&xq_set_poll, &xq_show_poll, NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "POLL", "POLL={DEFAULT|DISABLED|4..2500|DELAY=nnn}",
&xq_set_poll, &xq_show_poll, NULL, "Display the current polling mode" },
#else
{ MTAB_XTD | MTAB_VDV, 0, "POLL", "POLL={DEFAULT|DISABLED|4..2500}",
&xq_set_poll, &xq_show_poll, NULL },
&xq_set_poll, &xq_show_poll, NULL, "Display the current polling mode" },
#endif
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "SANITY", "SANITY={ON|OFF}",
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_VALR, 0, "SANITY", "SANITY={ON|OFF}",
&xq_set_sanity, &xq_show_sanity, NULL, "Sanity timer" },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO , 0, "LEDS", NULL,
{ MTAB_XTD|MTAB_VDV|MTAB_NMO , 0, "LEDS", NULL,
NULL, &xq_show_leds, NULL, "Display status LEDs" },
{ 0 },
};

18
PDP11/pdp11_xu.c
View file

@ -149,27 +149,27 @@ struct xu_device xua = {
MTAB xu_mod[] = {
#if defined (VM_PDP11)
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 010, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
{ MTAB_XTD | MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
{ MTAB_XTD|MTAB_VDV, 0, NULL, "AUTOCONFIGURE",
&set_addr_flt, NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "VECTOR", NULL,
&set_vec, &show_vec, NULL },
#else
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", NULL,
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, NULL, "Unibus address" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL, "Interrupt vector" },
#endif
{ MTAB_XTD | MTAB_VDV, 0, "MAC", "MAC=xx:xx:xx:xx:xx:xx",
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "MAC", "MAC=xx:xx:xx:xx:xx:xx",
&xu_setmac, &xu_showmac, NULL, "MAC address" },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "ETH", NULL,
{ MTAB_XTD |MTAB_VDV|MTAB_NMO, 0, "ETH", NULL,
NULL, &eth_show, NULL, "Display attachable devices" },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATS", "STATS",
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "STATS", "STATS",
&xu_set_stats, &xu_show_stats, NULL, "Display or reset statistics" },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "FILTERS", NULL,
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "FILTERS", NULL,
NULL, &xu_show_filters, NULL, "Display address filters" },
{ MTAB_XTD | MTAB_VDV, 0, "TYPE", "TYPE={DEUNA|DELUA}",
{ MTAB_XTD|MTAB_VDV, 0, "TYPE", "TYPE={DEUNA|DELUA}",
&xu_set_type, &xu_show_type, NULL },
{ 0 },
};

12
VAX/vax610_defs.h
View file

@ -94,14 +94,14 @@
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#undef PAMASK
#define PAMASK 0x203FFFFF /* KA610 needs a special mask */
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 19), NULL, "512k", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 19), NULL, "512k", &cpu_set_size, NULL, NULL, "Set Memory to 512K bytes" },\
{ UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size, NULL, NULL, "Set Memory to 1M bytes" }, \
{ UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \
{ UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size, NULL, NULL, "Set Memory to 4M bytes" }
#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "LEDS", NULL, \
NULL, &cpu_show_leds }, \
NULL, &cpu_show_leds, NULL, "Display the CPU LED values" }, \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model },
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }
/* Qbus I/O page */

6
VAX/vax610_io.c
View file

@ -62,11 +62,11 @@ REG qba_reg[] = {
MTAB qba_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
NULL, &show_iospace, NULL, "Display I/O space address map" },
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon },
&set_autocon, &show_autocon, NULL, "Enable/Display autoconfiguration" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
&set_autocon, NULL },
&set_autocon, NULL, NULL, "Disable autoconfiguration" },
{ 0 }
};

15
VAX/vax610_stddev.c
View file

@ -120,10 +120,9 @@ REG tti_reg[] = {
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};
@ -160,10 +159,10 @@ REG tto_reg[] = {
};
MTAB tto_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "Set 7 bit mode (suppress non printing)" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};

31
VAX/vax630_defs.h
View file

@ -89,17 +89,6 @@
#define MT_MBRK 60 /* microbreak */
#define MT_MAX 63 /* last valid IPR */
/* CPU */
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model }, \
{ MTAB_XTD|MTAB_VDV, 0, "DIAG", "DIAG={FULL|MIN}", \
&sysd_set_diag, &sysd_show_diag }, \
{ MTAB_XTD|MTAB_VDV, 0, "AUTOBOOT", "AUTOBOOT", \
&sysd_set_halt, &sysd_show_halt }, \
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "NOAUTOBOOT", "NOAUTOBOOT",\
&sysd_set_halt, &sysd_show_halt },
/* Memory */
#define MAXMEMWIDTH 24 /* max mem, std KA655 */
@ -109,12 +98,20 @@
#define INITMEMSIZE (1 << 24) /* initial memory size */
#define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 23) + (1u << 22), NULL, "12M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size, NULL, NULL, "Set Memory to 1M bytes" }, \
{ UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \
{ UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size, NULL, NULL, "Set Memory to 4M bytes" }, \
{ UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }, \
{ UNIT_MSIZE, (1u << 23) + (1u << 22), NULL, "12M", &cpu_set_size, NULL, NULL, "Set Memory to 12M bytes" }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }
#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }, \
{ MTAB_XTD|MTAB_VDV, 0, "DIAG", "DIAG={FULL|MIN}", \
&sysd_set_diag, &sysd_show_diag, NULL, "Set/Show boot rom diagnostic mode" }, \
{ MTAB_XTD|MTAB_VDV, 0, "AUTOBOOT", "AUTOBOOT", \
&sysd_set_halt, &sysd_show_halt, NULL, "Enable autoboot (Disable Halt)" }, \
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "NOAUTOBOOT", "NOAUTOBOOT", \
&sysd_set_halt, &sysd_show_halt, NULL, "Disable autoboot (Enable Halt)" }
/* Qbus I/O page */

8
VAX/vax630_io.c
View file

@ -105,13 +105,13 @@ REG qba_reg[] = {
MTAB qba_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
NULL, &show_iospace, NULL, "Display I/O space address map" },
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon },
&set_autocon, &show_autocon, NULL, "Enable/Display autoconfiguration" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
&set_autocon, NULL },
&set_autocon, NULL, NULL, "Disable autoconfiguration" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
NULL, &qba_show_virt },
NULL, &qba_show_virt, NULL, "Display translation for Qbus address arg" },
{ 0 }
};

15
VAX/vax630_stddev.c
View file

@ -95,10 +95,9 @@ REG tti_reg[] = {
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};
@ -135,10 +134,10 @@ REG tto_reg[] = {
};
MTAB tto_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "Set 7 bit mode (suppress non printing)" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};

42
VAX/vax630_sysdev.c
View file

@ -154,12 +154,14 @@ t_bool ka_hltenab = TRUE; /* Halt Enable / Autoboo
t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
t_stat rom_reset (DEVICE *dptr);
t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
t_stat rom_set_diag (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat rom_show_diag (FILE *st, UNIT *uptr, int32 val, void *desc);
char *rom_description (DEVICE *dptr);
t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
t_stat nvr_reset (DEVICE *dptr);
t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
t_stat nvr_attach (UNIT *uptr, char *cptr);
t_stat nvr_detach (UNIT *uptr);
char *nvr_description (DEVICE *dptr);
@ -209,8 +211,8 @@ REG rom_reg[] = {
};
MTAB rom_mod[] = {
{ UNIT_NODELAY, UNIT_NODELAY, "fast access", "NODELAY", NULL },
{ UNIT_NODELAY, 0, "1usec calibrated access", "DELAY", NULL },
{ UNIT_NODELAY, UNIT_NODELAY, "fast access", "NODELAY", NULL, NULL, NULL, "Disable calibrated ROM access speed" },
{ UNIT_NODELAY, 0, "1usec calibrated access", "DELAY", NULL, NULL, NULL, "Enable calibrated ROM access speed" },
{ 0 }
};
@ -219,7 +221,7 @@ DEVICE rom_dev = {
1, 16, ROMAWIDTH, 4, 16, 32,
&rom_ex, &rom_dep, &rom_reset,
NULL, NULL, NULL,
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, 0, 0, NULL, NULL, NULL, &rom_help, NULL, NULL,
&rom_description
};
@ -242,7 +244,7 @@ DEVICE nvr_dev = {
1, 16, NVRAWIDTH, 4, 16, 32,
&nvr_ex, &nvr_dep, &nvr_reset,
NULL, &nvr_attach, &nvr_detach,
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, 0, 0, NULL, NULL, NULL, &nvr_help, NULL, NULL,
&nvr_description
};
@ -400,6 +402,27 @@ if (rom == NULL)
return SCPE_OK;
}
t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{
fprintf (st, "Read-only memory (ROM)\n\n");
fprintf (st, "The boot ROM consists of a single unit, simulating the 64KB boot ROM. It has\n");
fprintf (st, "no registers. The boot ROM is loaded with a binary byte stream using the \n");
fprintf (st, "LOAD -r command:\n\n");
fprintf (st, " LOAD -r KA630.BIN load ROM image KA630.BIN\n\n");
fprintf (st, "ROM accesses a use a calibrated delay that slows ROM-based execution to about\n");
fprintf (st, "500K instructions per second. This delay is required to make the power-up\n");
fprintf (st, "self-test routines run correctly on very fast hosts. The delay is controlled\n");
fprintf (st, "with the commands:\n\n");
fprintf (st, " SET ROM NODELAY ROM runs like RAM\n");
fprintf (st, " SET ROM DELAY ROM runs slowly\n\n");
fprintf (st, "By default the memory power-up self-tests are skipped as they take a long time\n");
fprintf (st, "to complete. The self-test sequence can be controlled with the following\n");
fprintf (st, "commands:\n\n");
fprintf (st, " SET CPU DIAG=MIN Run minimal diagnostics (skip memory test)\n");
fprintf (st, " SET CPU DIAG=FULL Run full diagnostics\n\n");
return SCPE_OK;
}
char *rom_description (DEVICE *dptr)
{
return "read-only memory";
@ -471,6 +494,17 @@ if (nvr == NULL)
return SCPE_OK;
}
t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
{
fprintf (st, "Non-volatile Memory (NVR)\n\n");
fprintf (st, "The NVR simulates 50 bytes of battery-backed up memory.\n");
fprintf (st, "When the simulator starts, NVR is cleared to 0, and the battery-low indicator\n");
fprintf (st, "is set. Alternately, NVR can be attached to a file. This allows the NVR\n");
fprintf (st, "state to be preserved across simulator runs. Successfully attaching an NVR\n");
fprintf (st, "image clears the battery-low indicator.\n\n");
return SCPE_OK;
}
/* NVR attach */
t_stat nvr_attach (UNIT *uptr, char *cptr)

12
VAX/vax730_defs.h
View file

@ -125,14 +125,14 @@
#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
#define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \
{ UNIT_MSIZE, (2u << 20), NULL, "2M", &cpu_set_size }, \
{ UNIT_MSIZE, (3u << 20), NULL, "2M", &cpu_set_size }, \
{ UNIT_MSIZE, (4u << 20), NULL, "4M", &cpu_set_size }, \
{ UNIT_MSIZE, (5u << 20), NULL, "5M", &cpu_set_size }
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size, NULL, NULL, "Set Memory to 1M bytes" }, \
{ UNIT_MSIZE, (2u << 20), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \
{ UNIT_MSIZE, (3u << 20), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 3M bytes" }, \
{ UNIT_MSIZE, (4u << 20), NULL, "4M", &cpu_set_size, NULL, NULL, "Set Memory to 4M bytes" }, \
{ UNIT_MSIZE, (5u << 20), NULL, "5M", &cpu_set_size, NULL, NULL, "Set Memory to 5M bytes" }
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model },
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }
/* Unibus I/O registers */

2
VAX/vax730_mem.c
View file

@ -96,7 +96,7 @@ REG mctl_reg[] = {
MTAB mctl_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_MCTL, "NEXUS", NULL,
NULL, &show_nexus },
NULL, &show_nexus, NULL, "Display nexus" },
{ 0 }
};

21
VAX/vax730_rb.c
View file

@ -259,19 +259,24 @@ DEBTAB rb_debug[] = {
};
MTAB rb_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK", &rb_set_bad },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable disk drive" },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED",
NULL, NULL, NULL, "Write lock disk drive" },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK",
&rb_set_bad, NULL, NULL, "write bad block table on last track" },
{ (UNIT_RB80+UNIT_ATT), UNIT_ATT, "RB02", NULL, NULL },
{ (UNIT_RB80+UNIT_ATT), (UNIT_RB80+UNIT_ATT), "RB80", NULL, NULL },
{ (UNIT_RB80+UNIT_ATT), 0, "RB02", NULL, NULL },
{ (UNIT_RB80+UNIT_ATT), UNIT_RB80, "RB80", NULL, NULL },
{ (UNIT_RB80), 0, NULL, "RB02", &rb_set_size },
{ (UNIT_RB80), UNIT_RB80, NULL, "RB80", &rb_set_size },
{ MTAB_XTD|MTAB_VDV, 010, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
{ (UNIT_RB80), 0, NULL, "RB02",
&rb_set_size, NULL, NULL, "Set type to RB02" },
{ (UNIT_RB80), UNIT_RB80, NULL, "RB80",
&rb_set_size, NULL, NULL, "Set type to RB80" },
{ MTAB_XTD|MTAB_VDV, 0010, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL, "Bus address" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL },
&set_vec, &show_vec, NULL, "Interrupt vector" },
{ 0 }
};

14
VAX/vax730_stddev.c
View file

@ -254,8 +254,8 @@ REG tti_reg[] = {
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ 0 }
};
@ -289,9 +289,9 @@ REG tto_reg[] = {
};
MTAB tto_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "Set 7 bit mode (suppress non printing)" },
{ 0 }
};
@ -376,8 +376,8 @@ REG td_reg[] = {
};
MTAB td_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL, NULL, NULL, "Write enable TU58 drive" },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL, NULL, NULL, "Write lock TU58 drive" },
{ 0 }
};

10
VAX/vax730_uba.c
View file

@ -153,15 +153,15 @@ REG uba_reg[] = {
MTAB uba_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_UBA, "NEXUS", NULL,
NULL, &show_nexus },
NULL, &show_nexus, NULL, "Display nexus" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
NULL, &show_iospace, NULL, "Display I/O space address map" },
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon },
&set_autocon, &show_autocon, NULL, "Enable/Display autoconfiguration" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
&set_autocon, NULL },
&set_autocon, NULL, NULL, "Disable autoconfiguration" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
NULL, &uba_show_virt },
NULL, &uba_show_virt, NULL, "Display translation for Unibus address arg" },
{ 0 }
};

10
VAX/vax750_defs.h
View file

@ -146,13 +146,13 @@
#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
#define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size, NULL, NULL, "Set Memory to 1M bytes" }, \
{ UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size, NULL, NULL, "Set Memory to 2M bytes" }, \
{ UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size, NULL, NULL, "Set Memory to 4M bytes" }, \
{ UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model },
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }
/* Unibus I/O registers */

2
VAX/vax750_mem.c
View file

@ -105,7 +105,7 @@ REG mctl_reg[] = {
MTAB mctl_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_MCTL, "NEXUS", NULL,
NULL, &show_nexus },
NULL, &show_nexus, NULL, "Display Nexus" },
{ 0 }
};

14
VAX/vax750_stddev.c
View file

@ -254,8 +254,8 @@ REG tti_reg[] = {
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ 0 }
};
@ -289,9 +289,9 @@ REG tto_reg[] = {
};
MTAB tto_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "Set 7 bit mode (suppress non printing)" },
{ 0 }
};
@ -374,8 +374,8 @@ REG td_reg[] = {
};
MTAB td_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL, NULL, NULL, "Write enable TU58 drive" },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL, NULL, NULL, "Write lock TU58 drive" },
{ 0 }
};

10
VAX/vax750_uba.c
View file

@ -154,15 +154,15 @@ REG uba_reg[] = {
MTAB uba_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_UBA, "NEXUS", NULL,
NULL, &show_nexus },
NULL, &show_nexus, NULL, "Display nexus" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
NULL, &show_iospace, NULL, "Display I/O space address map" },
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon },
&set_autocon, &show_autocon, NULL, "Enable/Display autoconfiguration" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
&set_autocon, NULL },
&set_autocon, NULL, NULL, "Disable autoconfiguration" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
NULL, &uba_show_virt },
NULL, &uba_show_virt, NULL, "Display translation for Unibus address arg" },
{ 0 }
};

20
VAX/vax780_defs.h
View file

@ -148,11 +148,6 @@
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
/* CPU */
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={785|780}", \
&cpu_set_model, &cpu_show_model },
/* Memory */
#define MAXMEMWIDTH 23 /* max mem, MS780C */
@ -162,12 +157,15 @@
#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
#define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size }
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }, \
{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size, NULL, NULL, "Set Memory to 32M bytes" }, \
{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size, NULL, NULL, "Set Memory to 48M bytes" }, \
{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size, NULL, NULL, "Set Memory to 64M bytes" }, \
{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size, NULL, NULL, "Set Memory to 128M bytes" }
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }
/* Unibus I/O registers */

4
VAX/vax780_mem.c
View file

@ -114,7 +114,7 @@ REG mctl0_reg[] = {
MTAB mctl0_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_MCTL0, "NEXUS", NULL,
NULL, &show_nexus },
NULL, &show_nexus, NULL, "Display nexus" },
{ 0 }
};
@ -124,7 +124,7 @@ UNIT mctl1_unit = { UDATA (NULL, 0, 0) };
MTAB mctl1_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_MCTL1, "NEXUS", NULL,
NULL, &show_nexus },
NULL, &show_nexus, NULL, "Display nexus" },
{ 0 } };
REG mctl1_reg[] = {

14
VAX/vax780_stddev.c
View file

@ -270,8 +270,8 @@ REG tti_reg[] = {
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ 0 }
};
@ -305,9 +305,9 @@ REG tto_reg[] = {
};
MTAB tto_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "Set 7 bit mode (suppress non printing)" },
{ 0 }
};
@ -396,8 +396,8 @@ REG fl_reg[] = {
};
MTAB fl_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL, NULL, NULL, "Write enable floppy drive" },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL, NULL, NULL, "Write lock floppy drive" },
{ 0 }
};

10
VAX/vax780_uba.c
View file

@ -263,15 +263,15 @@ REG uba_reg[] = {
MTAB uba_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_UBA, "NEXUS", NULL,
NULL, &show_nexus },
NULL, &show_nexus, NULL, "Display nexus" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
NULL, &show_iospace, NULL, "Display I/O space address map" },
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon },
&set_autocon, &show_autocon, NULL, "Enable/Display autoconfiguration" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
&set_autocon, NULL },
&set_autocon, NULL, NULL, "Disable autoconfiguration" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
NULL, &uba_show_virt },
NULL, &uba_show_virt, NULL, "Display translation for Unibus address arg" },
{ 0 }
};

4
VAX/vax7x0_mba.c
View file

@ -296,7 +296,7 @@ REG mba0_reg[] = {
MTAB mba0_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_MBA0, "NEXUS", NULL,
NULL, &show_nexus },
NULL, &show_nexus, NULL, "Display nexus" },
{ 0 }
};
@ -306,7 +306,7 @@ UNIT mba1_unit = { UDATA (NULL, 0, 0) };
MTAB mba1_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_MBA1, "NEXUS", NULL,
NULL, &show_nexus },
NULL, &show_nexus, NULL, "Display nexus" },
{ 0 }
};

20
VAX/vax860_defs.h
View file

@ -174,11 +174,6 @@
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
/* CPU */
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={8600|8650}", \
&cpu_set_model, &cpu_show_model },
/* Memory */
#define MAXMEMWIDTH 25 /* max mem, 4MB boards */
@ -188,12 +183,15 @@
#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
#define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size }
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }, \
{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size, NULL, NULL, "Set Memory to 32M bytes" }, \
{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size, NULL, NULL, "Set Memory to 48M bytes" }, \
{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size, NULL, NULL, "Set Memory to 64M bytes" }, \
{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size, NULL, NULL, "Set Memory to 128M bytes" }
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model, NULL, "Display the simulator CPU Model" }
/* Unibus I/O registers */

14
VAX/vax860_stddev.c
View file

@ -289,8 +289,8 @@ REG tti_reg[] = {
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ 0 }
};
@ -329,9 +329,9 @@ REG tto_reg[] = {
};
MTAB tto_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "Set 7 bit mode (suppress non printing)" },
{ 0 }
};
@ -410,8 +410,8 @@ REG rlcs_reg[] = {
};
MTAB rlcs_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL, NULL, NULL, "Write enable console RL02 drive" },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL, NULL, NULL, "Write lock console RL02 drive" },
{ 0 }
};

14
VAX/vax_cpu.c
View file

@ -463,16 +463,16 @@ REG cpu_reg[] = {
};
MTAB cpu_mod[] = {
{ UNIT_CONH, 0, "HALT to SIMH", "SIMHALT", NULL },
{ UNIT_CONH, UNIT_CONH, "HALT to console", "CONHALT", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE={VMS|ULTRIX|NETBSD|OPENBSD|ULTRIXOLD|OPENBSDOLD|QUASIJARUS|32V|ALL}", &cpu_set_idle, &cpu_show_idle },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
{ UNIT_CONH, 0, "HALT to SIMH", "SIMHALT", NULL, NULL, NULL, "Set HALT to trap to simulator" },
{ UNIT_CONH, UNIT_CONH, "HALT to console", "CONHALT", NULL, NULL, NULL, "Set HALT to trap to console ROM" },
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE={VMS|ULTRIX|NETBSD|OPENBSD|ULTRIXOLD|OPENBSDOLD|QUASIJARUS|32V|ALL}", &cpu_set_idle, &cpu_show_idle, NULL, "Display idle detection mode" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL, NULL, "Disables idle detection" },
MEM_MODIFIERS, /* Model specific memory modifiers from vaxXXX_defs.h */
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
&cpu_set_hist, &cpu_show_hist },
&cpu_set_hist, &cpu_show_hist, NULL, "Displays instruction history" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
NULL, &cpu_show_virt },
CPU_MODEL_MODIFIERS /* Model specific cpu modifiers from vaxXXX_defs.h */
NULL, &cpu_show_virt, NULL, "show translation for address arg in KESU mode" },
CPU_MODEL_MODIFIERS, /* Model specific cpu modifiers from vaxXXX_defs.h */
{ 0 }
};

8
VAX/vax_io.c
View file

@ -164,13 +164,13 @@ REG qba_reg[] = {
MTAB qba_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
NULL, &show_iospace, NULL, "Display I/O space address map" },
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon },
&set_autocon, &show_autocon, NULL, "Enable/Display autoconfiguration" },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
&set_autocon, NULL },
&set_autocon, NULL, NULL, "Disable autoconfiguration" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
NULL, &qba_show_virt },
NULL, &qba_show_virt, NULL, "Display translation for Unibus address arg" },
{ 0 }
};

17
VAX/vax_stddev.c
View file

@ -151,10 +151,9 @@ REG tti_reg[] = {
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};
@ -191,10 +190,10 @@ REG tto_reg[] = {
};
MTAB tto_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "Set 7 bit mode (suppress non printing)" },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};
@ -236,7 +235,7 @@ REG clk_reg[] = {
};
MTAB clk_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};

8
VAX/vax_sysdev.c
View file

@ -314,8 +314,8 @@ REG rom_reg[] = {
};
MTAB rom_mod[] = {
{ UNIT_NODELAY, UNIT_NODELAY, "fast access", "NODELAY", NULL },
{ UNIT_NODELAY, 0, "1usec calibrated access", "DELAY", NULL },
{ UNIT_NODELAY, UNIT_NODELAY, "fast access", "NODELAY", NULL, NULL, NULL, "Disable calibrated ROM access speed" },
{ UNIT_NODELAY, 0, "1usec calibrated access", "DELAY", NULL, NULL, NULL, "Enable calibrated ROM access speed" },
{ 0 }
};
@ -375,7 +375,7 @@ REG csi_reg[] = {
};
MTAB csi_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};
@ -411,7 +411,7 @@ REG cso_reg[] = {
};
MTAB cso_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL, NULL, &show_vec, NULL, "Display interrupt vector" },
{ 0 }
};

2
VAX/vax_watch.c
View file

@ -81,7 +81,7 @@ REG wtc_reg[] = {
};
MTAB wtc_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "TIME", "TIME={VMS|STD}", &wtc_set, &wtc_show },
{ MTAB_XTD|MTAB_VDV, 0, "TIME", "TIME={VMS|STD}", &wtc_set, &wtc_show, NULL, "Display watch time mode" },
{ 0 }
};

25
VAX/vaxmod_defs.h
View file

@ -118,21 +118,20 @@
#define INITMEMSIZE (1 << 24) /* initial memory size */
#define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 29), NULL, "512M", &cpu_set_size }
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={VAXServer|MicroVAX}", \
&cpu_set_model, &cpu_show_model }, \
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size, NULL, NULL, "Set Memory to 8M bytes" }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }, \
{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size, NULL, NULL, "Set Memory to 32M bytes" }, \
{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size, NULL, NULL, "Set Memory to 48M bytes" }, \
{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size, NULL, NULL, "Set Memory to 64M bytes" }, \
{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size, NULL, NULL, "Set Memory to 128M bytes" }, \
{ UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size, NULL, NULL, "Set Memory to 256M bytes" }, \
{ UNIT_MSIZE, (1u << 29), NULL, "512M", &cpu_set_size, NULL, NULL, "Set Memory to 512M bytes" }
#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={VAXServer|MicroVAX}", \
&cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" }, \
{ MTAB_XTD|MTAB_VDV, 0, "AUTOBOOT", "AUTOBOOT", \
&sysd_set_halt, &sysd_show_halt }, \
&sysd_set_halt, &sysd_show_halt, NULL, "Enable autoboot (Disable Halt)" }, \
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "NOAUTOBOOT", "NOAUTOBOOT", \
&sysd_set_halt, &sysd_show_halt },
&sysd_set_halt, &sysd_show_halt, NULL, "Disable autoboot (Enable Halt)" }
/* Cache diagnostic space */