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PDP8: Added diagnostic mode for TSS/8

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Bob Supnik 2021-06-07 21:35:31 -07:00 • committed by Mark Pizzolato
parent 1a0024aabe
commit 2d20bc9d63
1 changed files with 20 additions and 5 deletions
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25
PDP8/pdp8_clk.c
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@ -1,6 +1,6 @@
/* pdp8_clk.c: PDP-8 real-time clock simulator
Copyright (c) 1993-2012, Robert M Supnik
Copyright (c) 1993-2021, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
clk real time clock
01-May-21 RMS Added diagnostic mode for TSS/8
18-Apr-12 RMS Added clock coscheduling
18-Jun-07 RMS Added UNIT_IDLE flag
01-Mar-03 RMS Aded SET/SHOW CLK FREQ support
@ -39,10 +40,13 @@
#include "pdp8_defs.h"
#define UNIT_V_DIAG (UNIT_V_UF + 0) /* diag mode */
#define UNIT_DIAG (1 << UNIT_V_DIAG)
extern int32 int_req, int_enable, dev_done, stop_inst;
int32 clk_tps = 60; /* ticks/second */
int32 tmxr_poll = 16000; /* term mux poll */
int32 tmxr_poll = 8000; /* term mux poll */
int32 clk (int32 IR, int32 AC);
t_stat clk_svc (UNIT *uptr);
@ -60,7 +64,7 @@ const char *clk_description (DEVICE *dptr);
DIB clk_dib = { DEV_CLK, 1, { &clk } };
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), 16000 };
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), 8000 };
REG clk_reg[] = {
{ FLDATAD (DONE, dev_done, INT_V_CLK, "device done flag") },
@ -79,6 +83,8 @@ MTAB clk_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "FREQUENCY", NULL,
NULL, &clk_show_freq, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev },
{ UNIT_DIAG, UNIT_DIAG, "diagnostic mode", "DIAG", NULL },
{ UNIT_DIAG, 0, NULL, "NORMAL", NULL },
{ 0 }
};
@ -144,10 +150,19 @@ switch (IR & 07) { /* decode IR<9:11> */
t_stat clk_svc (UNIT *uptr)
{
int32 t;
dev_done = dev_done | INT_CLK; /* set done */
int_req = INT_UPDATE; /* update interrupts */
tmxr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
if ((uptr->flags & UNIT_DIAG) != 0) { /* diagnostic mode? */
t = uptr->wait; /* fixed delay */
sim_activate (uptr, t);
}
else {
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate_after (uptr, 1000000/clk_tps); /* calibrated delay */
}
tmxr_poll = t; /* set mux poll */
return SCPE_OK;
}