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Added UBA register descriptions

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Mark Pizzolato 2013-01-22 16:07:55 -08:00
parent 71fcfacafc
commit 33897a6ff2
1 changed files with 27 additions and 27 deletions
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52
VAX/vax780_uba.c
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@ -230,32 +230,32 @@ DIB uba_dib = { TR_UBA, 0, &uba_rdreg, &uba_wrreg, 0, 0 };
UNIT uba_unit = { UDATA (&uba_svc, 0, 0) }; UNIT uba_unit = { UDATA (&uba_svc, 0, 0) };
REG uba_reg[] = { REG uba_reg[] = {
{ HRDATA (IPL14, int_req[0], 32), REG_RO }, { HRDATAD (IPL14, int_req[0], 32, "IPL 14 Interrupt Request"), REG_RO },
{ HRDATA (IPL15, int_req[1], 32), REG_RO }, { HRDATAD (IPL15, int_req[1], 32, "IPL 15 Interrupt Request"), REG_RO },
{ HRDATA (IPL16, int_req[2], 32), REG_RO }, { HRDATAD (IPL16, int_req[2], 32, "IPL 16 Interrupt Request"), REG_RO },
{ HRDATA (IPL17, int_req[3], 32), REG_RO }, { HRDATAD (IPL17, int_req[3], 32, "IPL 17 Interrupt Request"), REG_RO },
{ HRDATA (CNFR, uba_cnf, 32) }, { HRDATAD (CNFR, uba_cnf, 32, "config register") },
{ HRDATA (CR, uba_cr, 32) }, { HRDATAD (CR, uba_cr, 32, "control register") },
{ HRDATA (SR, uba_sr, 32) }, { HRDATAD (SR, uba_sr, 32, "status register") },
{ HRDATA (DR, uba_dr, 32) }, { HRDATAD (DR, uba_dr, 32, "diagnostic control register") },
{ FLDATA (INT, uba_int, 0) }, { FLDATAD (INT, uba_int, 0, "UBA interrupt") },
{ FLDATA (NEXINT, nexus_req[IPL_UBA], TR_UBA) }, { FLDATAD (NEXINT, nexus_req[IPL_UBA], TR_UBA, "") },
{ FLDATA (AIIP, uba_aiip, 0) }, { FLDATAD (AIIP, uba_aiip, 0, "adapter interrupt in progress") },
{ FLDATA (UIIP, uba_uiip, 0) }, { FLDATAD (UIIP, uba_uiip, 0, "Unibus interrupt in progress") },
{ HRDATA (FMER, uba_fmer, 32) }, { HRDATAD (FMER, uba_fmer, 32, "failing map register") },
{ HRDATA (FUBAR, uba_fubar, 32) }, { HRDATAD (FUBAR, uba_fubar, 32, "failing Unibus address") },
{ HRDATA (BRSVR0, uba_svr[0], 32) }, { HRDATAD (BRSVR0, uba_svr[0], 32, "diagnostic register 0") },
{ HRDATA (BRSVR1, uba_svr[1], 32) }, { HRDATAD (BRSVR1, uba_svr[1], 32, "diagnostic register 1") },
{ HRDATA (BRSVR2, uba_svr[2], 32) }, { HRDATAD (BRSVR2, uba_svr[2], 32, "diagnostic register 2") },
{ HRDATA (BRSVR3, uba_svr[3], 32) }, { HRDATAD (BRSVR3, uba_svr[3], 32, "diagnostic register 3") },
{ HRDATA (BRRVR4, uba_rvr[0], 32) }, { HRDATAD (BRRVR4, uba_rvr[0], 32, "vector register 0") },
{ HRDATA (BRRVR5, uba_rvr[1], 32) }, { HRDATAD (BRRVR5, uba_rvr[1], 32, "vector register 1") },
{ HRDATA (BRRVR6, uba_rvr[2], 32) }, { HRDATAD (BRRVR6, uba_rvr[2], 32, "vector register 2") },
{ HRDATA (BRRVR7, uba_rvr[3], 32) }, { HRDATAD (BRRVR7, uba_rvr[3], 32, "vector register 3") },
{ BRDATA (DPR, uba_dpr, 16, 32, 16) }, { BRDATAD (DPR, uba_dpr, 16, 32, 16, "number data paths") },
{ BRDATA (MAP, uba_map, 16, 32, 496) }, { BRDATAD (MAP, uba_map, 16, 32, 496, "Unibus map registers") },
{ DRDATA (AITIME, uba_aitime, 24), PV_LEFT + REG_NZ }, { DRDATAD (AITIME, uba_aitime, 24, "adapter init time"), PV_LEFT + REG_NZ },
{ DRDATA (UITIME, uba_uitime, 24), PV_LEFT + REG_NZ }, { DRDATAD (UITIME, uba_uitime, 24, "Unibus init time"), PV_LEFT + REG_NZ },
{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO }, { FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
{ NULL } { NULL }
}; };