PDP11, Unibus and Qbus VAX: Correct REG sizes in RQ, TQ and XQ devices

This commit is contained in:
Mark Pizzolato 2020-02-26 13:30:21 -08:00
parent 146f05d1f7
commit 3b802f644d
3 changed files with 6 additions and 6 deletions

View file

@ -994,7 +994,7 @@ REG rq_reg[] = {
{ URDATAD (PKTQ, rq_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
{ URDATAD (UFLG, rq_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0, "unit flags, units 0 to 3") },
{ URDATA (CAPAC, rq_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) },
{ URDATAD (PLUG, rq_unit[0].unit_plug, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
{ URDATAD (PLUG, rq_unit[0].unit_plug, 10, 32, 0, RQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
{ GRDATA (DEVADDR, rq_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, rq_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ DRDATA (DEVLBN, drv_tab[RA8U_DTYPE].lbn, 22), REG_HRO },
@ -1173,7 +1173,7 @@ REG rqb_reg[] = {
{ URDATAD (PKTQ, rqb_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
{ URDATAD (UFLG, rqb_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0, "unit flags, units 0 to 3") },
{ URDATA (CAPAC, rqb_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) },
{ URDATAD (PLUG, rqb_unit[0].unit_plug, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
{ URDATAD (PLUG, rqb_unit[0].unit_plug, 10, 32, 0, RQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
{ GRDATA (DEVADDR, rqb_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, rqb_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
@ -1246,7 +1246,7 @@ REG rqc_reg[] = {
{ URDATAD (PKTQ, rqc_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
{ URDATAD (UFLG, rqc_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0, "unit flags, units 0 to 3") },
{ URDATA (CAPAC, rqc_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) },
{ URDATAD (PLUG, rqc_unit[0].unit_plug, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
{ URDATAD (PLUG, rqc_unit[0].unit_plug, 10, 32, 0, RQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
{ GRDATA (DEVADDR, rqc_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, rqc_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
@ -1319,7 +1319,7 @@ REG rqd_reg[] = {
{ URDATAD (PKTQ, rqd_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
{ URDATAD (UFLG, rqd_unit[0].uf, DEV_RDX, 16, 0, RQ_NUMDR, 0, "unit flags, units 0 to 3") },
{ URDATA (CAPAC, rqd_unit[0].capac, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_HRO) },
{ URDATAD (PLUG, rqd_unit[0].unit_plug, 10, T_ADDR_W, 0, RQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
{ URDATAD (PLUG, rqd_unit[0].unit_plug, 10, 32, 0, RQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
{ GRDATA (DEVADDR, rqd_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, rqd_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }

View file

@ -465,7 +465,7 @@ REG tq_reg[] = {
{ DRDATAD (XTIME, tq_xtime, 24, "response time for data transfers"), PV_LEFT + REG_NZ },
{ DRDATAD (RWTIME, tq_rwtime, 32, "rewind time 2 sec (adjusted later)"), PV_LEFT + REG_NZ },
{ BRDATAD (PKTS, tq_pkt, DEV_RDX, 16, TQ_NPKTS * (TQ_PKT_SIZE_W + 1), "packet buffers, 33W each, 32 entries") },
{ URDATAD (PLUG, tq_unit[0].unit_plug, 10, T_ADDR_W, 0, TQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
{ URDATAD (PLUG, tq_unit[0].unit_plug, 10, 32, 0, TQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
{ DRDATA (DEVTYPE, tq_typ, 2), REG_HRO },
{ DRDATA (DEVCAP, drv_tab[TQU_TYPE].cap, T_ADDR_W), PV_LEFT | REG_HRO },
{ GRDATA (DEVADDR, tq_dib.ba, DEV_RDX, 32, 0), REG_HRO },

View file

@ -268,7 +268,7 @@ struct xq_device {
uint32 throttle_time; /* ms burst time window */
uint32 throttle_burst; /* packets passed with throttle_time which trigger throttling */
uint32 throttle_delay; /* ms to delay when throttling. 0 disables throttling */
uint16 startup_delay; /* instructions to delay when starting the receiver */
uint32 startup_delay; /* instructions to delay when starting the receiver */
/*- initialized values - DO NOT MOVE */
/* I/O register storage */