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Merge branch 'master' into AutoConfigure

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This commit is contained in:
Mark Pizzolato 2012-12-27 11:44:47 -08:00
commit 425ef4f113
26 changed files with 3489 additions and 34 deletions
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24
PDP11/pdp11_dmc.c
View file

@ -340,13 +340,13 @@ REG dmp_reg[] = {
MTAB dmc_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, "PEER", "PEER=address:port" ,&dmc_setpeer, &dmc_showpeer, NULL },
{ MTAB_XTD | MTAB_VDV, 0, "SPEED", "SPEED" ,&dmc_setspeed, &dmc_showspeed, NULL },
{ MTAB_XTD | MTAB_VDV, 0, "SPEED", "SPEED=bits/sec (0=unrestricted)" ,&dmc_setspeed, &dmc_showspeed, NULL },
#ifdef DMP
{ MTAB_XTD | MTAB_VDV, 0, "TYPE", "TYPE" ,&dmc_settype, &dmc_showtype, NULL },
#endif
{ MTAB_XTD | MTAB_VDV, 0, "LINEMODE", "LINEMODE" ,&dmc_setlinemode, &dmc_showlinemode, NULL },
{ MTAB_XTD | MTAB_VDV, 0, "LINEMODE", "LINEMODE={PRIMARY|SECONDARY}" ,&dmc_setlinemode, &dmc_showlinemode, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATS", "STATS" ,&dmc_setstats, &dmc_showstats, NULL },
{ MTAB_XTD | MTAB_VDV, 0, "CONNECTPOLL", "CONNECTPOLL" ,&dmc_setconnectpoll, &dmc_showconnectpoll, NULL },
{ MTAB_XTD | MTAB_VDV, 0, "CONNECTPOLL", "CONNECTPOLL=seconds" ,&dmc_setconnectpoll, &dmc_showconnectpoll, NULL },
{ MTAB_XTD | MTAB_VDV, 006, "ADDRESS", "ADDRESS", &set_addr, &show_addr, NULL },
{ MTAB_XTD |MTAB_VDV, 0, "VECTOR", "VECTOR", &set_vec, &show_vec, NULL },
{ 0 },
@ -415,10 +415,10 @@ UNIT_STATS dmp_stats[DMP_NUMDEVICE];
CTLR dmc_ctrls[] =
{
{ &dmc_csrs[0], &dmc_dev[0], Initialised, Idle, 0, 0, &dmc_line[0], &dmc_receive_queues[0], &dmc_transmit_queues[0], &dmc_stats[0], INVALID_SOCKET, -1, 30, DMC },
{ &dmc_csrs[1], &dmc_dev[1], Initialised, Idle, 0, 0, &dmc_line[1], &dmc_receive_queues[1], &dmc_transmit_queues[1], &dmc_stats[1], INVALID_SOCKET, -1, 30, DMC },
{ &dmc_csrs[2], &dmc_dev[2], Initialised, Idle, 0, 0, &dmc_line[2], &dmc_receive_queues[2], &dmc_transmit_queues[2], &dmc_stats[2], INVALID_SOCKET, -1, 30, DMC },
{ &dmc_csrs[3], &dmc_dev[3], Initialised, Idle, 0, 0, &dmc_line[3], &dmc_receive_queues[3], &dmc_transmit_queues[3], &dmc_stats[3], INVALID_SOCKET, -1, 30, DMC },
{ &dmc_csrs[0], &dmc_dev[0], Initialised, Idle, 0, 0, &dmc_line[0], &dmc_receive_queues[0], &dmc_transmit_queues[0], &dmc_stats[0], INVALID_SOCKET, 30, DMC },
{ &dmc_csrs[1], &dmc_dev[1], Initialised, Idle, 0, 0, &dmc_line[1], &dmc_receive_queues[1], &dmc_transmit_queues[1], &dmc_stats[1], INVALID_SOCKET, 30, DMC },
{ &dmc_csrs[2], &dmc_dev[2], Initialised, Idle, 0, 0, &dmc_line[2], &dmc_receive_queues[2], &dmc_transmit_queues[2], &dmc_stats[2], INVALID_SOCKET, 30, DMC },
{ &dmc_csrs[3], &dmc_dev[3], Initialised, Idle, 0, 0, &dmc_line[3], &dmc_receive_queues[3], &dmc_transmit_queues[3], &dmc_stats[3], INVALID_SOCKET, 30, DMC },
#ifdef DMP
{ &dmp_csrs[0], &dmp_dev[0], Initialised, Idle, 0, 0, &dmp_line[0], &dmp_receive_queues[0], &dmp_transmit_queues[0], &dmp_stats[0], INVALID_SOCKET, -1, 30, DMP }
#endif
@ -518,10 +518,6 @@ t_stat dmc_showpeer (FILE* st, UNIT* uptr, int32 val, void* desc)
{
fprintf(st, "peer=%s", controller->line->transmit_host);
}
else
{
fprintf(st, "peer Unspecified");
}
return SCPE_OK;
}
@ -553,7 +549,7 @@ t_stat dmc_showspeed (FILE* st, UNIT* uptr, int32 val, void* desc)
}
else
{
fprintf(st, "speed=unrestricted");
fprintf(st, "speed=0 (unrestricted)");
}
return SCPE_OK;
@ -693,7 +689,7 @@ t_stat dmc_setstats (UNIT* uptr, int32 val, char* cptr, void* desc)
t_stat dmc_showconnectpoll (FILE* st, UNIT* uptr, int32 val, void* desc)
{
CTLR *controller = dmc_get_controller_from_unit(uptr);
fprintf(st, "connect poll=%d", controller->connect_poll_interval);
fprintf(st, "connectpoll=%d", controller->connect_poll_interval);
return SCPE_OK;
}
@ -714,7 +710,7 @@ t_stat dmc_setconnectpoll (UNIT* uptr, int32 val, char* cptr, void* desc)
t_stat dmc_showlinemode (FILE* st, UNIT* uptr, int32 val, void* desc)
{
CTLR *controller = dmc_get_controller_from_unit(uptr);
fprintf(st, "line mode=%s", controller->line->isPrimary? "PRIMARY" : "SECONDARY");
fprintf(st, "linemode=%s", controller->line->isPrimary? "PRIMARY" : "SECONDARY");
return SCPE_OK;
}

1
VAX/vax610_defs.h
View file

@ -81,6 +81,7 @@
#define MT_IORESET 55 /* I/O Bus Reset */
#define MT_TBDATA 59 /* Translation Buffer Data */
#define MT_MBRK 60 /* microbreak */
#define MT_MAX 63 /* last valid IPR */
/* Memory */

1
VAX/vax630_defs.h
View file

@ -87,6 +87,7 @@
#define MT_IORESET 55 /* I/O Bus Reset */
#define MT_TBDATA 59 /* Translation Buffer Data */
#define MT_MBRK 60 /* microbreak */
#define MT_MAX 63 /* last valid IPR */
/* CPU */

1
VAX/vax730_defs.h
View file

@ -94,6 +94,7 @@
#define MT_SBITA 53 /* SBI timeout addr */
#define MT_SBIQC 54 /* SBI timeout clear */
#define MT_UBINIT 55 /* Unibus Init */
#define MT_MAX 63 /* last valid IPR */
/* Machine specific reserved operand tests */

12
VAX/vax730_sys.c
View file

@ -525,8 +525,16 @@ if ((strncmp (regptr, "/R5:", 4) == 0) ||
if (r != SCPE_OK)
return r;
}
else if (*regptr != 0)
return SCPE_ARG;
else
if (*regptr == '/') {
r5v = (int32) get_uint (regptr + 1, 16, LMASK, &r);
if (r != SCPE_OK)
return r;
}
else {
if (*regptr != 0)
return SCPE_ARG;
}
for (i = 0; boot_tab[i].name != NULL; i++) {
if (strcmp (dptr->name, boot_tab[i].name) == 0) {
R[0] = boot_tab[i].code;

12
VAX/vax750_cmi.c
View file

@ -609,8 +609,16 @@ if ((strncmp (regptr, "/R5:", 4) == 0) ||
if (r != SCPE_OK)
return r;
}
else if (*regptr != 0)
return SCPE_ARG;
else
if (*regptr == '/') {
r5v = (int32) get_uint (regptr + 1, 16, LMASK, &r);
if (r != SCPE_OK)
return r;
}
else {
if (*regptr != 0)
return SCPE_ARG;
}
for (i = 0; boot_tab[i].name != NULL; i++) {
if (strcmp (dptr->name, boot_tab[i].name) == 0) {
R[0] = boot_tab[i].code;

1
VAX/vax750_defs.h
View file

@ -115,6 +115,7 @@
#define MT_CAER 39 /* Cache error */
#define MT_ACCS 40 /* FPA control */
#define MT_IORESET 55 /* Unibus Init */
#define MT_MAX 63 /* last valid IPR */
/* Machine specific reserved operand tests */

1
VAX/vax780_defs.h
View file

@ -120,6 +120,7 @@
#define MT_SBITA 53 /* SBI timeout addr */
#define MT_SBIQC 54 /* SBI timeout clear */
#define MT_MBRK 60 /* microbreak */
#define MT_MAX 63 /* last valid IPR */
/* Machine specific reserved operand tests */

12
VAX/vax780_sbi.c
View file

@ -668,8 +668,16 @@ if ((strncmp (regptr, "/R5:", 4) == 0) ||
if (r != SCPE_OK)
return r;
}
else if (*regptr != 0)
return SCPE_ARG;
else
if (*regptr == '/') {
r5v = (int32) get_uint (regptr + 1, 16, LMASK, &r);
if (r != SCPE_OK)
return r;
}
else {
if (*regptr != 0)
return SCPE_ARG;
}
for (i = 0; boot_tab[i].name != NULL; i++) {
if (strcmp (dptr->name, boot_tab[i].name) == 0) {
R[0] = boot_tab[i].code;

730
VAX/vax860_abus.c Normal file
View file

@ -0,0 +1,730 @@
/* vax860_abus.c: VAX 8600 A-Bus
Copyright (c) 2011-2012, Matt Burke
This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name(s) of the author(s) shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the author(s).
abus bus controller
26-Dec-2012 MB First Version
*/
#include "vax_defs.h"
#ifdef DONT_USE_INTERNAL_ROM
#define BOOT_CODE_FILENAME "vmb.exe"
#else /* !DONT_USE_INTERNAL_ROM */
#include "vax_vmb_exe.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */
#endif /* DONT_USE_INTERNAL_ROM */
/* SBIA registers */
#define SBIER_TMO 0x00001000 /* timeout */
#define SBIER_STA 0x00000C00 /* timeout status (0) */
#define SBIER_CNF 0x00000100 /* error confirm */
#define SBIER_MULT 0x00000004 /* multiple errors */
#define SBIER_TMOW1C (SBIER_TMO|SBIER_STA|SBIER_CNF|SBIER_MULT)
/* PAMM */
#define PAMM_IOA0 0x18 /* I/O adapter 0 */
#define PAMM_IOA1 0x19 /* I/O adapter 1 */
#define PAMM_IOA2 0x1A /* I/O adapter 2 */
#define PAMM_IOA3 0x1B /* I/O adapter 3 */
#define PAMM_NXM 0x1F /* Non-existant address */
#define PAMACC_ADDR 0x3FF00000 /* PAMM address */
#define PAMACC_CODE 0x0000001F /* Configuration code */
#define PAMLOC_ADDR 0x3FF00000 /* PAMM address */
/* MBOX registers */
#define MSTAT1_V_CYC 26 /* MBOX cycle type */
#define MSTAT1_M_CYC 0xF
#define MSTAT1_CPRD 0xE /* CP read */
#define MSTAT2_NXM 0x00000008 /* CP NXM */
#define MERG_V_MME 8 /* Mem mgmt en */
#define MDCTL_RW 0x00006F0F /* MBOX data control */
/* EBOX registers */
#define EBCS_MFTL 0x00008000 /* MBOX fatal error */
#define EHMSTS_PROCA 0x00020000 /* Process abort */
#define EHSR_VMSE 0x00000020 /* VMS entered */
/* VAX 8600 boot device definitions */
struct boot_dev {
char *name;
int32 code;
int32 let;
};
uint32 nexus_req[NEXUS_HLVL]; /* nexus int req */
uint32 pamloc = 0;
uint32 cswp = 0;
uint32 ehsr = 0;
uint32 mdctl = 0;
int32 sys_model = 0;
char cpu_boot_cmd[CBUFSIZE] = { 0 }; /* boot command */
static struct boot_dev boot_tab[] = {
{ "RP", BOOT_MB, 0 },
{ "HK", BOOT_HK, 0 },
{ "RL", BOOT_RL, 0 },
{ "RQ", BOOT_UDA, 1 << 24 },
{ "RQB", BOOT_UDA, 1 << 24 },
{ "RQC", BOOT_UDA, 1 << 24 },
{ "RQD", BOOT_UDA, 1 << 24 },
{ "TQ", BOOT_TK, 1 << 24 },
{ "CS", BOOT_CS, 0 },
{ NULL }
};
extern int32 R[16];
extern int32 PSL;
extern int32 ASTLVL, SISR;
extern int32 mapen, pme, trpirq;
extern int32 in_ie;
extern int32 mchk_va, mchk_ref;
extern int32 crd_err, mem_err, hlt_pin;
extern int32 tmr_int, tti_int, tto_int, csi_int;
extern uint32 sbi_er;
extern jmp_buf save_env;
extern int32 p1;
extern int32 sim_switches;
extern DEVICE *sim_devices[];
extern FILE *sim_log;
extern CTAB *sim_vm_cmd;
extern int32 fault_PC; /* fault PC */
extern UNIT cpu_unit;
void uba_eval_int (void);
t_stat abus_reset (DEVICE *dptr);
t_stat vax860_boot (int32 flag, char *ptr);
t_stat vax860_boot_parse (int32 flag, char *ptr);
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
extern t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
extern t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 iccs_rd (void);
extern int32 nicr_rd (void);
extern int32 icr_rd (t_bool interp);
extern int32 todr_rd (void);
extern int32 rxcs_rd (void);
extern int32 rxdb_rd (void);
extern int32 txcs_rd (void);
extern int32 stxcs_rd (void);
extern int32 stxdb_rd (void);
extern void iccs_wr (int32 dat);
extern void nicr_wr (int32 dat);
extern void todr_wr (int32 dat);
extern void rxcs_wr (int32 dat);
extern void txcs_wr (int32 dat);
extern void txdb_wr (int32 dat);
extern void stxcs_wr (int32 data);
extern void stxdb_wr (int32 data);
extern void init_mbus_tab (void);
extern void init_ubus_tab (void);
extern void init_nexus_tab (void);
extern t_stat build_mbus_tab (DEVICE *dptr, DIB *dibp);
extern t_stat build_ubus_tab (DEVICE *dptr, DIB *dibp);
extern t_stat build_nexus_tab (DEVICE *dptr, DIB *dibp);
extern void sbi_set_tmo (int32 pa);
extern int32 sbia_rd (int32 pa, int32 lnt);
extern void sbia_wr (int32 pa, int32 val, int32 lnt);
extern t_stat sbi_rd (int32 pa, int32 *val, int32 lnt);
extern t_stat sbi_wr (int32 pa, int32 val, int32 lnt);
/* ABUS data structures
abus_dev A-Bus device descriptor
abus_unit A-Bus unit
abus_reg A-Bus register list
*/
UNIT abus_unit = { UDATA (NULL, 0, 0) };
REG abus_reg[] = {
{ NULL }
};
DEVICE abus_dev = {
"ABUS", &abus_unit, abus_reg, NULL,
1, 16, 16, 1, 16, 8,
NULL, NULL, &abus_reset,
NULL, NULL, NULL,
NULL, 0
};
/* Special boot command, overrides regular boot */
CTAB vax860_cmd[] = {
{ "BOOT", &vax860_boot, RU_BOOT,
"bo{ot} <device>{/R5:flg} boot device\n" },
{ NULL }
};
/* The VAX 8600 has three sources of interrupts
- internal device interrupts (CPU, console, clock)
- nexus interupts (e.g. MBA, UBA)
- external device interrupts (Unibus)
Internal devices vector to fixed SCB locations.
Nexus interrupts vector to an SCB location based on this
formula: SCB_NEXUS + ((IPL - 0x14) * 0x40) + (TR# * 0x4)
External device interrupts do not vector directly.
Instead, the interrupt handler for a given UBA IPL
reads a vector register that contains the Unibus vector
for that IPL.
/* Find highest priority vectorable interrupt */
int32 eval_int (void)
{
int32 ipl = PSL_GETIPL (PSL);
int32 i, t;
static const int32 sw_int_mask[IPL_SMAX] = {
0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */
0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */
0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */
0xE000, 0xC000, 0x8000 /* C - E */
};
if (hlt_pin) /* hlt pin int */
return IPL_HLTPIN;
if ((ipl < IPL_MEMERR) && mem_err) /* mem err int */
return IPL_MEMERR;
if ((ipl < IPL_CRDERR) && crd_err) /* crd err int */
return IPL_CRDERR;
if ((ipl < IPL_CLKINT) && tmr_int) /* clock int */
return IPL_CLKINT;
uba_eval_int (); /* update UBA */
for (i = IPL_HMAX; i >= IPL_HMIN; i--) { /* chk hwre int */
if (i <= ipl) /* at ipl? no int */
return 0;
if (nexus_req[i - IPL_HMIN]) /* req != 0? int */
return i;
}
if ((ipl < IPL_TTINT) && (tti_int || tto_int || csi_int)) /* console int */
return IPL_TTINT;
if (ipl >= IPL_SMAX) /* ipl >= sw max? */
return 0;
if ((t = SISR & sw_int_mask[ipl]) == 0)
return 0; /* eligible req */
for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */
if ((t >> i) & 1) /* req != 0? int */
return i;
}
return 0;
}
/* Return vector for highest priority hardware interrupt at IPL lvl */
int32 get_vector (int32 lvl)
{
int32 i, l;
if (lvl == IPL_MEMERR) { /* mem error? */
mem_err = 0;
return SCB_MEMERR;
}
if (lvl == IPL_CRDERR) { /* CRD error? */
crd_err = 0;
return SCB_CRDERR;
}
if (lvl == IPL_CLKINT) { /* clock? */
tmr_int = 0; /* clear req */
return SCB_INTTIM; /* return vector */
}
if (lvl > IPL_HMAX) { /* error req lvl? */
ABORT (STOP_UIPL); /* unknown intr */
}
if ((lvl <= IPL_HMAX) && (lvl >= IPL_HMIN)) { /* nexus? */
l = lvl - IPL_HMIN;
for (i = 0; nexus_req[l] && (i < NEXUS_NUM); i++) {
if ((nexus_req[l] >> i) & 1) {
nexus_req[l] = nexus_req[l] & ~(1u << i);
return SCB_NEXUS + (l << 6) + (i << 2); /* return vector */
}
}
}
if (lvl == IPL_TTINT) { /* console? */
if (tti_int) { /* input? */
tti_int = 0; /* clear req */
return SCB_TTI; /* return vector */
}
if (tto_int) { /* output? */
tto_int = 0; /* clear req */
return SCB_TTO; /* return vector */
}
if (csi_int) { /* console storage? */
csi_int = 0; /* clear req */
return SCB_CSI; /* return vector */
}
}
return 0;
}
/* Used by CPU */
void rom_wr_B (int32 pa, int32 val)
{
return;
}
/* Read 8600 specific IPR's */
int32 ReadIPR (int32 rg)
{
int32 val;
switch (rg) {
case MT_ICCS: /* ICCS */
val = iccs_rd ();
break;
case MT_NICR: /* NICR */
val = nicr_rd ();
break;
case MT_ICR: /* ICR */
val = icr_rd (FALSE);
break;
case MT_TODR: /* TODR */
val = todr_rd ();
break;
case MT_ACCS: /* ACCS (not impl) */
val = 0;
break;
case MT_RXCS: /* RXCS */
val = rxcs_rd ();
break;
case MT_RXDB: /* RXDB */
val = rxdb_rd ();
break;
case MT_TXCS: /* TXCS */
val = txcs_rd ();
break;
case MT_SID: /* SID */
if (sys_model)
val = VAX860_SID | VAX865_TYP | VAX860_PLANT | VAX860_SN;
else
val = VAX860_SID | VAX860_TYP | VAX860_PLANT | VAX860_SN;
break;
case MT_PAMACC: /* PAMACC */
if (ADDR_IS_REG (pamloc))
val = PAMM_IOA0; /* SBIA */
else if (ADDR_IS_MEM (pamloc)) {
if (MEMSIZE < MAXMEMSIZE)
val = (pamloc >> 23); /* 4MB Boards */
else
val = (pamloc >> 25); /* 16MB Boards */
}
else val = PAMM_NXM; /* NXM */
val = val | (pamloc & PAMACC_ADDR);
break;
case MT_PAMLOC: /* PAMLOC */
val = pamloc & PAMLOC_ADDR;
break;
case MT_MDCTL: /* MDCTL */
val = mdctl & MDCTL_RW;
case MT_EHSR: /* EHSR */
val = ehsr & EHSR_VMSE;
break;
case MT_CSWP: /* CSWP */
val = cswp & 0xF;
break;
case MT_MERG: /* MERG */
val = 0;
break;
case MT_STXCS: /* STXCS */
val = stxcs_rd ();
break;
case MT_STXDB: /* STXDB */
val = stxdb_rd ();
break;
default:
RSVD_OPND_FAULT;
}
return val;
}
/* Write 8600 specific IPR's */
void WriteIPR (int32 rg, int32 val)
{
switch (rg) {
case MT_ICCS: /* ICCS */
iccs_wr (val);
break;
case MT_NICR: /* NICR */
nicr_wr (val);
break;
case MT_TODR: /* TODR */
todr_wr (val);
break;
case MT_ACCS: /* ACCS (not impl) */
break;
case MT_RXCS: /* RXCS */
rxcs_wr (val);
break;
case MT_TXCS: /* TXCS */
txcs_wr (val);
break;
case MT_TXDB: /* TXDB */
txdb_wr (val);
break;
case MT_PAMACC: /* PAMACC (not impl) */
break;
case MT_PAMLOC: /* PAMLOC */
pamloc = val & PAMLOC_ADDR;
break;
case MT_MDCTL: /* MDCTL */
mdctl = val & MDCTL_RW;
break;
case MT_EHSR: /* EHSR */
ehsr = val & EHSR_VMSE;
break;
case MT_CSWP: /* CSWP */
cswp = val & 0xF;
break;
case MT_MERG: /* MERG (not impl) */
break;
case MT_CRBT: /* CRBT (not impl) */
break;
case MT_STXCS: /* STXCS */
stxcs_wr (val);
break;
case MT_STXDB: /* STXDB */
stxdb_wr (val);
break;
default:
RSVD_OPND_FAULT;
}
return;
}
/* ReadReg - read register space
Inputs:
pa = physical address
lnt = length (BWLQ)
Output:
longword of data
*/
int32 ReadReg (int32 pa, int32 lnt)
{
int32 val;
if (ADDR_IS_SBIA (pa)) return sbia_rd (pa, lnt); /* SBI adapter space? */
if (ADDR_IS_REG (pa)) { /* reg space? */
if (sbi_rd (pa, &val, lnt) == SCPE_OK)
return val;
}
MACH_CHECK (MCHK_RD_F); /* machine check */
return 0;
}
/* WriteReg - write register space
Inputs:
pa = physical address
val = data to write, right justified in 32b longword
lnt = length (BWLQ)
Outputs:
none
*/
void WriteReg (int32 pa, int32 val, int32 lnt)
{
if (ADDR_IS_SBIA (pa)) { /* SBI adapter space? */
sbia_wr (pa, val, lnt);
SET_IRQL;
return;
}
if (ADDR_IS_REG (pa)) { /* reg space? */
if (sbi_wr (pa, val, lnt) == SCPE_OK)
return;
}
mem_err = 1; /* interrupt */
eval_int ();
return;
}
/* Machine check */
int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta)
{
int32 acc;
int32 mstat1, mstat2, mear, ebcs, merg, ehmsts;
mstat1 = (MSTAT1_CPRD << MSTAT1_V_CYC); /* MBOX Status 1 */
mstat2 = MSTAT2_NXM; /* MBOX Status 2 */
mear = mchk_va; /* Memory error address */
merg = (mchk_ref << MERG_V_MME); /* MBOX error generation word */
ebcs = EBCS_MFTL; /* EBOX control/status */
ehmsts = EHMSTS_PROCA; /* Error handling microcode status */
cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take exception */
acc = ACC_MASK (KERN); /* in kernel mode */
in_ie = 1;
SP = SP - 92; /* push 25 words */
Write (SP, 88, L_LONG, WA); /* # bytes */
Write (SP + 4, ehmsts, L_LONG, WA); /* EHM.STS */
Write (SP + 8, 0, L_LONG, WA); /* EVMQSAV */
Write (SP + 12, ebcs, L_LONG, WA); /* EBCS */
Write (SP + 16, 0, L_LONG, WA); /* EDPSR */
Write (SP + 20, 0, L_LONG, WA); /* CSLINT */
Write (SP + 24, 0, L_LONG, WA); /* IBESR */
Write (SP + 28, 0, L_LONG, WA); /* EBXWD1 */
Write (SP + 32, 0, L_LONG, WA); /* EBXWD2 */
Write (SP + 36, 0, L_LONG, WA); /* IVASAV */
Write (SP + 40, 0, L_LONG, WA); /* VIBASAV */
Write (SP + 44, 0, L_LONG, WA); /* ESASAV */
Write (SP + 48, 0, L_LONG, WA); /* ISASAV */
Write (SP + 52, 0, L_LONG, WA); /* CPC */
Write (SP + 56, mstat1, L_LONG, WA); /* MSTAT1 */
Write (SP + 60, mstat2, L_LONG, WA); /* MSTAT2 */
Write (SP + 64, 0, L_LONG, WA); /* MDECC */
Write (SP + 68, merg, L_LONG, WA); /* MERG */
Write (SP + 72, 0, L_LONG, WA); /* CSHCTL */
Write (SP + 76, mear, L_LONG, WA); /* MEAR */
Write (SP + 80, 0, L_LONG, WA); /* MEDR */
Write (SP + 84, 0, L_LONG, WA); /* FBXERR */
Write (SP + 88, 0, L_LONG, WA); /* CSES */
in_ie = 0;
sbi_er = sbi_er & ~SBIER_TMOW1C; /* clr SBIER<tmo> etc */
ehsr = ehsr | EHSR_VMSE; /* VMS entered */
return cc;
}
/* Console entry */
int32 con_halt (int32 code, int32 cc)
{
ABORT (STOP_HALT);
return cc;
}
/* Special boot command - linked into SCP by initial reset
Syntax: BOOT <device>{/R5:val}
Sets up R0-R5, calls SCP boot processor with effective BOOT CPU
*/
t_stat vax860_boot (int32 flag, char *ptr)
{
t_stat r;
r = vax860_boot_parse (flag, ptr); /* parse the boot cmd */
if (r != SCPE_OK) /* error? */
return r;
strncpy (cpu_boot_cmd, ptr, CBUFSIZE); /* save for reboot */
return run_cmd (flag, "CPU");
}
/* Parse boot command, set up registers - also used on reset */
t_stat vax860_boot_parse (int32 flag, char *ptr)
{
char gbuf[CBUFSIZE];
char *slptr, *regptr;
int32 i, r5v, unitno;
DEVICE *dptr;
UNIT *uptr;
DIB *dibp;
uint32 ba;
t_stat r;
regptr = get_glyph (ptr, gbuf, 0); /* get glyph */
if (slptr = strchr (gbuf, '/')) { /* found slash? */
regptr = strchr (ptr, '/'); /* locate orig */
*slptr = 0; /* zero in string */
}
dptr = find_unit (gbuf, &uptr); /* find device */
if ((dptr == NULL) || (uptr == NULL))
return SCPE_ARG;
dibp = (DIB *) dptr->ctxt; /* get DIB */
if (dibp == NULL)
ba = 0;
else
ba = dibp->ba;
unitno = (int32) (uptr - dptr->units);
r5v = 0;
if ((strncmp (regptr, "/R5:", 4) == 0) ||
(strncmp (regptr, "/R5=", 4) == 0) ||
(strncmp (regptr, "/r5:", 4) == 0) ||
(strncmp (regptr, "/r5=", 4) == 0)) {
r5v = (int32) get_uint (regptr + 4, 16, LMASK, &r);
if (r != SCPE_OK)
return r;
}
else
if (*regptr == '/') {
r5v = (int32) get_uint (regptr + 1, 16, LMASK, &r);
if (r != SCPE_OK)
return r;
}
else {
if (*regptr != 0)
return SCPE_ARG;
}
for (i = 0; boot_tab[i].name != NULL; i++) {
if (strcmp (dptr->name, boot_tab[i].name) == 0) {
R[0] = boot_tab[i].code;
if (dptr->flags & DEV_MBUS) {
R[1] = ba + TR_MBA0;
R[2] = unitno;
}
else {
R[1] = TR_UBA;
R[2] = boot_tab[i].let | (ba & UBADDRMASK);
}
R[3] = unitno;
R[4] = 0;
R[5] = r5v;
return SCPE_OK;
}
}
return SCPE_NOFNC;
}
/* Bootstrap - finish up bootstrap process */
t_stat cpu_boot (int32 unitno, DEVICE *dptr)
{
t_stat r;
r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, FALSE, 0x200);
if (r != SCPE_OK)
return r;
SP = PC = 512;
return SCPE_OK;
}
/* A-Bus reset */
t_stat abus_reset (DEVICE *dptr)
{
sim_vm_cmd = vax860_cmd;
return SCPE_OK;
}
/* Build dib_tab from device list */
t_stat build_dib_tab (void)
{
uint32 i;
DEVICE *dptr;
DIB *dibp;
t_stat r;
init_nexus_tab ();
init_ubus_tab ();
init_mbus_tab ();
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
dibp = (DIB *) dptr->ctxt; /* get DIB */
if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */
if (dptr->flags & DEV_NEXUS) { /* Nexus? */
if (r = build_nexus_tab (dptr, dibp)) /* add to dispatch table */
return r;
}
else if (dptr->flags & DEV_MBUS) { /* Massbus? */
if (r = build_mbus_tab (dptr, dibp))
return r;
}
else { /* no, Unibus device */
if (r = build_ubus_tab (dptr, dibp)) /* add to dispatch tab */
return r;
} /* end else */
} /* end if enabled */
} /* end for */
return SCPE_OK;
}
t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc)
{
if (cptr == NULL) return SCPE_ARG;
if (strcmp(cptr, "8600") == 0)
sys_model = 0;
else if (strcmp(cptr, "8650") == 0)
sys_model = 1;
else
return SCPE_ARG;
return SCPE_OK;
}
t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc)
{
fprintf (st, "model=%s", (sys_model ? "8650" : "8600"));
return SCPE_OK;
}

522
VAX/vax860_defs.h Normal file
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/* vax860_defs.h: VAX 8600 model-specific definitions file
Copyright (c) 2011-2012, Matt Burke
This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name(s) of the author(s) shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the author(s).
26-Dec-2012 MB First Version
This file covers the VAX 8600, the fourth VAX.
System memory map
0000 0000 - 1FFF FFFF main memory
2000 0000 - 2001 FFFF SBI0 adapter space
2002 0000 - 200F FFFF reserved
2008 0000 - 2008 00BF SBI0 registers
2008 00C0 - 200F FFFF reserved
2010 0000 - 2013 FFFF Unibus address space, Unibus 0
2014 0000 - 2017 FFFF Unibus address space, Unibus 1
2018 0000 - 201B FFFF Unibus address space, Unibus 2
201C 0000 - 201F FFFF Unibus address space, Unibus 3
2020 0000 - 21FF FFFF reserved
2200 0000 - 2201 FFFF SBI1 adapter space
2202 0000 - 220F FFFF reserved
2208 0000 - 2208 00BF SBI1 registers
2208 00C0 - 220F FFFF reserved
2210 0000 - 2213 FFFF Unibus address space, Unibus 4
2214 0000 - 2217 FFFF Unibus address space, Unibus 5
2218 0000 - 221B FFFF Unibus address space, Unibus 6
221C 0000 - 221F FFFF Unibus address space, Unibus 7
2220 0000 - 23FF FFFF reserved
2400 0000 - 2401 FFFF SBI2 adapter space
2402 0000 - 240F FFFF reserved
2408 0000 - 2408 00BF SBI2 registers
2408 00C0 - 240F FFFF reserved
2410 0000 - 2413 FFFF Unibus address space, Unibus 8
2414 0000 - 2417 FFFF Unibus address space, Unibus 9
2418 0000 - 241B FFFF Unibus address space, Unibus 10
241C 0000 - 241F FFFF Unibus address space, Unibus 11
2420 0000 - 25FF FFFF reserved
2600 0000 - 2601 FFFF SBI3 adapter space
2602 0000 - 260F FFFF reserved
2608 0000 - 2608 00BF SBI3 registers
2608 00C0 - 260F FFFF reserved
2610 0000 - 2613 FFFF Unibus address space, Unibus 12
2614 0000 - 2617 FFFF Unibus address space, Unibus 13
2618 0000 - 261B FFFF Unibus address space, Unibus 14
261C 0000 - 261F FFFF Unibus address space, Unibus 15
2620 0000 - 3FFF FFFF reserved
*/
#ifndef FULL_VAX
#define FULL_VAX 1
#endif
#ifndef _VAX_860_DEFS_H_
#define _VAX_860_DEFS_H_ 1
/* Microcode constructs */
#define VAX860_SID (4 << 24) /* system ID */
#define VAX860_TYP (0 << 23) /* sys type: 8600 */
#define VAX865_TYP (1 << 23) /* sys type: 8650 */
#define VAX860_ECO (7 << 19) /* ucode revision */
#define VAX860_PLANT (0 << 12) /* plant (Salem NH) */
#define VAX860_SN (1234)
#define CON_HLTPIN 0x0200 /* external CPU halt */
#define CON_HLTINS 0x0600 /* HALT instruction */
#define MCHK_RD_F 0x00 /* read fault */
#define MCHK_RD_A 0xF4 /* read abort */
#define MCHK_IBUF 0x0D /* read istream */
#define VER_UCODE 0x1 /* Microcode version */
/* Interrupts */
#define IPL_HMAX 0x17 /* highest hwre level */
#define IPL_HMIN 0x14 /* lowest hwre level */
#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */
#define IPL_SMAX 0xF /* highest swre level */
/* SBI Nexus constants */
#define NEXUS_NUM 16 /* number of nexus */
#define MCTL_NUM 2 /* number of mem ctrl */
#define MBA_NUM 2 /* number of MBA's */
#define TR_MCTL0 1 /* nexus assignments */
#define TR_MCTL1 2
#define TR_UBA 3
#define TR_MBA0 8
#define TR_MBA1 9
#define TR_CI 14
#define NEXUS_HLVL (IPL_HMAX - IPL_HMIN + 1)
#define SCB_NEXUS 0x100 /* nexus intr base */
#define SBI_FAULTS 0xFC000000 /* SBI fault flags */
/* Internal I/O interrupts - relative except for clock and console */
#define IPL_CLKINT 0x18 /* clock IPL */
#define IPL_TTINT 0x14 /* console IPL */
#define IPL_MCTL0 (0x15 - IPL_HMIN)
#define IPL_MCTL1 (0x15 - IPL_HMIN)
#define IPL_UBA (0x15 - IPL_HMIN)
#define IPL_MBA0 (0x15 - IPL_HMIN)
#define IPL_MBA1 (0x15 - IPL_HMIN)
#define IPL_CI (0x15 - IPL_HMIN)
/* Nexus interrupt macros */
#define SET_NEXUS_INT(dv) nexus_req[IPL_##dv] |= (1 << TR_##dv)
#define CLR_NEXUS_INT(dv) nexus_req[IPL_##dv] &= ~(1 << TR_##dv)
/* Machine specific IPRs */
#define MT_ACCS 40 /* FPA control */
#define MT_PAMACC 64
#define MT_PAMLOC 65
#define MT_CSWP 66
#define MT_MDECC 67
#define MT_MENA 68
#define MT_MDCTL 69
#define MT_MCCTL 70
#define MT_MERG 71
#define MT_CRBT 72 /* Console reboot */
#define MT_DFI 73
#define MT_EHSR 74
#define MT_STXCS 76
#define MT_STXDB 77
#define MT_ESPA 78
#define MT_ESPD 79
#define MT_MAX MT_ESPD /* last valid IPR */
/* Machine specific reserved operand tests */
/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */
#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT
/* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */
#define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \
((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT
#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0xC0000003) != 0) RSVD_OPND_FAULT
/* 780 microcode patch 78 - only test xCBB<1:0> = 0 */
#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
/* CPU */
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL", \
&cpu_set_model, &cpu_show_model },
/* Memory */
#define MAXMEMWIDTH 25 /* max mem, 4MB boards */
#define MAXMEMSIZE (1 << MAXMEMWIDTH)
#define MAXMEMWIDTH_X 27 /* max mem, 16MB boards */
#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X)
#define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */
#define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size }
/* Unibus I/O registers */
#define UBADDRWIDTH 18 /* Unibus addr width */
#define UBADDRSIZE (1u << UBADDRWIDTH) /* Unibus addr length */
#define UBADDRMASK (UBADDRSIZE - 1) /* Unibus addr mask */
#define IOPAGEAWIDTH 13 /* IO addr width */
#define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */
#define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */
#define UBADDRBASE 0x20100000 /* Unibus addr base */
#define IOPAGEBASE 0x2013E000 /* IO page base */
#define ADDR_IS_IO(x) ((((uint32) (x)) >= UBADDRBASE) && \
(((uint32) (x)) < (UBADDRBASE + UBADDRSIZE)))
#define ADDR_IS_IOP(x) (((uint32) (x)) >= IOPAGEBASE)
/* Nexus register space */
#define REGAWIDTH 17 /* REG addr width */
#define REG_V_NEXUS 13 /* nexus number */
#define REG_M_NEXUS 0xF
#define REG_V_OFS 2 /* register number */
#define REG_M_OFS 0x7FF
#define REGSIZE (1u << REGAWIDTH) /* REG length */
#define REGBASE 0x20000000 /* REG addr base */
#define ADDR_IS_REG(x) ((((uint32) (x)) >= REGBASE) && \
(((uint32) (x)) < (REGBASE + REGSIZE)))
#define NEXUS_GETNEX(x) (((x) >> REG_V_NEXUS) & REG_M_NEXUS)
#define NEXUS_GETOFS(x) (((x) >> REG_V_OFS) & REG_M_OFS)
/* SBI adapter space */
#define SBIAWIDTH 19
#define SBIABASE 0x20080000
#define SBIASIZE (1u << SBIAWIDTH)
#define ADDR_IS_SBIA(x) ((((uint32) (x)) >= SBIABASE) && \
(((uint32) (x)) < (SBIABASE + SBIASIZE)))
/* ROM address space in memory controllers */
#define ROMAWIDTH 12 /* ROM addr width */
#define ROMSIZE (1u << ROMAWIDTH) /* ROM size */
#define ROM0BASE (REGBASE + (TR_MCTL0 << REG_V_NEXUS) + 0x1000)
#define ROM1BASE (REGBASE + (TR_MCTL1 << REG_V_NEXUS) + 0x1000)
#define ADDR_IS_ROM0(x) ((((uint32) (x)) >= ROM0BASE) && \
(((uint32) (x)) < (ROM0BASE + ROMSIZE)))
#define ADDR_IS_ROM1(x) ((((uint32) (x)) >= ROM1BASE) && \
(((uint32) (x)) < (ROM1BASE + ROMSIZE)))
#define ADDR_IS_ROM(x) (ADDR_IS_ROM0 (x) || ADDR_IS_ROM1 (x))
/* Other address spaces */
#define ADDR_IS_CDG(x) (0)
#define ADDR_IS_NVR(x) (0)
/* Unibus I/O modes */
#define READ 0 /* PDP-11 compatibility */
#define WRITE (L_WORD)
#define WRITEB (L_BYTE)
/* Common CSI flags */
#define CSR_V_GO 0 /* go */
#define CSR_V_IE 6 /* interrupt enable */
#define CSR_V_DONE 7 /* done */
#define CSR_V_BUSY 11 /* busy */
#define CSR_V_ERR 15 /* error */
#define CSR_GO (1u << CSR_V_GO)
#define CSR_IE (1u << CSR_V_IE)
#define CSR_DONE (1u << CSR_V_DONE)
#define CSR_BUSY (1u << CSR_V_BUSY)
#define CSR_ERR (1u << CSR_V_ERR)
/* Timers */
#define TMR_CLK 0 /* 100Hz clock */
/* I/O system definitions */
#define DZ_MUXES 4 /* max # of DZV muxes */
#define DZ_LINES 8 /* lines per DZV mux */
#define VH_MUXES 4 /* max # of DHU muxes */
#define DLX_LINES 16 /* max # of KL11/DL11's */
#define DCX_LINES 16 /* max # of DC11's */
#define MT_MAXFR (1 << 16) /* magtape max rec */
#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */
#define DEV_V_MBUS (DEV_V_UF + 1) /* Massbus */
#define DEV_V_NEXUS (DEV_V_UF + 2) /* Nexus */
#define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */
#define DEV_V_FFUF (DEV_V_UF + 4) /* first free flag */
#define DEV_UBUS (1u << DEV_V_UBUS)
#define DEV_MBUS (1u << DEV_V_MBUS)
#define DEV_NEXUS (1u << DEV_V_NEXUS)
#define DEV_FLTA (1u << DEV_V_FLTA)
#define DEV_QBUS (0)
#define DEV_Q18 (0)
#define UNIBUS TRUE /* Unibus only */
#define DEV_RDX 16 /* default device radix */
/* Device information block
For Massbus devices,
ba = Massbus number
lnt = Massbus ctrl type
ack[0] = abort routine
For Nexus devices,
ba = Nexus number
lnt = number of consecutive nexi */
#define VEC_DEVMAX 4 /* max device vec */
typedef struct {
uint32 ba; /* base addr */
uint32 lnt; /* length */
t_stat (*rd)(int32 *dat, int32 ad, int32 md);
t_stat (*wr)(int32 dat, int32 ad, int32 md);
int32 vnum; /* vectors: number */
int32 vloc; /* locator */
int32 vec; /* value */
int32 (*ack[VEC_DEVMAX])(void); /* ack routine */
} DIB;
/* Unibus I/O page layout - XUB,RQB,RQC,RQD float based on number of DZ's
Massbus devices (RP, TU) do not appear in the Unibus IO page */
#define IOBA_FLOAT (0) /* Assigned by Auto Configure */
#define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */
#define IOLN_DZ 010
#define IOBA_XUB (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2)))
#define IOLN_XUB 010
#define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2)))
#define IOLN_RQB 004
#define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
#define IOLN_RQC 004
#define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
#define IOLN_RQD 004
#define IOBA_RQ (IOPAGEBASE + 012150) /* UDA50 */
#define IOLN_RQ 004
#define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */
#define IOLN_TS 004
#define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */
#define IOLN_RL 012
#define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */
#define IOLN_XQ 020
#define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */
#define IOLN_XQB 020
#define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */
#define IOLN_TQ 004
#define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */
#define IOLN_XU 010
#define IOBA_CR (IOPAGEBASE + 017160) /* CD/CR/CM */
#define IOLN_CR 010
#define IOBA_RX (IOPAGEBASE + 017170) /* RX11 */
#define IOLN_RX 004
#define IOBA_RY (IOPAGEBASE + 017170) /* RXV21 */
#define IOLN_RY 004
#define IOBA_QDSS (IOPAGEBASE + 017400) /* QDSS */
#define IOLN_QDSS 002
#define IOBA_HK (IOPAGEBASE + 017440) /* RK611 */
#define IOLN_HK 040
#define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */
#define IOLN_LPT 004
#define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */
#define IOLN_PTR 004
#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */
#define IOLN_PTP 004
/* Interrupt assignments; within each level, priority is right to left */
#define INT_V_DZRX 0 /* BR5 */
#define INT_V_DZTX 1
#define INT_V_HK 2
#define INT_V_RL 3
#define INT_V_RQ 4
#define INT_V_TQ 5
#define INT_V_TS 6
#define INT_V_RY 7
#define INT_V_XU 8
#define INT_V_DMCRX 9
#define INT_V_DMCTX 10
#define INT_V_LPT 0 /* BR4 */
#define INT_V_PTR 1
#define INT_V_PTP 2
#define INT_V_CR 3
#define INT_V_VHRX 4
#define INT_V_VHTX 5
#define INT_DZRX (1u << INT_V_DZRX)
#define INT_DZTX (1u << INT_V_DZTX)
#define INT_HK (1u << INT_V_HK)
#define INT_RL (1u << INT_V_RL)
#define INT_RQ (1u << INT_V_RQ)
#define INT_TQ (1u << INT_V_TQ)
#define INT_TS (1u << INT_V_TS)
#define INT_RY (1u << INT_V_RY)
#define INT_XU (1u << INT_V_XU)
#define INT_LPT (1u << INT_V_LPT)
#define INT_VHRX (1u << INT_V_VHRX)
#define INT_VHTX (1u << INT_V_VHTX)
#define INT_PTR (1u << INT_V_PTR)
#define INT_PTP (1u << INT_V_PTP)
#define INT_CR (1u << INT_V_CR)
#define INT_DMCRX (1u << INT_V_DMCRX)
#define INT_DMCTX (1u << INT_V_DMCTX)
#define IPL_DZRX (0x15 - IPL_HMIN)
#define IPL_DZTX (0x15 - IPL_HMIN)
#define IPL_HK (0x15 - IPL_HMIN)
#define IPL_RL (0x15 - IPL_HMIN)
#define IPL_RQ (0x15 - IPL_HMIN)
#define IPL_TQ (0x15 - IPL_HMIN)
#define IPL_TS (0x15 - IPL_HMIN)
#define IPL_RY (0x15 - IPL_HMIN)
#define IPL_XU (0x15 - IPL_HMIN)
#define IPL_LPT (0x14 - IPL_HMIN)
#define IPL_PTR (0x14 - IPL_HMIN)
#define IPL_PTP (0x14 - IPL_HMIN)
#define IPL_CR (0x14 - IPL_HMIN)
#define IPL_VHRX (0x14 - IPL_HMIN)
#define IPL_VHTX (0x14 - IPL_HMIN)
#define IPL_DMCRX (0x15 - IPL_HMIN)
#define IPL_DMCTX (0x15 - IPL_HMIN)
/* Device vectors */
#define VEC_FLOAT (0) /* Assigned by Auto Configure */
#define VEC_QBUS 0
#define VEC_Q 0000
#define VEC_PTR 0070
#define VEC_PTP 0074
#define VEC_XQ 0120
#define VEC_XU 0120
#define VEC_RQ 0154
#define VEC_RL 0160
#define VEC_LPT 0200
#define VEC_HK 0210
#define VEC_TS 0224
#define VEC_CR 0230
#define VEC_TQ 0260
#define VEC_RX 0264
#define VEC_RY 0264
#define VEC_DZRX 0300
#define VEC_DZTX 0304
/* Interrupt macros */
#define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv)
#define NVCL(dv) ((IPL_##dv * 32) + TR_##dv)
#define IREQ(dv) int_req[IPL_##dv]
#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
/* Logging */
#define LOG_CPU_I 0x1 /* intexc */
#define LOG_CPU_R 0x2 /* REI */
#define LOG_CPU_P 0x4 /* context */
/* Massbus definitions */
#define MBA_RP (TR_MBA0 - TR_MBA0) /* MBA for RP */
#define MBA_TU (TR_MBA1 - TR_MBA0) /* MBA for TU */
#define MBA_RMASK 0x1F /* max 32 reg */
#define MBE_NXD 1 /* nx drive */
#define MBE_NXR 2 /* nx reg */
#define MBE_GOE 3 /* err on GO */
/* Boot definitions */
#define BOOT_MB 0 /* device codes */
#define BOOT_HK 1 /* for VMB */
#define BOOT_RL 2
#define BOOT_UDA 17
#define BOOT_TK 18
#define BOOT_CS 64
/* Function prototypes for virtual memory interface */
int32 Read (uint32 va, int32 lnt, int32 acc);
void Write (uint32 va, int32 val, int32 lnt, int32 acc);
/* Function prototypes for physical memory interface (inlined) */
SIM_INLINE int32 ReadB (uint32 pa);
SIM_INLINE int32 ReadW (uint32 pa);
SIM_INLINE int32 ReadL (uint32 pa);
SIM_INLINE int32 ReadLP (uint32 pa);
SIM_INLINE void WriteB (uint32 pa, int32 val);
SIM_INLINE void WriteW (uint32 pa, int32 val);
SIM_INLINE void WriteL (uint32 pa, int32 val);
void WriteLP (uint32 pa, int32 val);
/* Function prototypes for I/O */
int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);
int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);
int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf);
int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf);
int32 mba_rdbufW (uint32 mbus, int32 bc, uint16 *buf);
int32 mba_wrbufW (uint32 mbus, int32 bc, uint16 *buf);
int32 mba_chbufW (uint32 mbus, int32 bc, uint16 *buf);
int32 mba_get_bc (uint32 mbus);
void mba_upd_ata (uint32 mbus, uint32 val);
void mba_set_exc (uint32 mbus);
void mba_set_don (uint32 mbus);
void mba_set_enbdis (uint32 mbus, t_bool dis);
t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc);
void sbi_set_errcnf (void);
int32 clk_cosched (int32 wait);
t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc);
#include "pdp11_io_lib.h"
#endif

359
VAX/vax860_sbia.c Normal file
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@ -0,0 +1,359 @@
/* vax860_sbia.c: VAX 8600 SBIA
Copyright (c) 2011-2012, Matt Burke
This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name(s) of the author(s) shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the author(s).
sbia SBI adapter
26-Dec-2012 MB First Version
*/
#include "vax_defs.h"
/* SBIA registers */
#define SBICSR_MIE 0x80000000 /* master int en */
#define SBICSR_SCOEN 0x40000000 /* SBI cycles out enable */
#define SBICSR_SCIEN 0x20000000 /* SBI cycles in enable */
#define SBICSR_WR (SBICSR_MIE | SBICSR_SCOEN | SBICSR_SCIEN)
#define SBIFS_RD (0x031F0000|SBI_FAULTS) /* SBI faults */
#define SBIFS_WR 0x03140000
#define SBIFS_W1C 0x00080000
#define SBISC_RD 0xFFFF0000 /* SBI silo comp */
#define SBISC_WR 0x7FFF0000
#define SBISC_LOCK 0x80000000 /* lock */
#define SBIMT_RD 0xFFFFFF00 /* SBI maint */
#define SBIMT_WR 0xFFFFF900
#define SBIER_CRDIE 0x00008000 /* SBI error, CRD IE */
#define SBIER_CRD 0x00004000 /* CRD */
#define SBIER_RDS 0x00002000 /* RDS */
#define SBIER_TMO 0x00001000 /* timeout */
#define SBIER_STA 0x00000C00 /* timeout status (0) */
#define SBIER_CNF 0x00000100 /* error confirm */
#define SBIER_IBRDS 0x00000080
#define SBIER_IBTMO 0x00000040
#define SBIER_IBSTA 0x00000030
#define SBIER_IBCNF 0x00000008
#define SBIER_MULT 0x00000004 /* multiple errors */
#define SBIER_FREE 0x00000002 /* SBI free */
#define SBIER_RD 0x0000FDFE
#define SBIER_WR 0x00008000
#define SBIER_W1C 0x000070C0
#define SBIER_TMOW1C (SBIER_TMO|SBIER_STA|SBIER_CNF|SBIER_MULT)
#define SBIER_IBTW1C (SBIER_IBTMO|SBIER_STA|SBIER_IBCNF)
#define SBITMO_V_MODE 30 /* mode */
#define SBITMO_VIRT 0x20000000 /* physical */
#define SBIQC_MBZ 0xC0000007 /* MBZ */
uint32 nexus_req[NEXUS_HLVL]; /* nexus int req */
uint32 sbi_fs = 0; /* SBI fault status */
uint32 sbi_sc = 0; /* SBI silo comparator */
uint32 sbi_mt = 0; /* SBI maintenance */
uint32 sbi_er = 0; /* SBI error status */
uint32 sbi_tmo = 0; /* SBI timeout addr */
uint32 sbi_csr = 0; /* SBI control/status */
extern int32 R[16];
extern int32 PSL;
extern int32 ASTLVL, SISR;
extern jmp_buf save_env;
extern int32 trpirq;
extern int32 p1;
extern int32 mchk_ref;
extern int32 crd_err;
extern int32 sim_switches;
extern DEVICE *sim_devices[];
extern FILE *sim_log;
extern int32 fault_PC; /* fault PC */
extern UNIT cpu_unit;
t_stat sbia_reset (DEVICE *dptr);
void sbi_set_tmo (int32 pa);
t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 eval_int (void);
/* SBIA data structures
sbia_dev SBIA device descriptor
sbia_unit SBIA unit
sbia_reg SBIA register list
*/
UNIT sbia_unit = { UDATA (NULL, 0, 0) };
REG sbia_reg[] = {
{ HRDATA (NREQ14, nexus_req[0], 16) },
{ HRDATA (NREQ15, nexus_req[1], 16) },
{ HRDATA (NREQ16, nexus_req[2], 16) },
{ HRDATA (NREQ17, nexus_req[3], 16) },
{ HRDATA (SBIFS, sbi_fs, 32) },
{ HRDATA (SBISC, sbi_sc, 32) },
{ HRDATA (SBIMT, sbi_mt, 32) },
{ HRDATA (SBIER, sbi_er, 32) },
{ HRDATA (SBITMO, sbi_tmo, 32) },
{ HRDATA (SBICSR, sbi_csr, 32) },
{ NULL }
};
DEVICE sbia_dev = {
"SBIA", &sbia_unit, sbia_reg, NULL,
1, 16, 16, 1, 16, 8,
NULL, NULL, &sbia_reset,
NULL, NULL, NULL,
NULL, 0
};
int32 sbia_rd (int32 pa, int32 lnt)
{
int32 rg = (pa >> 2) & 0x1F;
switch (rg) {
case 0: /* SBICNF */
return 0x00400010; /* 8MB + SBIA Abus code */
case 1: /* SBICSR */
return sbi_csr;
case 2: /* SBIES (not impl) */
case 3: /* SBIDCR (not impl) */
case 4: /* DMAI CMD (not impl) */
case 5: /* DMAI ID (not impl) */
case 6: /* DMAA CMD (not impl) */
case 7: /* DMAA ID (not impl) */
case 8: /* DMAB CMD (not impl) */
case 9: /* DMAB ID (not impl) */
case 0xa: /* DMAC CMD (not impl) */
case 0xb: /* DMAC ID (not impl) */
case 0xc: /* SBIS (not impl) */
return 0;
case 0xd: /* SBIER */
return sbi_er & SBIER_RD;
case 0xe: /* SBITA */
return sbi_tmo;
case 0xf: /* SBIFS */
return sbi_fs & SBIFS_RD;
case 0x10: /* SBISC */
return sbi_sc & SBISC_RD;
case 0x11: /* SBIMT */
return sbi_mt & SBIMT_RD;
default: /* Anything else is not impl */
return 0;
}
}
void sbia_wr (int32 pa, int32 val, int32 lnt)
{
int32 rg = (pa >> 2) & 0x1F;
switch (rg) {
case 0: /* SBICNF */
break;
case 1: /* SBICSR */
printf ("sbi_csr wr: %08X\n", val);
sbi_csr = sbi_csr & SBICSR_WR;
break;
case 2: /* SBIES (not impl) */
case 3: /* SBIDCR (not impl) */
case 4: /* DMAI CMD (not impl) */
case 5: /* DMAI ID (not impl) */
case 6: /* DMAA CMD (not impl) */
case 7: /* DMAA ID (not impl) */
case 8: /* DMAB CMD (not impl) */
case 9: /* DMAB ID (not impl) */
case 0xa: /* DMAC CMD (not impl) */
case 0xb: /* DMAC ID (not impl) */
case 0xc: /* SBIS (not impl) */
break;
case 0xd: /* SBIER */
sbi_er = (sbi_er & ~SBIER_WR) | (val & SBIER_WR);
sbi_er = sbi_er & ~(val & SBIER_W1C);
if (val & SBIER_TMO)
sbi_er = sbi_er & ~SBIER_TMOW1C;
if (val & SBIER_IBTMO)
sbi_er = sbi_er & ~SBIER_IBTW1C;
if ((sbi_er & SBIER_CRDIE) && (sbi_er & SBIER_CRD))
crd_err = 1;
else crd_err = 0;
break;
case 0xe: /* SBITA */
break;
case 0xf: /* SBIFS */
sbi_fs = (sbi_fs & ~SBIFS_WR) | (val & SBIFS_WR);
sbi_fs = sbi_fs & ~(val & SBIFS_W1C);
break;
case 0x10: /* SBISC */
sbi_sc = (sbi_sc & ~(SBISC_LOCK|SBISC_WR)) | (val & SBISC_WR);
break;
case 0x11: /* SBIMT */
sbi_mt = (sbi_mt & ~SBIMT_WR) | (val & SBIMT_WR);
break;
}
return;
}
t_stat sbi_rd (int32 pa, int32 *val, int32 lnt)
{
int32 nexus;
nexus = NEXUS_GETNEX (pa); /* get nexus */
if ((sbi_csr & SBICSR_SCOEN) && /* SBI en? */
nexusR[nexus] && /* valid? */
(nexusR[nexus] (val, pa, lnt) == SCPE_OK)) {
SET_IRQL;
return SCPE_OK;
}
else sbi_set_tmo (pa); /* timeout */
return SCPE_NXM;
}
t_stat sbi_wr (int32 pa, int32 val, int32 lnt)
{
int32 nexus;
nexus = NEXUS_GETNEX (pa); /* get nexus */
if ((sbi_csr & SBICSR_SCOEN) && /* SBI en? */
nexusW[nexus] && /* valid? */
(nexusW[nexus] (val, pa, lnt) == SCPE_OK)) {
SET_IRQL;
return SCPE_OK;
}
else sbi_set_tmo (pa); /* timeout */
return SCPE_NXM;
}
/* Set SBI timeout - machine checks only on reads */
void sbi_set_tmo (int32 pa)
{
if ((sbi_er & SBIER_TMO) == 0) { /* not yet set? */
sbi_tmo = pa >> 2; /* save addr */
if (mchk_ref == REF_V) /* virt? add mode */
sbi_tmo |= SBITMO_VIRT | (PSL_GETCUR (PSL) << SBITMO_V_MODE);
sbi_er |= SBIER_TMO; /* set tmo flag */
}
else sbi_er |= SBIER_MULT; /* yes, multiple */
return;
}
/* Set SBI error confirmation - always machine checks */
void sbi_set_errcnf (void)
{
if (sbi_er & SBIER_CNF)
sbi_er |= SBIER_MULT;
else sbi_er |= SBIER_CNF;
MACH_CHECK (MCHK_RD_F);
return;
}
/* SBI reset */
t_stat sbia_reset (DEVICE *dptr)
{
sbi_fs = 0;
sbi_sc = 0;
sbi_mt = 0;
sbi_er = 0;
sbi_tmo = 0;
sbi_csr = SBICSR_SCOEN | SBICSR_SCIEN;
return SCPE_OK;
}
/* Show nexus */
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc)
{
fprintf (st, "nexus=%d", val);
return SCPE_OK;
}
/* Init nexus tables */
void init_nexus_tab (void)
{
uint32 i;
for (i = 0; i < NEXUS_NUM; i++) {
nexusR[i] = NULL;
nexusW[i] = NULL;
}
return;
}
/* Build nexus tables
Inputs:
dptr = pointer to device
dibp = pointer to DIB
Outputs:
status
*/
t_stat build_nexus_tab (DEVICE *dptr, DIB *dibp)
{
uint32 idx;
if ((dptr == NULL) || (dibp == NULL))
return SCPE_IERR;
idx = dibp->ba;
if (idx >= NEXUS_NUM)
return SCPE_IERR;
if ((nexusR[idx] && dibp->rd && /* conflict? */
(nexusR[idx] != dibp->rd)) ||
(nexusW[idx] && dibp->wr &&
(nexusW[idx] != dibp->wr))) {
printf ("Nexus %s conflict at %d\n", sim_dname (dptr), dibp->ba);
if (sim_log)
fprintf (sim_log, "Nexus %s conflict at %d\n", sim_dname (dptr), dibp->ba);
return SCPE_STOP;
}
if (dibp->rd) /* set rd dispatch */
nexusR[idx] = dibp->rd;
if (dibp->wr) /* set wr dispatch */
nexusW[idx] = dibp->wr;
return SCPE_OK;
}

1154
VAX/vax860_stddev.c Normal file
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File diff suppressed because it is too large Load diff

130
VAX/vax860_syslist.c Normal file
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@ -0,0 +1,130 @@
/* vax860_syslist.c: VAX 8600 device list
Copyright (c) 2011-2012, Matt Burke
This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name(s) of the author(s) shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the author(s).
26-Dec-2012 MB First version
*/
#include "vax_defs.h"
char sim_name[] = "VAX860";
extern DEVICE cpu_dev;
extern DEVICE tlb_dev;
extern DEVICE abus_dev;
extern DEVICE sbia_dev;
extern DEVICE uba_dev;
extern DEVICE mba_dev[MBA_NUM];
extern DEVICE clk_dev;
extern DEVICE tmr_dev;
extern DEVICE tti_dev, tto_dev;
extern DEVICE rlcs_dev;
extern DEVICE cr_dev;
extern DEVICE lpt_dev;
extern DEVICE rq_dev, rqb_dev, rqc_dev, rqd_dev;
extern DEVICE rl_dev;
extern DEVICE hk_dev;
extern DEVICE rp_dev;
extern DEVICE ry_dev;
extern DEVICE ts_dev;
extern DEVICE tq_dev;
extern DEVICE tu_dev;
extern DEVICE dz_dev;
extern DEVICE xu_dev, xub_dev;
extern DEVICE dmc_dev[];
extern int32 sim_switches;
extern UNIT cpu_unit;
extern void WriteB (uint32 pa, int32 val);
DEVICE *sim_devices[] = {
&cpu_dev,
&tlb_dev,
&abus_dev,
&sbia_dev,
&uba_dev,
&mba_dev[0],
&mba_dev[1],
&clk_dev,
&tmr_dev,
&tti_dev,
&tto_dev,
&rlcs_dev,
&dz_dev,
&cr_dev,
&lpt_dev,
&rp_dev,
&rl_dev,
&hk_dev,
&rq_dev,
&rqb_dev,
&rqc_dev,
&rqd_dev,
&ry_dev,
&tu_dev,
&ts_dev,
&tq_dev,
&xu_dev,
&xub_dev,
&dmc_dev[0],
&dmc_dev[1],
&dmc_dev[2],
&dmc_dev[3],
NULL
};
/* Binary loader
The binary loader handles absolute system images, that is, system
images linked /SYSTEM. These are simply a byte stream, with no
origin or relocation information.
-o for memory, specify origin
*/
t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
t_stat r;
int32 val;
uint32 origin, limit;
if (flag) /* dump? */
return SCPE_ARG;
origin = 0; /* memory */
limit = (uint32) cpu_unit.capac;
if (sim_switches & SWMASK ('O')) { /* origin? */
origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r);
if (r != SCPE_OK)
return SCPE_ARG;
}
while ((val = getc (fileref)) != EOF) { /* read byte stream */
if (origin >= limit) /* NXM? */
return SCPE_NXM;
WriteB (origin, val); /* memory */
origin = origin + 1;
}
return SCPE_OK;
}

4
VAX/vax_cpu1.c
View file

@ -1445,7 +1445,7 @@ int32 cc;
if (PSL & PSL_CUR) /* must be kernel */
RSVD_INST_FAULT;
if (prn > 63) /* reg# > 63? fault */
if (prn > MT_MAX) /* reg# > max? fault */
RSVD_OPND_FAULT;
CC_IIZZ_L (val); /* set cc's */
switch (prn) { /* case on reg # */
@ -1576,7 +1576,7 @@ int32 val;
if (PSL & PSL_CUR) /* must be kernel */
RSVD_INST_FAULT;
if (prn > 63) /* reg# > 63? fault */
if (prn > MT_MAX) /* reg# > max? fault */
RSVD_OPND_FAULT;
switch (prn) { /* case on reg# */

2
VAX/vax_defs.h
View file

@ -738,6 +738,8 @@ void cpu_idle (void);
#include "vax610_defs.h"
#elif defined (VAX_620) || defined (VAX_630)
#include "vax630_defs.h"
#elif defined (VAX_860)
#include "vax860_defs.h"
#else /* VAX 3900 */
#include "vaxmod_defs.h"
#endif

1
VAX/vaxmod_defs.h
View file

@ -96,6 +96,7 @@
#define MT_CONPC 42
#define MT_CONPSL 43
#define MT_IORESET 55
#define MT_MAX 63 /* last valid IPR */
/* Memory system error register */

9
Visual Studio Projects/Simh.sln
View file

@ -92,6 +92,11 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAX630", "VAX630.vcproj", "
EndProject
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "TX-0", "TX-0.vcproj", "{24BC7F75-FB56-44A9-BB7C-78AE6A694D0C}"
EndProject
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAX860", "VAX860.vcproj", "{F5C22D72-460E-43CD-9AC6-6D6AC517BD1F}"
ProjectSection(ProjectDependencies) = postProject
{D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8}
EndProjectSection
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|Win32 = Debug|Win32
@ -238,6 +243,10 @@ Global
{24BC7F75-FB56-44A9-BB7C-78AE6A694D0C}.Debug|Win32.Build.0 = Debug|Win32
{24BC7F75-FB56-44A9-BB7C-78AE6A694D0C}.Release|Win32.ActiveCfg = Release|Win32
{24BC7F75-FB56-44A9-BB7C-78AE6A694D0C}.Release|Win32.Build.0 = Release|Win32
{F5C22D72-460E-43CD-9AC6-6D6AC517BD1F}.Debug|Win32.ActiveCfg = Debug|Win32
{F5C22D72-460E-43CD-9AC6-6D6AC517BD1F}.Debug|Win32.Build.0 = Debug|Win32
{F5C22D72-460E-43CD-9AC6-6D6AC517BD1F}.Release|Win32.ActiveCfg = Release|Win32
{F5C22D72-460E-43CD-9AC6-6D6AC517BD1F}.Release|Win32.Build.0 = Release|Win32
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE

479
Visual Studio Projects/VAX860.vcproj Normal file
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@ -0,0 +1,479 @@
<?xml version="1.0" encoding="Windows-1252"?>
<VisualStudioProject
ProjectType="Visual C++"
Version="9.00"
Name="VAX860"
ProjectGUID="{F5C22D72-460E-43CD-9AC6-6D6AC517BD1F}"
RootNamespace="VAX860"
Keyword="Win32Proj"
TargetFrameworkVersion="131072"
>
<Platforms>
<Platform
Name="Win32"
/>
</Platforms>
<ToolFiles>
</ToolFiles>
<Configurations>
<Configuration
Name="Debug|Win32"
OutputDirectory="..\BIN\NT\$(PlatformName)-$(ConfigurationName)"
IntermediateDirectory="..\BIN\NT\Project\simh\VAX860\$(PlatformName)-$(ConfigurationName)"
ConfigurationType="1"
InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"
CharacterSet="0"
>
<Tool
Name="VCPreBuildEventTool"
Description="Build Dependent ROM include File(s) &amp; Check for required build dependencies"
CommandLine="pushd ..&#x0D;&#x0A;&quot;$(TargetDir)BuildROMs&quot;&#x0D;&#x0A;popd&#x0D;&#x0A;&#x0D;&#x0A;if not exist ../../windows-build/winpcap/Wpdpack/Include/pcap.h goto _notice&#x0D;&#x0A;if not exist ../../windows-build/pthreads/pthread.h goto _notice&#x0D;&#x0A;goto _good&#x0D;&#x0A;&#x0D;&#x0A;:_notice&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo ** The required build support is not available. **&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;type 0ReadMe_Projects.txt&#x0D;&#x0A;exit 1&#x0D;&#x0A;&#x0D;&#x0A;:_good&#x0D;&#x0A;"
/>
<Tool
Name="VCCustomBuildTool"
/>
<Tool
Name="VCXMLDataGeneratorTool"
/>
<Tool
Name="VCWebServiceProxyGeneratorTool"
/>
<Tool
Name="VCMIDLTool"
/>
<Tool
Name="VCCLCompilerTool"
Optimization="0"
AdditionalIncludeDirectories="./;../;../VAX/;../pdp11/;&quot;../../windows-build/winpcap/Wpdpack/Include&quot;;&quot;../../windows-build/pthreads&quot;"
PreprocessorDefinitions="USE_INT64;USE_ADDR64;VM_VAX;VAX_860;USE_SHARED;_CRT_NONSTDC_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;PTW32_STATIC_LIB;USE_READER_THREAD;SIM_ASYNCH_IO"
MinimalRebuild="true"
BasicRuntimeChecks="0"
RuntimeLibrary="1"
UsePrecompiledHeader="0"
WarningLevel="3"
Detect64BitPortabilityProblems="false"
DebugInformationFormat="3"
CompileAs="1"
ShowIncludes="false"
/>
<Tool
Name="VCManagedResourceCompilerTool"
/>
<Tool
Name="VCResourceCompilerTool"
/>
<Tool
Name="VCPreLinkEventTool"
/>
<Tool
Name="VCLinkerTool"
AdditionalOptions="/fixed:no"
AdditionalDependencies="wpcap.lib packet.lib wsock32.lib winmm.lib"
OutputFile="$(OutDir)\VAX860.exe"
LinkIncremental="1"
AdditionalLibraryDirectories="&quot;../../windows-build/winpcap/Wpdpack/Lib/&quot;"
GenerateDebugInformation="true"
ProgramDatabaseFile="$(OutDir)\VAX860.pdb"
SubSystem="1"
RandomizedBaseAddress="1"
DataExecutionPrevention="0"
TargetMachine="1"
/>
<Tool
Name="VCALinkTool"
/>
<Tool
Name="VCManifestTool"
/>
<Tool
Name="VCXDCMakeTool"
/>
<Tool
Name="VCBscMakeTool"
/>
<Tool
Name="VCFxCopTool"
/>
<Tool
Name="VCAppVerifierTool"
/>
<Tool
Name="VCPostBuildEventTool"
/>
</Configuration>
<Configuration
Name="Release|Win32"
OutputDirectory="..\BIN\NT\$(PlatformName)-$(ConfigurationName)"
IntermediateDirectory="..\BIN\NT\Project\simh\VAX860\$(PlatformName)-$(ConfigurationName)"
ConfigurationType="1"
InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"
CharacterSet="0"
>
<Tool
Name="VCPreBuildEventTool"
Description="Build Dependent ROM include File(s) &amp; Check for required build dependencies"
CommandLine="pushd ..&#x0D;&#x0A;&quot;$(TargetDir)BuildROMs&quot;&#x0D;&#x0A;popd&#x0D;&#x0A;&#x0D;&#x0A;if not exist ../../windows-build/winpcap/Wpdpack/Include/pcap.h goto _notice&#x0D;&#x0A;if not exist ../../windows-build/pthreads/pthread.h goto _notice&#x0D;&#x0A;goto _good&#x0D;&#x0A;&#x0D;&#x0A;:_notice&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo ** The required build support is not available. **&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;type 0ReadMe_Projects.txt&#x0D;&#x0A;exit 1&#x0D;&#x0A;&#x0D;&#x0A;:_good&#x0D;&#x0A;"
/>
<Tool
Name="VCCustomBuildTool"
/>
<Tool
Name="VCXMLDataGeneratorTool"
/>
<Tool
Name="VCWebServiceProxyGeneratorTool"
/>
<Tool
Name="VCMIDLTool"
/>
<Tool
Name="VCCLCompilerTool"
Optimization="2"
InlineFunctionExpansion="2"
EnableIntrinsicFunctions="true"
FavorSizeOrSpeed="1"
OmitFramePointers="true"
WholeProgramOptimization="true"
AdditionalIncludeDirectories="./;../;../VAX/;../pdp11/;&quot;../../windows-build/winpcap/Wpdpack/Include&quot;;&quot;../../windows-build/pthreads&quot;"
PreprocessorDefinitions="USE_INT64;USE_ADDR64;VM_VAX;VAX_860;USE_SHARED;_CRT_NONSTDC_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;PTW32_STATIC_LIB;USE_READER_THREAD;SIM_ASYNCH_IO"
StringPooling="true"
RuntimeLibrary="0"
BufferSecurityCheck="false"
EnableFunctionLevelLinking="true"
UsePrecompiledHeader="0"
WarningLevel="3"
Detect64BitPortabilityProblems="false"
DebugInformationFormat="3"
CompileAs="1"
/>
<Tool
Name="VCManagedResourceCompilerTool"
/>
<Tool
Name="VCResourceCompilerTool"
/>
<Tool
Name="VCPreLinkEventTool"
/>
<Tool
Name="VCLinkerTool"
AdditionalOptions="/fixed:no"
AdditionalDependencies="wpcap.lib packet.lib wsock32.lib winmm.lib"
OutputFile="$(OutDir)\VAX860.exe"
LinkIncremental="1"
AdditionalLibraryDirectories="&quot;../../windows-build/winpcap/Wpdpack/Lib/&quot;"
GenerateDebugInformation="true"
SubSystem="1"
OptimizeReferences="2"
EnableCOMDATFolding="2"
LinkTimeCodeGeneration="1"
RandomizedBaseAddress="1"
DataExecutionPrevention="0"
TargetMachine="1"
/>
<Tool
Name="VCALinkTool"
/>
<Tool
Name="VCManifestTool"
/>
<Tool
Name="VCXDCMakeTool"
/>
<Tool
Name="VCBscMakeTool"
/>
<Tool
Name="VCFxCopTool"
/>
<Tool
Name="VCAppVerifierTool"
/>
<Tool
Name="VCPostBuildEventTool"
/>
</Configuration>
</Configurations>
<References>
</References>
<Files>
<Filter
Name="Source Files"
Filter="cpp;c;cxx;def;odl;idl;hpj;bat;asm"
>
<File
RelativePath="..\PDP11\pdp11_cr.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_dmc.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_dz.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_hk.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_io_lib.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_lp.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_pt.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_rl.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_rp.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_rq.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_ry.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_tq.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_ts.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_tu.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_vh.c"
>
</File>
<File
RelativePath="..\PDP11\pdp11_xu.c"
>
</File>
<File
RelativePath="..\..\windows-build\pthreads\pthread.c"
>
<FileConfiguration
Name="Debug|Win32"
>
<Tool
Name="VCCLCompilerTool"
PreprocessorDefinitions="HAVE_PTW32_CONFIG_H;PTW32_BUILD_INLINED;PTW32_STATIC_LIB;__CLEANUP_C;$(NOINHERIT)"
/>
</FileConfiguration>
<FileConfiguration
Name="Release|Win32"
>
<Tool
Name="VCCLCompilerTool"
WholeProgramOptimization="false"
PreprocessorDefinitions="HAVE_PTW32_CONFIG_H;PTW32_BUILD_INLINED;PTW32_STATIC_LIB;__CLEANUP_C;$(NOINHERIT)"
/>
</FileConfiguration>
</File>
<File
RelativePath="..\scp.c"
>
</File>
<File
RelativePath="..\sim_console.c"
>
</File>
<File
RelativePath="..\sim_disk.c"
>
</File>
<File
RelativePath="..\sim_ether.c"
>
</File>
<File
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
</File>
<File
RelativePath="..\sim_tape.c"
>
</File>
<File
RelativePath="..\sim_timer.c"
>
</File>
<File
RelativePath="..\sim_tmxr.c"
>
</File>
<File
RelativePath="..\VAX\vax860_abus.c"
>
</File>
<File
RelativePath="..\VAX\vax860_sbia.c"
>
</File>
<File
RelativePath="..\VAX\vax860_stddev.c"
>
</File>
<File
RelativePath="..\VAX\vax860_syslist.c"
>
</File>
<File
RelativePath="..\VAX\vax780_uba.c"
>
</File>
<File
RelativePath="..\VAX\vax7x0_mba.c"
>
</File>
<File
RelativePath="..\VAX\vax_cis.c"
>
</File>
<File
RelativePath="..\VAX\vax_cmode.c"
>
</File>
<File
RelativePath="..\VAX\vax_cpu.c"
>
</File>
<File
RelativePath="..\VAX\vax_cpu1.c"
>
</File>
<File
RelativePath="..\VAX\vax_fpa.c"
>
</File>
<File
RelativePath="..\VAX\vax_mmu.c"
>
</File>
<File
RelativePath="..\VAX\vax_octa.c"
>
</File>
<File
RelativePath="..\VAX\vax_sys.c"
>
</File>
<File
RelativePath="..\VAX\vax_syscm.c"
>
</File>
</Filter>
<Filter
Name="Header Files"
Filter="h;hpp;hxx;hm;inl;inc"
>
<File
RelativePath="..\PDP11\pdp11_dmc.h"
>
</File>
<File
RelativePath="..\PDP11\pdp11_io_lib.h"
>
</File>
<File
RelativePath="..\PDP11\pdp11_mscp.h"
>
</File>
<File
RelativePath="..\PDP11\pdp11_uqssp.h"
>
</File>
<File
RelativePath="..\PDP11\pdp11_xu.h"
>
</File>
<File
RelativePath="..\scp.h"
>
</File>
<File
RelativePath="..\sim_console.h"
>
</File>
<File
RelativePath="..\sim_defs.h"
>
</File>
<File
RelativePath="..\sim_disk.h"
>
</File>
<File
RelativePath="..\sim_ether.h"
>
</File>
<File
RelativePath="..\sim_fio.h"
>
</File>
<File
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>
</File>
<File
RelativePath="..\sim_tape.h"
>
</File>
<File
RelativePath="..\sim_timer.h"
>
</File>
<File
RelativePath="..\sim_tmxr.h"
>
</File>
<File
RelativePath="..\VAX\vax860_defs.h"
>
</File>
<File
RelativePath="..\VAX\vax_defs.h"
>
</File>
</Filter>
<Filter
Name="Resource Files"
Filter="rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe"
>
</Filter>
</Files>
<Globals>
</Globals>
</VisualStudioProject>

2
display/win32.c
View file

@ -278,7 +278,7 @@ ws_init2(void) {
}
#ifdef THREADS
static volatile init_done;
static volatile int init_done;
static DWORD msgthread_id;
static DWORD WINAPI

BIN
doc/pdp10_doc.doc
View file

Binary file not shown.

32
makefile
View file

@ -302,7 +302,11 @@ ifeq ($(WIN32),) #*nix Environments (&& cygwin)
else
#Win32 Environments (via MinGW32)
GCC = gcc
GCC_Path := $(dir $(shell where gcc.exe))
ifeq (XP,$(findstring XP,$(shell ver)))
GCC_Path := C:\MinGW\bin\
else
GCC_Path := $(dir $(shell where gcc.exe))
endif
GCC_VERSION = $(word 3,$(shell $(GCC) --version))
COMPILER_NAME = GCC Version: $(GCC_VERSION)
LTO_EXCLUDE_VERSIONS = 4.5.2
@ -529,6 +533,7 @@ VAX630 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \
VAX620_OPT = -DVM_VAX -DVAX_620 -DUSE_INT64 -DUSE_ADDR64 -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT}
VAX630_OPT = -DVM_VAX -DVAX_630 -DUSE_INT64 -DUSE_ADDR64 -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT}
VAX730 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \
${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \
${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \
@ -571,6 +576,20 @@ VAX780 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \
VAX780_OPT = -DVM_VAX -DVAX_780 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT}
VAX860 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \
${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \
${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \
${VAXD}/vax860_stddev.c ${VAXD}/vax860_sbia.c \
${VAXD}/vax860_abus.c ${VAXD}/vax780_uba.c ${VAXD}/vax7x0_mba.c \
${VAXD}/vax860_syslist.c \
${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \
${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \
${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \
${PDP11D}/pdp11_rp.c ${PDP11D}/pdp11_tu.c ${PDP11D}/pdp11_hk.c \
${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_dmc.c ${PDP11D}/pdp11_io_lib.c
VAX860_OPT = -DVM_VAX -DVAX_860 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT}
PDP10D = PDP10
PDP10 = ${PDP10D}/pdp10_fe.c ${PDP11D}/pdp11_dz.c ${PDP10D}/pdp10_cpu.c \
${PDP10D}/pdp10_ksio.c ${PDP10D}/pdp10_lp20.c ${PDP10D}/pdp10_mdfp.c \
@ -581,7 +600,6 @@ PDP10 = ${PDP10D}/pdp10_fe.c ${PDP11D}/pdp11_dz.c ${PDP10D}/pdp10_cpu.c \
PDP10_OPT = -DVM_PDP10 -DUSE_INT64 -I ${PDP10D} -I ${PDP11D}
PDP8D = PDP8
PDP8 = ${PDP8D}/pdp8_cpu.c ${PDP8D}/pdp8_clk.c ${PDP8D}/pdp8_df.c \
${PDP8D}/pdp8_dt.c ${PDP8D}/pdp8_lp.c ${PDP8D}/pdp8_mt.c \
@ -729,7 +747,7 @@ ifeq ($(WIN32),)
DISPLAY_OPT =
endif
else
DISPLAYL = ${DISPLAYD}/display.c $(DISPLAYD)/w32.c
DISPLAYL = ${DISPLAYD}/display.c $(DISPLAYD)/win32.c
DISPLAY_OPT = -DUSE_DISPLAY
endif
@ -743,7 +761,7 @@ TX0_OPT = -I ${TX0D} $(DISPLAY_OPT)
# Build everything
#
ALL = pdp1 pdp4 pdp7 pdp8 pdp9 pdp15 pdp11 pdp10 \
vax vax610 vax620 vax630 vax730 vax750 vax780 \
vax vax610 vax620 vax630 vax730 vax750 vax780 vax860 \
nova eclipse hp2100 i1401 i1620 s3 altair altairz80 gri \
i7094 ibm1130 id16 id32 sds lgp h316 \
swtp6800mp-a swtp6800mp-a2 tx-0
@ -869,6 +887,12 @@ ${BIN}vax780${EXE} : ${VAX780} ${SIM} ${BUILD_ROMS}
${MKDIRBIN}
${CC} ${VAX780} ${SIM} ${VAX780_OPT} $(CC_OUTSPEC) ${LDFLAGS}
vax860 : ${BIN}vax860${EXE}
${BIN}vax860${EXE} : ${VAX860} ${SIM} ${BUILD_ROMS}
${MKDIRBIN}
${CC} ${VAX860} ${SIM} ${VAX860_OPT} $(CC_OUTSPEC) ${LDFLAGS}
nova : ${BIN}nova${EXE}
${BIN}nova${EXE} : ${NOVA} ${SIM}

3
scp.c
View file

@ -2315,6 +2315,9 @@ if (cptr && (*cptr != 0))
fprintf (st, "%s simulator V%d.%d-%d", sim_name, vmaj, vmin, vpat);
if (vdelt)
fprintf (st, " delta %d", vdelt);
#if defined(SIM_VERSION_MODE)
fprintf (st, " %s", SIM_VERSION_MODE);
#endif
if (flag)
fprintf (st, " [%s, %s, %s]", sim_si64, sim_sa64, sim_snet);
#if defined(SIM_GIT_COMMIT_ID)

12
sim_rev.h
View file

@ -27,10 +27,22 @@
#ifndef _SIM_REV_H_
#define _SIM_REV_H_ 0
#ifndef SIM_MAJOR
#define SIM_MAJOR 4
#endif
#ifndef SIM_MINOR
#define SIM_MINOR 0
#endif
#ifndef SIM_PATCH
#define SIM_PATCH 0
#endif
#ifndef SIM_DELTA
#define SIM_DELTA 0
#endif
#ifndef SIM_VERSION_MODE
#define SIM_VERSION_MODE "Beta"
#endif
/*
The comment section below reflects the manual editing process which was in place

9
sim_serial.c
View file

@ -897,6 +897,15 @@ for (i=0; (ports < max) && (i < 64); ++i) {
close (port);
}
}
for (i=0; (ports < max) && (i < 64); ++i) {
sprintf (list[ports].name, "/dev/ttyAMA%d", i);
port = open (list[ports].name, O_RDWR | O_NOCTTY | O_NONBLOCK); /* open the port */
if (port != -1) { /* open OK? */
if (isatty (port)) /* is device a TTY? */
++ports;
close (port);
}
}
for (i=1; (ports < max) && (i < 64); ++i) {
sprintf (list[ports].name, "/dev/tty.serial%d", i);
port = open (list[ports].name, O_RDWR | O_NOCTTY | O_NONBLOCK); /* open the port */

10
sim_tmxr.c
View file

@ -783,6 +783,8 @@ for (i = 0; i < mp->lines; i++) { /* check each line in se
lp->conn = TRUE; /* record connection */
lp->sock = lp->connecting; /* it now looks normal */
lp->connecting = 0;
lp->ipad = realloc (lp->ipad, 1+strlen (lp->destination));
strcpy (lp->ipad, lp->destination);
lp->cnms = sim_os_msec ();
break;
case -1: /* failed connection */
@ -901,14 +903,8 @@ if ((lp->destination) && (!lp->serport)) {
if (lp->connecting)
sim_close_sock (lp->connecting, 0);
lp->connecting = sim_connect_sock (lp->destination, "localhost", NULL);
lp->ipad = malloc (1 + strlen (lp->destination));
strcpy (lp->ipad, lp->destination);
lp->cnms = sim_os_msec ();
}
else {
tmxr_init_line (lp); /* initialize line state */
}
lp->conn = FALSE; /* remove connection flag */
tmxr_init_line (lp); /* initialize line state */
/* Revise the unit's connect string to reflect the current attachments */
lp->mp->uptr->filename = _mux_attach_string (lp->mp->uptr->filename, lp->mp);
/* No connections or listeners exist, then we're equivalent to being fully detached. We should reflect that */