From 45d8c908ba1f153522d9575e373599f1ff19bae8 Mon Sep 17 00:00:00 2001
From: Mark Pizzolato <mark@infocomm.com>
Date: Wed, 29 May 2019 00:44:17 -0700
Subject: [PATCH] PDP10: Leverage the internal calibrated timer for accurate
 wall clock timing

Avoid the common situation on with this simulator whereby the programmatic
interval timer is being used for intervals which change often.  The internal
calibrated timing routines depend on consistent rate for the calibrated device.

As discussed in #699
---
 PDP10/pdp10_cpu.c | 2 --
 PDP10/pdp10_tim.c | 7 +++----
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/PDP10/pdp10_cpu.c b/PDP10/pdp10_cpu.c
index 30b8bb50..a37c8070 100644
--- a/PDP10/pdp10_cpu.c
+++ b/PDP10/pdp10_cpu.c
@@ -2198,8 +2198,6 @@ if (ea & APR_SENB)                                      /* set enables? */
 if (ea & APR_CENB)                                      /* clear enables? */
     apr_enb = apr_enb & ~bits;
 if (ea & APR_CFLG) {                                    /* clear flags? */
-    if ((bits & APRF_TIM) && (apr_flg & APRF_TIM))
-        sim_rtcn_tick_ack (30, 0);
     apr_flg = apr_flg & ~bits;
     }
 if (ea & APR_SFLG)                                      /* set flags? */
diff --git a/PDP10/pdp10_tim.c b/PDP10/pdp10_tim.c
index 71422f7a..4b585145 100644
--- a/PDP10/pdp10_tim.c
+++ b/PDP10/pdp10_tim.c
@@ -340,10 +340,10 @@ if (cpu_unit.flags & UNIT_KLAD) {                       /* diags? */
     sim_activate (uptr, tmr_poll);                          /* reactivate unit */
     }
 else {
-    tmr_poll = sim_rtc_calb (clk_tps);                  /* else calibrate */
     sim_activate_after (uptr, 1000000/clk_tps);         /* reactivate unit */
+    tmr_poll = sim_activate_time (uptr) - 1;
     }
-tmxr_poll = tmr_poll * tim_mult;                        /* set mux poll */
+tmxr_poll = (int32)(sim_timer_inst_per_sec () / clk_tps);/* set mux poll */
 tim_incr_base (tim_base, tim_period);                   /* incr time base based on period of expired interval */
 tim_period = tim_new_period;                            /* If interval has changed, update period */
 apr_flg = apr_flg | APRF_TIM;                           /* request interrupt */
@@ -373,7 +373,6 @@ return;
 static t_stat tim_reset (DEVICE *dptr)
 {
 sim_debug (DEB_TRC, &tim_dev, "tim_reset()\n");
-sim_register_clock_unit (&tim_unit);                    /* declare clock unit */
 
 tim_base[0] = tim_base[1] = 0;                          /* clear timebase (HW does) */
 /* HW does not initialize the interval timer, so the rate at which the timer flag
@@ -391,10 +390,10 @@ tim_interval = 0;
 clk_tps = 60;
 sim_debug (DEB_TPS, &tim_dev, "tim_reset() - clk_tps set to %d\n", clk_tps);
 update_interval(17*4096);
+tmr_poll = (int32)(20000 * ((double)sim_rand () / (double)RAND_MAX));
 
 apr_flg = apr_flg & ~APRF_TIM;                          /* clear interrupt */
 
-tmr_poll = sim_rtc_init (tim_unit.wait);                /* init timer */
 sim_activate (&tim_unit, tmr_poll);                     /* activate unit */
 tmxr_poll = tmr_poll * tim_mult;                        /* set mux poll */
 return SCPE_OK;