diff --git a/VAX/vax_sysdev.c b/VAX/vax_sysdev.c
index addb5b89..03593736 100644
--- a/VAX/vax_sysdev.c
+++ b/VAX/vax_sysdev.c
@@ -478,15 +478,15 @@ REG sysd_reg[] = {
     { HRDATAD (CACR,   ka_cacr,      8, "second-level cache control register") },
     { HRDATAD (BDR,    ka_bdr,       8, "front panel jumper register") },
     { HRDATAD (BASE,   ssc_base,    29, "SSC base address register") },
-    { HRDATAD (CNF,    ssc_cnf,     32, "SSC configuration register") },
+    { HRDATADF (CNF,   ssc_cnf,     32, "SSC configuration register", ssc_cnf_bits) },
     { HRDATAD (BTO,    ssc_bto,     32, "SSC bus timeout register") },
     { HRDATAD (OTP,    ssc_otp,      4, "SSC output port") },
-    { HRDATAD (TCSR0,  tmr_csr[0],  32, "SSC timer 0 control/status register") },
+    { HRDATADF (TCSR0, tmr_csr[0],  32, "SSC timer 0 control/status register", tmr_csr_bits) },
     { HRDATAD (TIR0,   tmr_tir[0],  32, "SSC timer 0 interval register") },
     { HRDATAD (TNIR0,  tmr_tnir[0], 32, "SSC timer 0 next interval register") },
     { HRDATAD (TIVEC0, tmr_tivr[0],  9, "SSC timer 0 interrupt vector register") },
     { FLDATAD (TINST0, tmr_inst[0],  0, "SSC timer 0 last wait instructions") },
-    { HRDATAD (TCSR1,  tmr_csr[1],  32, "SSC timer 1 control/status register") },
+    { HRDATADF (TCSR1, tmr_csr[1],  32, "SSC timer 1 control/status register", tmr_csr_bits) },
     { HRDATAD (TIR1,   tmr_tir[1],  32, "SSC timer 1 interval register") },
     { HRDATAD (TNIR1,  tmr_tnir[1], 32, "SSC timer 1 next interval register") },
     { HRDATAD (TIVEC1, tmr_tivr[1],  9, "SSC timer 1 interrupt vector register") },