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All VAX, PDP11, PDP10: Minor fixes to DZ device

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Matt Burke 2017-04-26 15:34:01 -07:00 • committed by Mark Pizzolato
parent f6d4e92c6d
commit 4b41b3372f
1 changed files with 4 additions and 2 deletions
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6
PDP11/pdp11_dz.c
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@ -114,6 +114,7 @@
BITFIELD dz_csr_bits[] = { BITFIELD dz_csr_bits[] = {
BITNCF(3), /* not used */ BITNCF(3), /* not used */
BIT(MAINT), /* Maint */ BIT(MAINT), /* Maint */
BIT(CLR), /* clear */
BIT(MSE), /* naster scan enable */ BIT(MSE), /* naster scan enable */
BIT(RIE), /* receive interrupt enable */ BIT(RIE), /* receive interrupt enable */
BIT(RDONE), /* receive done */ BIT(RDONE), /* receive done */
@ -211,8 +212,8 @@ BITFIELD dz_msr_bits[] = {
#define TDR_V_TBR 8 /* xmit break - NI */ #define TDR_V_TBR 8 /* xmit break - NI */
BITFIELD dz_tdr_bits[] = { BITFIELD dz_tdr_bits[] = {
BITFFMT(CHAR,8,%02X), /* ring indicators */ BITFFMT(CHAR,8,%02X), /* xmit char */
BITFFMT(TBR, 8,%02X), /* carrier detects */ BITFFMT(TBR, 8,%02X), /* xmit break - NI */
ENDBITS ENDBITS
}; };
@ -751,6 +752,7 @@ sim_debug(DBG_TRC, &dz_dev, "dz_clear(dz=%d,flag=%d)\n", dz, flag);
dz_csr[dz] = 0; /* clear CSR */ dz_csr[dz] = 0; /* clear CSR */
dz_rbuf[dz] = 0; /* silo empty */ dz_rbuf[dz] = 0; /* silo empty */
dz_scnt[dz] = 0;
dz_lpr[dz] = 0; /* no params */ dz_lpr[dz] = 0; /* no params */
if (flag) /* INIT? clr all */ if (flag) /* INIT? clr all */
dz_tcr[dz] = 0; dz_tcr[dz] = 0;